JP2008145560A - Plasma display device and method of driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a stable write discharge without raising a voltage required for generating the write discharge. <P>SOLUTION: A plasma display device includes: a plasma display panel having a plurality of discharge cells each having a display electrode pair comprising a scan electrode and a sustain electrode; a driving circuit which drives respective electrodes by providing, in a one-field period, a plurality of subfields each having a write period wherein a discharge cell for making a discharge is selected and a sustain period where the discharge cell selected in the write period generates a sustain discharge; and a panel temperature decision circuit which has a temperature sensor and decides the temperature state of the plasma display panel. After applying a sustain pulse voltage for generating a final sustain discharge in a sustain period to a scan electrode, the driving circuit applies a voltage for reducing the potential difference between the electrodes of the display electrode pair to the sustain electrode at predetermined intervals, and varies the predetermined interval according to a signal from the panel temperature decision circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a plasma display device and a plasma display panel driving method used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon in a partial pressure ratio is sealed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, wall charges necessary for the subsequent address operation are formed on each electrode, and priming particles for stably generating the address discharge (priming agent for discharge = excited particles) ). In the address period, an address pulse voltage is selectively applied to the discharge cells to be displayed to generate an address discharge to form wall charges (hereinafter, this operation is also referred to as “address”). In the sustain period, a sustain pulse voltage is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell emits light. To display an image.

  In addition, among the subfield methods, initializing discharge is performed using a slowly changing voltage waveform, and further, initializing discharge is selectively performed on discharge cells that have undergone sustain discharge. A driving method is disclosed in which light emission that is not generated is reduced as much as possible to improve the contrast ratio.

  In this driving method, for example, among the plurality of subfields, an initialization operation (hereinafter referred to as “all-cell initialization operation”) in which initialization discharge is generated in all discharge cells in the initialization period of one subfield. In the initializing period of the other subfield, an initializing operation (hereinafter abbreviated as “selective initializing operation”) for generating an initializing discharge only in the discharge cells in which the sustain discharge has been performed is performed. By driving in this way, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation, and the luminance of the black display area (hereinafter abbreviated as “black luminance”) is the initial value of all cells. Only weak light emission in the digitizing operation is possible, and high-contrast image display is possible (for example, see Patent Document 1).

In the above-mentioned Patent Document 1, the pulse width of the last sustain pulse in the sustain period is made shorter than the pulse widths of the other sustain pulses, and so-called narrow erasure is performed to alleviate the potential difference due to wall charges between the display electrode pairs. It also describes the discharge. By stably generating this narrow erase discharge, a reliable address operation can be performed in the address period of the subsequent subfield, and a plasma display device with a high contrast ratio can be realized.
JP 2000-242224 A

  In recent years, it has been desired to further improve the display quality of the plasma display device as the panel becomes higher in definition, larger in screen, and higher in brightness. On the other hand, in a panel with high definition, large screen, and high brightness, the address discharge becomes unstable, and no address discharge occurs in the discharge cells to be displayed (hereinafter, such discharge cells are referred to as “ The problem has arisen that the voltage necessary for degrading the image display quality or generating the address discharge has increased.

  The present invention has been made in view of such a problem, and even in a panel with high definition, large screen, and high brightness, it is stable without increasing the voltage necessary for generating address discharge. An object of the present invention is to provide a plasma display device and a panel driving method capable of generating the address discharge and improving the image display quality.

  A plasma display device according to the present invention includes a panel including a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode, an address period for selecting a discharge cell to be discharged, and a discharge cell selected in the address period A driving circuit for driving a panel by providing a plurality of subfields having a sustain period for generating a sustain discharge of the number corresponding to the luminance weight in one field period, and a panel having a temperature sensor for determining the temperature state of the panel A temperature determination circuit, and the drive circuit collects the electric power accumulated in the interelectrode capacitance of the display electrode pair and supplies the collected electric power to the display electrode pair, and each of the display electrode pair is set to the power supply voltage. Sustain pulse generation circuit having a switching element to be clamped and a clamp portion having a switching element to be clamped to a base potential, and a display electrode And a switching element for applying a voltage for relaxing the potential difference between the electrodes to the display electrode pair, and a sustain pulse voltage that is displaced from a base potential to a potential for generating a sustain discharge during the sustain period is alternately applied to the display electrode pair. In order to alleviate the potential difference between the electrodes of the display electrode pair after a predetermined time interval after applying a sustain pulse voltage for generating the last sustain discharge in the sustain period to the scan electrodes. This voltage is applied to the sustain electrode, and the predetermined time interval is changed according to a signal from the panel temperature determination circuit.

  With this configuration, it is possible to generate a stable address discharge without increasing the voltage necessary for generating the address discharge, and to improve the image display quality.

  Further, in this plasma display device, the panel temperature determination circuit is configured to determine the temperature state of the panel by comparing the temperature detected by the temperature sensor with a predetermined threshold, and the drive circuit is provided in the panel temperature determination circuit. When it is determined that the temperature detected by the temperature sensor is lower than a predetermined threshold, the above-described predetermined time interval is shortened as compared with the case where it is not. With this configuration, it is possible to determine whether or not the panel temperature is lower than a predetermined threshold value, and to control the predetermined time based on the determination result.

  The present invention also relates to a method for driving a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, the address period for selecting a discharge cell to be discharged, and the address period selected in this address period. A plurality of subfields having a sustain period for generating a sustain discharge of the number corresponding to the luminance weight in the discharge cell are provided in one field period, and the sustain pulse is displaced from the base potential to a potential for generating the sustain discharge in the sustain period. A voltage is applied alternately to the display electrode pair, and a sustain pulse voltage for generating the last sustain discharge in the sustain period is applied to the scan electrode, and then the potential difference between the electrodes of the display electrode pair with a predetermined time interval. A voltage for relaxing the voltage is applied to the sustain electrode, and it is determined whether or not the panel temperature is lower than the predetermined temperature. When it is determined also low, the predetermined time intervals mentioned above, characterized in that for short driving than otherwise.

  By this method, it is possible to generate a stable address discharge without increasing the voltage necessary for generating the address discharge, and to improve the image display quality.

  According to the present invention, it is possible to provide a plasma display device and a panel driving method capable of generating stable address discharge without increasing the voltage necessary for generating address discharge and improving image display quality. Is possible.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to an embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed on a glass front plate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is formed from a material mainly composed of MgO having excellent properties.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel is not limited to the above-described structure, and for example, a structure having a stripe-shaped partition may be used.

  FIG. 2 is an electrode array diagram of panel 10 according to the embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. As shown in FIGS. 1 and 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance Cp.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. The plasma display device according to the present embodiment performs gradation display by subfield method, that is, by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In each subfield, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. In addition, it has a function of generating priming particles (priming for discharge = excited particles) for reducing discharge delay and generating address discharge stably. The initializing operation at this time includes all-cell initializing operation in which initializing discharge is generated in all discharge cells and selective initializing in which initializing discharge is generated in the discharge cell that has undergone sustain discharge in the previous subfield. There is an operation.

  In the address period, an address discharge is selectively generated in the discharge cells to emit light in the subsequent sustain period to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission. The proportionality constant at this time is called “luminance magnification”.

  In this embodiment, one field is composed of ten subfields (first SF, second SF,..., Tenth SF), and each subfield is, for example, (1, 2, 3, 6, 11). , 18, 30, 44, 60, 80). Then, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the tenth SF. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  In the present embodiment, the erase discharge generated at the end of the sustain period is controlled according to the temperature state of the panel 10 determined by the panel temperature determination circuit described later. Specifically, the discharge period of the erase discharge generated by the sustain pulse voltage at the end of the sustain period is shortened when the temperature of the panel 10 is lower than a predetermined temperature than when it is not. As a result, it is possible to generate a stable address discharge without increasing the voltage necessary for generating the address discharge. Hereinafter, the outline of the drive voltage waveform will be described first, and then, when the panel temperature determination circuit determines that the temperature of the panel 10 is lower than the predetermined temperature, and when it is determined that the temperature is equal to or higher than the predetermined temperature. The difference in drive voltage waveform will be described.

  FIG. 3 is a waveform diagram of drive voltages applied to each electrode of panel 10 according to the embodiment of the present invention, and FIG. 4 is a partially enlarged view of FIG. FIG. 3 shows driving voltage waveforms of two subfields, that is, a subfield that performs an all-cell initializing operation (hereinafter referred to as “all-cell initializing subfield”) and a subfield that performs a selective initializing operation ( Hereinafter, it is referred to as “selective initialization subfield”), but the driving voltage waveforms in the other subfields are substantially the same. FIG. 4 is an enlarged view of a portion surrounded by a broken line in FIG. 3 and shows the last portion of the sustain period.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and the discharge start voltage with respect to the sustain electrodes SU1 to SUn is applied to the scan electrodes SC1 to SCn. A ramp waveform voltage (hereinafter referred to as “up-ramp waveform voltage”) that gradually rises from the voltage Vi1 below toward the voltage Vi2 that exceeds the discharge start voltage is applied.

  While the rising ramp waveform voltage rises, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, 0 (V) is applied to data electrodes D1 to Dm, and scan electrodes SC1 to SCn have sustain electrodes SU1 to SUn. Then, a ramp waveform voltage (hereinafter referred to as “down-ramp waveform voltage”) that gently falls from a voltage Vi3 that is equal to or lower than the discharge start voltage to a voltage Vi4 that exceeds the discharge start voltage is applied. During this time, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  In the subsequent address period, voltage Ve2 is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn.

  First, the negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell to be emitted in the first row among the data electrodes D1 to Dm is positive. The write pulse voltage Vd is applied. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference in externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. Then, address discharge occurs between data electrode Dk and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1, positive wall voltage is accumulated on scan electrode SC1, and negative wall is applied on sustain electrode SU1. A voltage is accumulated, and a negative wall voltage is also accumulated on the data electrode Dk.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn, and a ground potential that is a base potential, that is, 0 (V) is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeding the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as a base potential is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, the sustain electrodes of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and a potential difference is given between the electrodes of the display electrode pair 24, thereby writing. The sustain discharge is continuously performed in the discharge cell that has caused the address discharge in the period.

  As shown in FIG. 4, at the end of the sustain period, a so-called narrow pulse-shaped voltage difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the positive polarity on data electrode Dk is increased. The wall voltage on scan electrode SCi and sustain electrode SUi is adjusted while leaving the wall voltage.

  Specifically, after sustain electrodes SU1 to SUn are once returned to 0 (V) as the base potential, sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn.

  Then, a sustain discharge occurs between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred. The voltage Ve1 is applied to the sustain electrodes SU1 to SUn before the discharge converges, that is, while charged particles generated by the discharge remain sufficiently in the discharge space. As a result, the voltage difference between sustain electrode SUi and scan electrode SCi is reduced to the extent of (Vs−Ve1). Then, the wall voltage between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn is the difference between the voltages applied to the respective electrodes (Vs−Ve1) while leaving the positive wall charges on the data electrode Dk. It is weakened to the extent of. Hereinafter, this discharge is referred to as “erase discharge”. Further, the potential difference applied between the electrodes of the display electrode pair 24, that is, between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn in order to generate the erasing discharge is a narrow pulse-shaped potential difference.

  Thus, after applying the voltage Vs for generating the last sustain discharge, that is, the erasure discharge, to the scan electrodes SC1 to SCn, after a predetermined time interval (hereinafter referred to as “erasure phase difference Th1”), A voltage Ve1 for reducing the potential difference between the electrodes of the display electrode pair 24 is applied to the sustain electrodes SU1 to SUn. Thus, the maintenance operation in the maintenance period of the first SF is completed.

  Next, the operation of the second SF that is the selective initialization subfield will be described.

  In the selective initialization period of the second SF, while the voltage Ve1 is applied to the sustain electrodes SU1 to SUn and 0 (V) is applied to the data electrodes D1 to Dm, the voltage Vi3 ′ is applied to the scan electrodes SC1 to SCn from the voltage Vi3 ′ to the voltage Vi4. Apply a ramp-down waveform voltage that gently falls.

  Then, a weak initializing discharge is generated in the discharge cell that has caused the sustain discharge in the sustain period of the previous subfield, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. For data electrode Dk, a sufficient positive wall voltage is accumulated on data electrode Dk by the last sustain discharge, so that an excessive portion of this wall voltage is discharged, and the wall voltage suitable for the write operation is obtained. Adjusted to

  On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. As described above, the selective initializing operation is an initializing operation in which initializing discharge is selectively performed on the discharge cells that have undergone the sustain operation in the sustain period of the immediately preceding subfield.

  The subsequent operation in the write period is the same as the operation in the write period of the all-cell initialization subfield, and thus the description thereof is omitted. The operation in the subsequent sustain period is the same except for the number of sustain pulses. In the third SF to the tenth SF, the operation in the initialization period is a selective initialization operation similar to that in the second SF, the address operation in the write period is the same as that in the second SF, and the operation in the sustain period also has the number of sustain pulses. It is the same except for this.

  Here, in this embodiment, the erasing discharge generated at the end of the sustain period is controlled in accordance with the temperature state of the panel 10 determined by the panel temperature determination circuit described later. Specifically, in order to control the discharge period of the erase discharge, the erase phase difference Th1 of the voltage applied to each of the display electrode pair 24 at the end of the sustain period is determined by the panel temperature determination circuit, and the temperature state of the panel 10 Is controlled by.

  FIG. 5 is a diagram showing the relationship between the temperature state of the panel and the erasing phase difference Th1 in one embodiment of the present invention. As shown in FIG. 5, in the present embodiment, the erasing phase difference Th1 is switched based on the temperature state of the panel 10 determined by the panel temperature determination circuit.

  That is, when the panel temperature determination circuit determines that the temperature of the panel 10 is equal to or higher than a predetermined temperature (in this embodiment, the temperature of the panel 10 is 40 ° C. or higher), the erase phase difference Th1 is set to 250 nsec, which is less than the predetermined temperature. (In this embodiment, when it is determined that the temperature of the panel 10 is less than 40 ° C.), the erase phase difference Th1 is set to 200 nsec.

  As described above, in the present embodiment, when the temperature of the panel 10 is lower than the predetermined temperature, the voltage necessary for generating the write discharge by shortening the erase phase difference Th1 is shorter than when the temperature is not so. Stable address discharge is generated without increasing the. This is for the following reason.

  As described above, the erasing discharge by the narrow pulse changes the electric field in the discharge space while the charged particles generated in the discharge remain sufficiently in the discharge space, and relaxes the changed electric field. A desired wall charge is formed by rearranging charged particles to form a wall charge. However, when the erase phase difference Th1 becomes longer, charged particles generated by the discharge are recombined, and there is a shortage of charged particles for relaxing the electric field, so that a desired wall charge cannot be formed. It has been confirmed that it will increase.

  On the other hand, if the erasing phase difference Th1 is too small, the discharge becomes insufficient, the charged particles for relaxing the electric field are insufficient, and a desired wall charge cannot be formed, so that it is desired to generate the write discharge originally. It has also been confirmed that an address failure sometimes occurs in which the wall voltage is insufficient and address discharge does not occur.

  For this reason, it is desirable to set the erase phase difference Th1 to a value that does not cause either writing failure, and by doing so, it is possible to generate stable writing discharge without increasing the voltage required for writing. . In order to reduce both address defects and realize stable address discharge, it has been experimentally obtained that it is desirable to set the erase phase difference Th1 in the range of 200 nsec to 250 nsec. Therefore, in the present embodiment, the following experiment was performed by switching the erasing phase difference Th1 between 200 nsec and 250 nsec based on this result.

  The discharge characteristics change depending on the temperature of the panel 10, and the discharge delay (the time delay from when the voltage for generating the discharge is applied to the discharge cell until the actual discharge is generated) or the dark current ( The factor that makes the discharge unstable, such as the current generated in the discharge cell regardless of the discharge, also changes depending on the temperature of the panel 10. It has also been confirmed that when the temperature of the panel 10 is lowered, the dark current in the discharge cell changes and the disappearance of the wall charge (hereinafter referred to as “charge loss”) increases, so that unlit cells are likely to occur. . Therefore, the applied voltage necessary to generate a stable address discharge varies depending on the temperature of panel 10.

  For example, the voltage Ve <b> 2 necessary for generating a stable address discharge varies depending on the temperature of the panel 10. FIG. 6 is a diagram showing the relationship between the voltage Ve2 required for generating a stable address discharge, the panel temperature, and the erase phase difference Th1 in one embodiment of the present invention. In FIG. 6, the vertical axis represents the voltage Ve <b> 2 necessary for generating a stable address discharge, and the horizontal axis represents the temperature of the panel 10. The solid line represents the time when the erase phase difference Th1 is set to 250 nsec, and the broken line represents the time when the erase phase difference Th1 is set to 200 nsec.

  As shown in FIG. 6, the higher the temperature of the panel 10, the higher the voltage Ve2 necessary for generating a stable address discharge. For example, when the erase phase difference Th1 is set to 250 nsec, the voltage Ve2 necessary for generating a stable address discharge is about 140 (V) when the temperature of the panel 10 is about 40 ° C. When the temperature is about 70 ° C., it becomes about 150 (V), which is about 10 (V). Thus, the voltage Ve2 necessary for generating a stable address discharge changes according to the temperature of the panel 10, and the necessary voltage Ve2 increases as the temperature of the panel 10 increases.

  Further, as shown in FIG. 6, the voltage Ve2 required for generating a stable address discharge also changes depending on the erase phase difference Th1, and when the erase phase difference Th1 is set to 200 nsec, the erase phase difference Th1 is set to 250 nsec. It was confirmed that the voltage was about 4 (V) higher than when set to.

  Further, the address pulse voltage Vd necessary for generating a stable address discharge also changes according to the temperature of the panel 10. FIG. 7 is a diagram showing the relationship between the address pulse voltage Vd necessary for generating a stable address discharge, the panel temperature, and the erase phase difference Th1 in one embodiment of the present invention. In FIG. 7, the vertical axis represents the address pulse voltage Vd (amplitude) necessary for generating a stable address discharge, and the horizontal axis represents the temperature of the panel 10. The solid line represents the time when the erase phase difference Th1 is set to 250 nsec, and the broken line represents the time when the erase phase difference Th1 is set to 200 nsec.

  As shown in FIG. 7, the lower the temperature of panel 10, the higher the address pulse voltage Vd necessary for generating a stable address discharge. For example, when the erase phase difference Th1 is set to 250 nsec, the address pulse voltage Vd necessary for generating a stable address discharge is approximately 70 (V) when the temperature of the panel 10 is approximately 10 ° C. When the temperature of the panel 10 is about 0 ° C., it becomes about 85 (V) and about 15 (V). Thus, the address pulse voltage Vd necessary for generating a stable address discharge changes according to the temperature of the panel 10, and the address pulse voltage Vd required increases as the temperature of the panel 10 decreases.

  Further, as shown in FIG. 7, the address pulse voltage Vd necessary for generating a stable address discharge also varies depending on the erase phase difference Th1, and when the erase phase difference Th1 is set to 200 nsec, the erase phase difference Th1. It was confirmed that the required write pulse voltage Vd can be lowered by about 5 (V) than when the value is set to 250 nsec.

  As described above, the address pulse voltage Vd necessary for generating a stable address discharge and the voltage Ve2 required for generating a stable address discharge change according to the temperature of the panel 10 and the erase phase difference Th1. Confirmed to do. Furthermore, it was also confirmed that the characteristics of the panel 10 contradict each other with respect to the temperature and the erasing phase difference Th1.

  Here, in the plasma display device, an operation guarantee range relating to temperature is defined, and each drive voltage must be set so that stable operation is performed within the operation guarantee range. For example, with respect to the voltage Ve2, as described above, the voltage Ve2 required for generating a stable address discharge increases as the temperature of the panel 10 increases. Therefore, in order to perform a stable operation within the guaranteed operation range, the voltage Ve2 must be set so that a stable write operation can be performed at the highest temperature of the panel 10 assumed. As for the address pulse voltage Vd, the address pulse voltage Vd necessary for generating a stable address discharge increases as the temperature of the panel 10 decreases as described above. Therefore, in order to perform a stable operation within the guaranteed operation range, it is necessary to set the write pulse voltage Vd so that a stable write operation is performed at the lowest temperature of the assumed panel 10.

  On the other hand, as described above, the voltage Ve2 and the address pulse voltage Vd necessary for generating a stable address discharge also change depending on the erase phase difference Th1. Also, in order to generate a discharge stably, it is better that the margin between the drive voltage necessary for generating the discharge and the voltage actually applied is large. Therefore, in the plasma display device, the drive necessary for the discharge is required. It is desirable to reduce the voltage as much as possible.

  Therefore, in this embodiment, when the temperature of panel 10 is 40 ° C. or higher, erase phase difference Th1 is set to 250 nsec. This is because the voltage Ve2 necessary for generating a stable address discharge can be reduced by setting such a value, as shown in FIG. 6, rather than setting the erase phase difference Th1 to 200 nsec. .

  In the present embodiment, when the temperature of panel 10 is lower than 40 ° C., erase phase difference Th1 is set to 200 nsec. With this setting, as shown in FIG. 7, it is possible to reduce the address pulse voltage Vd necessary for generating a stable address discharge, rather than setting the erase phase difference Th1 to 250 nsec. It is. In particular, if the address pulse voltage Vd necessary for generating a stable address discharge is reduced and the margin for the address pulse voltage Vd to be actually applied is increased, the non-lighting that is likely to occur when the temperature of the panel 10 is low. It was also confirmed that the generation of cells was reduced.

  As described above, in the present embodiment, when the panel temperature determination circuit described later determines that the temperature of the panel 10 is 40 ° C. or higher, the erase phase difference Th1 is set to 250 nsec, and the temperature of the panel 10 is determined to be less than 40 ° C. In this case, the erase phase difference Th1 is set to 200 nsec. As a result, it is possible to generate stable address discharge without increasing the voltage necessary for generating address discharge, and to improve image display quality.

  As shown in FIG. 6, when the erase phase difference Th1 is set to 200 nsec, the voltage Ve2 required for generating a stable address discharge is higher than when the erase phase difference Th1 is set to 250 nsec. This is the same when the panel temperature is lower than 40 ° C. However, this voltage Ve2 is higher when the erase phase difference Th1 is 250 nsec and the panel temperature is 70 ° C. than when the erase phase difference Th1 is 200 nsec and the panel temperature is 40 ° C. Therefore, for example, if the voltage Ve2 to be actually applied is set based on the voltage Ve2 required when the erase phase difference Th1 is 250 nsec and the panel temperature is 70 ° C., the erase is performed when the panel temperature is less than 40 ° C. Even if the phase difference Th1 is switched from 250 nsec to 200 nsec, no problem occurs. This also applies to the write pulse voltage Vd.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 8 is a circuit block diagram of the plasma display device according to one embodiment of the present invention. The plasma display apparatus 1 is necessary for the panel 10, the image signal processing circuit 41, the data electrode drive circuit 42, the scan electrode drive circuit 43, the sustain electrode drive circuit 44, the timing generation circuit 45, the panel temperature determination circuit 46, and each circuit block. A power supply circuit (not shown) for supplying power is provided.

  The image signal processing circuit 41 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  Scan electrode drive circuit 43 includes sustain pulse generation circuit 50, and supplies a drive voltage waveform to scan electrodes SC1 to SCn based on a timing signal. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 60 and a circuit for generating voltages Ve1 and Ve2, and supplies a drive voltage waveform to sustain electrodes SU1 to SUn based on a timing signal.

  The panel temperature determination circuit 46 includes a temperature sensor 47 made of a generally known element such as a thermocouple used for detecting the temperature. Then, an estimated value of the temperature of the panel 10 is calculated from the temperature around the panel 10 detected by the temperature sensor 47, and the temperature value of the panel 10 is determined by comparing the calculated value with a predetermined threshold value. The result is output to the timing generation circuit 45. As described above, in the present embodiment, the threshold is set to 40 ° C., but this is merely an example, and an optimal value may be set according to the panel characteristics and the specifications of the plasma display device. .

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H, the vertical synchronization signal V, and the temperature state of the panel 10 determined by the panel temperature determination circuit 46. Supply to each circuit block. As described above, in the present embodiment, when the panel temperature determination circuit 46 determines that the temperature of the panel 10 is lower than the threshold value (40 ° C.), the erase phase difference Th1 is shortened more than when it is not. (Switching from 250 nsec to 200 nsec), and a timing signal corresponding to the control is output to scan electrode drive circuit 43 and sustain electrode drive circuit 44.

  Next, the details and operation of sustain pulse generating circuits 50 and 60 will be described. FIG. 9 is a circuit diagram of sustain pulse generating circuits 50 and 60 in one embodiment of the present invention. In FIG. 9, the interelectrode capacitance of the panel 10 is shown as Cp, and the circuit for generating the scan pulse and the initialization voltage waveform is omitted.

  The sustain pulse generation circuit 50 includes a power recovery unit 51 and a clamp unit 52. The power recovery unit 51 includes a power recovery capacitor C10, switching elements Q11 and Q12, backflow prevention diodes D11 and D12, and a resonance inductor L10. Clamp unit 52 includes switching element Q13 for clamping scan electrodes SC1 to SCn to power supply VS having a voltage value of Vs, and switching element Q14 for clamping scan electrodes SC1 to SCn to the ground potential. ing. The power recovery unit 51 and the clamp unit 52 are connected to the scan electrodes SC1 to SCn which are one end of the interelectrode capacitance Cp of the panel 10 via a scan pulse generation circuit (not shown because it is in a short circuit state during the sustain period). Has been.

  The power recovery unit 51 causes the interelectrode capacitance Cp and the inductor L10 to resonate with each other so as to rise and fall the sustain pulse. When the sustain pulse rises, the charge stored in the power recovery capacitor C10 is transferred to the interelectrode capacitance Cp via the switching element Q11, the diode D11, and the inductor L10. When the sustain pulse falls, the charge stored in the interelectrode capacitance Cp is returned to the power recovery capacitor C10 via the inductor L10, the diode D12, and the switching element Q12. In this way, the sustain pulse is applied to scan electrodes SC1 to SCn. As described above, the power recovery unit 51 drives the scan electrodes SC1 to SCn by LC resonance without being supplied with power from the power source, so that the power consumption is ideally zero. The power recovery capacitor C10 has a sufficiently large capacity compared to the interelectrode capacitance Cp, and is configured to work as a power source for the power recovery unit 51, and is approximately Vs / half of the voltage value Vs of the power source VS. 2 is charged.

  Voltage clamp unit 52 connects scan electrodes SC1 to SCn to power supply VS via switching element Q13, and clamps scan electrodes SC1 to SCn to voltage Vs. Further, scan electrodes SC1 to SCn are grounded via switching element Q14 and clamped to 0 (V). In this way, voltage clamp unit 52 drives scan electrodes SC1 to SCn. Therefore, the impedance at the time of voltage application by the voltage clamp unit 52 is small, and a large discharge current due to strong sustain discharge can be stably passed.

  In this way, sustain pulse generating circuit 50 applies sustain pulse voltage to scan electrodes SC1 to SCn using power recovery unit 51 and voltage clamp unit 52 by controlling switching elements Q11, Q12, Q13, and Q14. Note that these switching elements can be configured using generally known elements such as MOSFETs and IGBTs.

  Sustain pulse generating circuit 60 includes power recovery capacitor C20, switching elements Q21 and Q22, backflow prevention diodes D21 and D22, and resonance inductor L20, and sustain electrodes SU1 to SUn at voltage Vs. And a clamp portion 62 having a switching element Q24 for clamping the sustaining electrodes SU1 to SUn to the ground potential, and sustaining electrodes SU1 to SUn that are one end of the interelectrode capacitance Cp of the panel 10 It is connected to the. The operation of sustain pulse generating circuit 60 is the same as that of sustain pulse generating circuit 50, and therefore description thereof is omitted.

  Further, FIG. 9 shows a power source VE1 that generates a voltage Ve1 for relaxing the potential difference between the electrodes of the display electrode pair 24, switching elements Q26 and Q27 for applying the voltage Ve1 to the sustain electrodes SU1 to SUn, and a voltage ΔVe. Also shown is a switching element Q28, Q29 for accumulating the voltage ΔVe to the voltage Ve2 by accumulating the voltage ΔVe to the power source ΔVE for generating the reverse current, the diode D30 for preventing backflow, the capacitor C30, and the voltage Ve1. For example, at the timing of applying the voltage Ve1 shown in FIG. 3, the switching elements Q26 and Q27 are turned on, and the positive voltage Ve1 is applied to the sustain electrodes SU1 to SUn via the diode D30 and the switching elements Q26 and Q27. At this time, the switching element Q28 is turned on and charged so that the voltage of the capacitor C30 becomes the voltage Ve1. In addition, at the timing of applying the voltage Ve2 shown in FIG. 3, the switching elements Q26 and Q27 are kept conductive while the switching element Q28 is cut off and the switching element Q29 is turned on to superimpose the voltage ΔVe on the voltage of the capacitor C30. The voltage Ve1 + ΔVe, that is, the voltage Ve2 is applied to the sustain electrodes SU1 to SUn. At this time, the current from the capacitor C30 to the power source VE1 is cut off by the function of the backflow preventing diode D30.

  Note that the period of LC resonance between the inductor L10 of the power recovery unit 51 and the interelectrode capacitance Cp of the panel 10 and the period of LC resonance between the inductor L20 of the power recovery unit 61 and the interelectrode capacitance Cp (hereinafter referred to as “resonance period”). Can be obtained by the calculation formula “2π√ (LCp)”, where L is the inductance of the inductors L10 and L20. In the present embodiment, the inductors L10 and L20 are set so that the resonance period in the power recovery units 51 and 61 is about 1100 nsec. However, this numerical value is only an example in the embodiment, and the characteristics of the panel. It may be set to an optimum value according to the specifications of the plasma display device.

  Next, details of the drive voltage waveform in the sustain period will be described. FIG. 10 is a timing chart for explaining the operation of sustain pulse generating circuits 50 and 60 in one embodiment of the present invention, and is a detailed timing chart of a portion surrounded by a broken line in FIG. First, one period of the sustain pulse is divided into six periods indicated by T1 to T6, and each period will be described.

  In the following description, the operation for conducting the switching element is expressed as ON and the operation for blocking is expressed as OFF. In the drawing, the signal for turning on the switching element is expressed as “ON”, and the signal for turning off is expressed as “OFF”.

(Period T1)
At time t1, switching element Q12 is turned on. Then, the charges on the scan electrodes SC1 to SCn side start to flow to the capacitor C10 through the inductor L10, the diode D12, and the switching element Q12, and the voltage on the scan electrodes SC1 to SCn starts to decrease. Since inductor L10 and interelectrode capacitance Cp form a resonance circuit, the voltage of scan electrodes SC1 to SCn drops to near 0 (V) at time t2 after the time ½ of the resonance period has elapsed. However, the voltage of scan electrodes SC1 to SCn does not drop to 0 (V) due to power loss due to the resistance component of the resonance circuit. During this time, the switching element Q24 is kept on.

(Period T2)
At time t2, switching element Q14 is turned on. Then, scan electrodes SC1 to SCn are directly grounded through switching element Q14, so that the voltages of scan electrodes SC1 to SCn are forcibly lowered to 0 (V).

  Further, switching element Q21 is turned on at time t2. Then, a current starts to flow from the power recovery capacitor C20 through the switching element Q21, the diode D21, and the inductor L20, and the voltages of the sustain electrodes SU1 to SUn begin to rise. Since the inductor L20 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the sustain electrodes SU1 to SUn rises to near Vs at time t3 after a time ½ of the resonance period has elapsed. Due to power loss due to the resistance component or the like, the voltage of the sustain electrodes SU1 to SUn does not rise to Vs.

(Period T3)
At time t3, switching element Q23 is turned on. Then, since sustain electrodes SU1 to SUn are directly connected to power supply VS through switching element Q23, the voltages of sustain electrodes SU1 to SUn are forcibly increased to Vs. Then, in the discharge cell in which the address discharge has occurred, the voltage between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, and a sustain discharge occurs.

(Period T4-T6)
The sustain pulse applied to scan electrodes SC1 to SCn and the sustain pulse applied to sustain electrodes SU1 to SUn have the same waveform, and the operation from period T4 to period T6 scans the operation from period T1 to period T3. Since this is equivalent to the operation of driving the electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, the description thereof will be omitted.

  Switching element Q12 may be turned off after time t2 and before time t5, and switching element Q21 may be turned off after time t3 and before time t4. Further, the switching element Q22 may be turned off after time t5 before the next time t2, and the switching element Q11 may be turned off after time t6 until the next time t1. In order to lower the output impedance of sustain pulse generating circuits 50 and 60, switching element Q24 is preferably turned off immediately before time t2, switching element Q13 is preferably turned off immediately before time t1, and switching element Q14 is turned off immediately before time t5. Switching element Q23 is preferably turned off immediately before time t4.

  In the sustain period, the operations in the above periods T1 to T6 are repeated according to the required number of pulses. In this manner, a sustain pulse voltage that shifts from 0 (V), which is the base potential, to a voltage Vs, which is a potential for generating a sustain discharge, is alternately applied to each of the display electrode pairs 24 to sustain discharge the discharge cells. .

  Next, the last erasing discharge in the sustain period will be described in detail by dividing it into five periods T7 to T11.

(Period T7)
This period is the fall of the sustain pulse applied to sustain electrodes SU1 to SUn, and is the same as period T4. That is, by turning off the switching element Q23 just before time t7 and turning on the switching element Q22 at time t7, the charges on the sustain electrodes SU1 to SUn side start to flow to the capacitor C20 through the inductor L20, the diode D22, and the switching element Q22. The voltage of sustain electrodes SU1 to SUn begins to drop.

(Period T8)
At time t8, switching element Q24 is turned on to forcibly reduce the voltages of sustain electrodes SU1 to SUn to 0 (V). Further, the switching element Q14 is turned off immediately before time t8, and the switching element Q11 is turned on at time t8. Then, current begins to flow from the power recovery capacitor C10 through the switching element Q11, the diode D11, and the inductor L10, and the voltages of the scan electrodes SC1 to SCn begin to rise.

(Period T9)
Since the inductor L10 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrodes SC1 to SCn rises to near Vs after a time ½ of the resonance period has elapsed. Here, the power recovery unit The switching element Q13 is turned on at a time shorter than ½ of the resonance period, that is, at time t9 before the voltage of the scan electrodes SC1 to SCn rises to near Vs. Then, scan electrodes SC1 to SCn are directly connected to power supply VS through switching element Q13, so that the voltage of scan electrodes SC1 to SCn rises sharply to Vs, and the last sustain discharge is generated.

(Period T10)
Switching element Q24 is turned off immediately before time t10, and switching elements Q26 and Q27 are turned on at time t10. Then, since sustain electrodes SU1 to SUn are directly connected to erasing power supply VE1 through switching elements Q26 and Q27, the voltages of sustain electrodes SU1 to SUn are forcibly increased to Ve1. This time t10 is a time before the discharge generated in the period T9 converges, that is, the charged particles generated by the discharge sufficiently remain in the discharge space. Since the electric field in the discharge space changes while the charged particles remain sufficiently in the discharge space, the charged particles are rearranged to relax the changed electric field to form wall charges.

  At this time, voltage Ve1 is applied to sustain electrodes SU1 to SUn to reduce the voltage difference between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and walls on scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. The voltage is weakened. Thus, the potential difference for generating the last sustain discharge is a narrow pulse-shaped potential difference that is changed so as to relax the potential difference applied between the electrodes of the display electrode pair 24 before the last sustain discharge converges. The sustain discharge that occurs is an erasing discharge. Although not shown in FIG. 10, the data electrodes D1 to Dm are held at 0 (V) at this time, and are applied to the voltages applied to the data electrodes D1 to Dm and the scan electrodes SC1 to SCn. Since the charged particles due to the discharge form wall charges so as to alleviate the potential difference from the existing voltage, a positive wall voltage is formed on the data electrodes D1 to Dm. Voltage Ve1 is set to a voltage value smaller than voltage Vs so that the polarities of the wall charges on scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn do not change.

  In this manner, the sustain pulse for generating the last sustain discharge is applied to one of the display electrode pairs 24 (here, the scan electrodes SC1 to SCn), and then the potential difference between the electrodes of the display electrode pair 24 is reduced. A predetermined time interval is provided until the voltage for applying the voltage to the other of the display electrode pair 24 (here, the sustain electrodes SU1 to SUn), and the time interval is defined as an erasing phase difference Th1.

  In this embodiment, the control is performed by turning on the switching element Q13 for applying the voltage Vs for generating the sustain discharge to the scan electrodes SC1 to SCn, and then the panel 10 in the panel temperature determination circuit 46. Switching in which a voltage Ve1 for reducing the potential difference between the electrodes of the display electrode pair 24 is applied to the sustain electrodes SU1 to SUn at a time interval (200 nsec or 250 nsec in the present embodiment) according to the determination result of the temperature state. This is done by turning on the elements Q26 and Q27. Therefore, a delay due to the delay time of the switching element occurs after the control signal is input to the switching element until the switching element actually starts the switching operation. In practice, however, the control signal input to the switching element , That is, from time t9 to time t10 can be regarded as the erasure phase difference Th1.

  As described above, in the present embodiment, after applying sustain pulse voltage Vs for generating the last sustain discharge in the sustain period to scan electrodes SC1 to SCn, the erase phase difference that is a predetermined time interval is applied. A voltage Ve1 for relaxing the potential difference between the electrodes of the display electrode pair 24 with Th1 being applied is applied to the sustain electrodes SU1 to SUn, and a predetermined time interval according to a signal from the panel temperature determination circuit 46 The erasing phase difference Th1 is changed. That is, when the panel temperature determination circuit 46 determines that the temperature of the panel 10 is 40 ° C. or higher, the erase phase difference Th1 is set to 250 nsec, and when the panel 10 temperature is determined to be less than 40 ° C., the erase phase difference Th1 is set to 200 nsec. By doing so, it is possible to generate a stable address discharge without increasing the voltage necessary for generating the address discharge, and to improve the image display quality.

  Note that the circuit that applies the voltage Ve1 and the voltage Ve2 is not limited to the circuit illustrated in FIG. 9. For example, the power source that generates the voltage Ve1 and the power source that generates the voltage Ve2 and the respective voltages are maintained electrodes. A plurality of switching elements for applying to SU1 to SUn can be used to apply the sustain electrodes SU1 to SUn at necessary timings.

  Each numerical value shown in the present embodiment, for example, the threshold value used for comparison with the temperature of the panel 10 in the panel temperature determination circuit 46 and the erase phase difference Th1 is 50 of the display electrode pair number 1080 used in the experiment. It is based on the characteristics of the inch panel and is merely an example of an embodiment. This embodiment is not limited to these numerical values, and is desirably set to an optimal value according to the characteristics of the panel, the specifications of the plasma display device, and the like. Each of these numerical values allows variation within a range where the above-described effect can be obtained.

  If the panel temperature determination circuit 46 determines the temperature of the panel 10 so as to have a hysteresis characteristic, frequent fluctuations in the erase phase difference Th1 can be suppressed when the panel 10 temperature is near the threshold value. Display quality can be improved. Specifically, two threshold values are provided for determining the temperature state of the panel 10, and the threshold value used when the temperature of the panel 10 is rising (for example, 42 ° C.) is used when the temperature of the panel 10 is decreasing. Hysteresis characteristics can be provided by setting the threshold value higher than the threshold value (for example, 38 ° C.).

  In the present embodiment, the configuration in which the temperature state of the panel 10 is divided into two and the erasing phase difference Th1 is switched has been described. However, the configuration is not limited to this configuration. For example, the temperature state of the panel 10 is 3 Alternatively, the erase phase difference Th1 may be shortened as the temperature decreases.

  In the embodiment of the present invention, the sub-field configuration in which the first SF is an all-cell initializing subfield and the second SF to the tenth SF are selective initializing subfields has been described as an example. It is not limited to the field configuration, and other subfield configurations may be used.

  Further, in the present embodiment, the configuration in which the same inductor is used for power supply and for power recovery has been described. However, the configuration is not limited to this configuration, and a configuration in which a plurality of inductors having different inductances are switched and used. It is good. In this configuration, for example, it is possible to drive by switching the resonance frequency between the rising edge and the falling edge of the sustain pulse.

  In this embodiment, the base potential is set to the ground potential. However, in the AC panel, the discharge cell is surrounded by a dielectric, and the drive voltage waveform of each electrode is capacitively coupled to the discharge cell. Since the voltage is applied, each drive voltage waveform including the base potential may be level-shifted in a DC manner.

  INDUSTRIAL APPLICABILITY The present invention can generate stable address discharge without increasing the voltage necessary for generating address discharge and improve image display quality, and is useful as a method for driving a plasma display device and a panel. is there.

The disassembled perspective view which shows the structure of the panel in one embodiment of this invention. Electrode arrangement of the panel Drive voltage waveform diagram applied to each electrode of the panel Partial enlarged view of drive voltage waveform applied to each electrode of the panel The figure which shows the relationship between the temperature state of the panel, and erasure | elimination phase difference Th1 The figure which shows the relationship between voltage Ve2 required in order to generate the stable address discharge in one embodiment of this invention, the temperature of a panel, and erase | elimination phase difference Th1 The figure which shows the relationship between the address pulse voltage required in order to generate the stable address discharge in one embodiment of this invention, the temperature of a panel, and erase phase difference Th1. The circuit block diagram of the plasma display apparatus in one embodiment of the present invention 1 is a circuit diagram of a sustain pulse generation circuit according to an embodiment of the present invention. Timing chart for explaining operation of sustain pulse generating circuit in one embodiment of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 data electrode drive circuit 43 scan electrode drive circuit 44 sustain electrode drive circuit 45 timing generation circuit 46 panel temperature determination circuit 47 temperature sensor 50, 60 sustain pulse generation circuit 51, 61 power recovery unit 52, 62 (voltage) clamp unit Q11, Q12, Q13, Q14, Q21, Q22, Q23, Q24, Q26, Q27, Q28, Q29 Switching elements D11, D12, D21, D22, D30 (for backflow prevention) Diodes C10, C20, C30 (for power recovery) Capacitors L10, L20 (for resonance Inductor Cp interelectrode capacitance VE1, [Delta] VE, VS Power

Claims (3)

A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode;
A plurality of subfields having an address period for selecting a discharge cell to be discharged and a sustain period for generating a sustain discharge of the number corresponding to the luminance weight in the discharge cell selected in the address period are provided in one field period. A driving circuit for driving the plasma display panel;
A panel temperature determination circuit having a temperature sensor and determining a temperature state of the plasma display panel;
The driving circuit recovers the electric power stored in the interelectrode capacitance of the display electrode pair and supplies the recovered electric power to the display electrode pair and switching for clamping each of the display electrode pair to a power supply voltage A sustain pulse generating circuit having an element and a clamp part having a switching element for clamping to a base potential, and a switching element for applying a voltage to the display electrode pair to relieve a potential difference between the electrodes of the display electrode pair. And a sustain pulse voltage that is displaced from a base potential to a potential that generates a sustain discharge in the sustain period is alternately applied to the display electrode pair, and the last sustain discharge is generated in the sustain period. After applying the sustain pulse voltage to the scan electrode, a potential difference between the electrodes of the display electrode pair is provided at a predetermined time interval. A voltage for mitigating configured to apply to the sustain electrode, and a plasma display apparatus characterized by being configured to change the predetermined time interval in response to a signal from the panel temperature determination circuit. The panel temperature determination circuit is configured to determine the temperature state of the plasma display panel by comparing the temperature detected by the temperature sensor with a predetermined threshold value,
The drive circuit is configured to shorten the predetermined time interval when it is determined that the temperature detected by the temperature sensor in the panel temperature determination circuit is lower than a predetermined threshold, than when it is not. The plasma display device according to claim 1, wherein: A method of driving a plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode,
A plurality of subfields having an address period for selecting discharge cells to be discharged and a sustain period for generating sustain discharges corresponding to the luminance weight in the discharge cells selected in the address period are provided in one field period,
In the sustain period, a sustain pulse voltage that shifts from a base potential to a potential that generates a sustain discharge is alternately applied to the display electrode pair, and a sustain pulse voltage for generating the last sustain discharge in the sustain period is applied to the display electrode pair. After being applied to the scan electrodes, a voltage for relaxing the potential difference between the electrodes of the display electrode pair is applied to the sustain electrodes with a predetermined time interval, and the temperature of the plasma display panel is higher than the predetermined temperature. The plasma display panel driving method is characterized in that when the temperature is lower than the predetermined temperature and the temperature is lower than the predetermined temperature, the predetermined time interval is shorter than that when the temperature is lower. .

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