JP2008140811A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, capable of removing a BeO film to form a p-side electrode having excellent bondability without complicating an electrode forming process. <P>SOLUTION: According to the method of manufacturing a semiconductor device, the BeO formed due to heat in providing ohmic characteristics on the surfaces of p-side electrodes 18, 18a, 18b having an AuBe layer 5 is removed by etching. Thus, the p-side electrodes 18, 18a, 18b having excellent bondability can be formed without complicating the electrode forming step. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a semiconductor element capable of forming an electrode having excellent bonding properties to the semiconductor element.

  Semiconductor devices are widely developed as active parts such as diodes and transistors, recording devices such as memories, light receiving devices such as photodiodes, and light emitting devices such as semiconductor lasers. It is indispensable for.

  In these semiconductor elements, particularly semiconductor elements using III-V group compound semiconductors such as GaAs (gallium arsenide), AlGaAs (aluminum gallium arsenide), AlGaInP (aluminum gallium indium phosphide), InP (indium phosphide), the p-type semiconductor side As an electrode material, an intermetallic compound such as AuBe (gold-beryllium) is often used. Here, an example of a conventional electrode forming method for forming a p-side electrode as a p-type ohmic electrode having an AuBe layer on a p-type semiconductor layer of a semiconductor element using a III-V group compound semiconductor will be described with reference to FIG. I will explain.

  First, a p-type GaAs layer 42 is formed on a GaAs substrate 41 which is a III-V group compound semiconductor shown in FIG. 8A by a known technique such as metal organic chemical vapor deposition or molecular beam epitaxial growth. Next, the surface of the p-type GaAs layer 42 is etched with an etchant such as a known mixed solution containing phosphoric acid and hydrogen peroxide, thereby removing oxides, foreign matters, and the like on the surface of the p-type GaAs layer 42.

  Next, as shown in FIG. 8B, an AuBe layer 5 and an Au layer 6 having a predetermined thickness are sequentially formed on the surface of the p-type GaAs layer 42 by a known method such as vapor deposition or sputtering. A p-side electrode 18 is formed.

  Next, heat treatment is performed at a predetermined temperature and time during or after the formation of the p-side electrode 18. As a result, the Au element and the Be element contained in the AuBe layer 5 diffuse into the p-type GaAs layer 42, and the vicinity of the interface of the p-type GaAs layer 42 in contact with the AuBe layer 5 is high as shown in FIG. A p-type GaAs-Au-Be alloy layer 7 containing Au elements and Be elements at a concentration is obtained. Since the impurity concentration of the alloy layer 7 is higher than that of the p-type GaAs layer 42, the thickness of the depletion layer present in the alloy layer 7 is thinner than before the formation of the alloy layer 7. For this reason, a tunnel effect based on quantum mechanics acts on the alloy layer 7, and the voltage-current characteristics between the AuBe layer 5 and the p-type GaAs layer 42 change from Schottky characteristics to ohmic characteristics. Thereby, the p-side electrode 18 functions as a p-type ohmic electrode capable of flowing a current to the p-type GaAs layer 42 side.

  However, the p-side electrode 18 of the semiconductor laser chip is formed by the above-described method, and the p-side electrode 18 of the semiconductor laser chip and a base such as a package are joined using a solder material containing Sn (tin) or the like. As a result, many mounting failures on the base may occur. In addition, even if the mounting failure did not occur, there were many cases where the heat dissipation of the heat generated when the semiconductor laser was driven was poor and the device characteristics deteriorated. Furthermore, when an Au wire or the like is bonded to the p-side electrode 18 of the semiconductor laser chip by wire bonding, there are cases where bonding failure such as peeling of the Au wire frequently occurs.

  Further, when the p-side electrode 18 is formed as the transistor electrode by the above-described method, there may be a case where characteristic defects frequently occur due to a decrease in high frequency characteristics (cutoff frequency and noise characteristics) of the transistor.

  Therefore, when the inventors analyzed the cause of the occurrence of the above-described defect, the Be element in the AuBe layer 5 diffuses to the p-type semiconductor layer side and the Au layer when the p-side electrode 18 is heat treated to give ohmic characteristics. It was found that the Be element diffused to the 6 side and the Be element diffused to the Au layer 6 side deposited on the surface of the p-side electrode 18 and then reacted with oxygen in the air to form a BeO (beryllium oxide) film. .

  Since this BeO has extremely poor wettability with the solder material, the BeO film formed on the surface of the p-side electrode 18 obstructs the bonding between the p-side electrode 18 and the solder material, which is the base of the semiconductor laser chip. It was confirmed that it would cause mounting failure. Even if mounting failure does not occur, the bonding area between the p-side electrode 18 and the solder material is reduced due to the presence of the BeO film, so that heat generated in the semiconductor laser chip is not conducted efficiently to the base and is dissipated. It has been found that the device characteristics deteriorate and the device characteristics deteriorate. Furthermore, when bonding the p-side electrode 18 and Au wire or the like by wire bonding, it was confirmed that the BeO film on the surface of the p-side electrode 18 hinders bonding, and this causes peeling of the Au wire or the like. It was.

  In addition, when the p-side electrode 18 formed by the above method is used as an electrode of a transistor or the like, a BeO film having a high specific resistance is interposed between the p-side electrode 18 and the wiring metal layer. In order to increase the resistance value between the wiring metal layers and to increase the dispersion of the resistance value, it has been found that this causes a characteristic defect.

  As one method for preventing the formation of a BeO film on the p-side electrode 18, an AuBe layer (ohmic contact layer) is disclosed as an electrode forming method for a semiconductor light emitting device and an invention relating to the semiconductor light emitting device disclosed in [Patent Document 1] below. And providing a barrier metal layer made of Ti, TiN, Mo or the like between the Au layer and the Au layer (bonding pad layer). Since this barrier metal layer can prevent the Be element in the AuBe layer 5 from diffusing to the Au layer 6 side, a BeO film is not formed on the p-side electrode 18, and the p-side electrode 18 having high bonding properties. Can be formed.

JP 2001-217501 A

  However, it is necessary to use an electron beam heating vacuum deposition apparatus to form the barrier metal layer. On the other hand, it is preferable to use a resistance heating vacuum deposition apparatus that can easily control the composition ratio of Au and Be constituting the AuBe layer 5 to form the AuBe layer 5. Therefore, in order to form a good p-side electrode 18 using the electrode forming method described in [Patent Document 1], first, an AuBe layer 5 is formed by a resistance heating vacuum deposition apparatus, and then an electron beam heating vacuum is used. It is necessary to form a barrier metal layer with a vapor deposition apparatus, the electrode formation process becomes complicated, the production efficiency is extremely poor, and further improvement is desired.

  The present invention has been made in view of the above circumstances, and it is possible to manufacture a semiconductor element capable of removing a BeO film and forming a p-side electrode having excellent bonding properties without complicating an electrode formation process. It aims to provide a method.

The present invention
In a method for manufacturing a semiconductor element,
An electrode forming step of forming an electrode containing Be (beryllium) in the semiconductor layer;
After the electrode formation step, the semiconductor layer and the electrode are subjected to heat treatment to make the electrode ohmic electrode, and an ohmic property imparting step,
After the ohmic property imparting step, a surface treatment step of surface-treating the electrode with a solution in which beryllium oxide is soluble,
The above-described problems are solved by providing a method for manufacturing a semiconductor device characterized by having the following.

  Moreover, the said solution solves the said subject by providing the manufacturing method of the said semiconductor element characterized by containing hydrogen fluoride.

The manufacturing method of the semiconductor element according to the present invention is as follows.
Since the BeO film on the surface of the p-side electrode is removed by etching, it is possible to form a p-side electrode having excellent bonding properties without complicating the electrode formation process.

  Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating the present invention applied to a method for manufacturing a semiconductor laser chip. FIG. 2 is a schematic view showing the bonding of the semiconductor laser chip manufactured according to the present invention. 3, 4 and 5 are diagrams illustrating the present invention applied to a method for manufacturing a junction field effect transistor. 6 and 7 are diagrams for explaining the present invention by applying it to a method for manufacturing a junction field effect transistor according to the second embodiment. Note that members similar to those in the conventional example are represented using the same reference numerals. In this embodiment, a semiconductor laser chip and a junction field effect transistor will be described as an example of a semiconductor element. However, dimensions, compositions, layer configurations, and the like of each part of the semiconductor laser chip and the junction field effect transistor are described here. It is not limited. The present invention is not particularly limited to the semiconductor laser chip and the junction field effect transistor.

  As Example 1 of the semiconductor device manufacturing method according to the present invention, an example in which the present invention is applied to a semiconductor laser chip manufacturing method will be described with reference to FIG.

First, as shown in FIG. 1A, a light-emitting layer 2 and a p-type GaAs contact layer 3 (Zn doping concentration: 5 × 10 ¹⁸ cm ⁻³ ) having a thickness of 5 μm are formed on an n-type GaAs substrate 1 in an organometallic vapor phase. The semiconductor wafer 10 is fabricated by sequentially forming a film by a known method such as a growth method or a molecular beam epitaxial growth method. Next, the surface of the p-type GaAs contact layer 3 is etched with an etchant such as a known mixed solution containing phosphoric acid and hydrogen peroxide solution to remove oxides and foreign matters on the surface of the p-type GaAs contact layer 3. The etchant used at this time may be another etchant such as a mixed solution containing sulfuric acid and hydrogen peroxide solution, or a mixed solution containing organic acid and hydrogen peroxide solution, which can obtain the same effect.

  Next, as an electrode forming step, as shown in FIG. 1B, an AuBe layer 5 having a thickness of 150 nm and an Au layer 6 having a thickness of 500 nm are formed on the p-type GaAs contact layer 3 side from the p-type GaAs contact layer 3 side. The p-side electrode 18 is formed by sequentially forming a film.

  The AuBe layer 5 is formed by depositing an AuBe alloy having a predetermined composition ratio in a vacuum on a boat or crucible made of Mo, W, Ta or the like, evaporating it by resistance heating, and depositing it on the p-type GaAs contact layer 3. It is preferable to use a resistance heating vacuum deposition method to form a film. This resistance heating vacuum deposition method is characterized in that there is no significant difference between the composition ratio of the metal that forms the film and the composition ratio of the metal film formed thereby. Therefore, by using a resistance heating vacuum deposition method for forming the AuBe layer 5, the composition ratio of Au and Be in the AuBe layer 5 can be easily controlled by the composition ratio of the AuBe alloy that forms the film. Is possible.

If the content of the Be element in the AuBe layer 5 is less than 15 mol%, the amount of Be necessary for forming an alloy layer 7 to be described later on the p-type GaAs contact layer 3 is insufficient. Ohmic characteristics cannot be imparted. On the contrary, if the content of Be element in the AuBe layer 5 exceeds 20 mol%, an Au _x Be compound is generated in the AuBe layer 5 and the AuBe layer 5 is hardened and becomes brittle, and Se segregation of the Be element occurs. there is a possibility. This Be segregated material is oxidized to BeO and is removed in a surface treatment step to be described later. However, at this time, the removed portion becomes a cavity and the surface smoothness of the p-side electrode 18 is deteriorated, which is not preferable. Therefore, the content of Be in the AuBe layer 5 is preferably 15 mol% or more and 20 mol% or less.

  A known vapor deposition method, sputtering method, or the like can be used to form the Au layer 6, but from the viewpoint of productivity, it is continuously formed after the AuBe layer 5 is formed by using a resistance heating vacuum vapor deposition method. It is preferable.

  Next, as the ohmic characteristic imparting step, a well-known heating device such as an electric furnace, a hot plate, or a lamp annealing furnace using infrared rays is applied to the semiconductor wafer 10 on which the p-side electrode 18 is formed, in a vacuum, in a nitrogen atmosphere or Heat treatment is performed for several seconds to several tens of minutes in a hydrogen atmosphere. By this heat treatment, the Au element and the Be element contained in the AuBe layer 5 diffuse into the p-type GaAs contact layer 3 and react with the same layer, and as shown in FIG. 1C, the p-type GaAs contact layer 3 A p-type GaAs-Au-Be alloy layer 7 is formed at the interface between the p-side electrode 18 and the p-side electrode 18. The alloy layer 7 provides ohmic characteristics between the AuBe layer 5 and the p-type GaAs contact layer 3, and the p-side electrode 18 functions as a p-type ohmic electrode.

  Note that the Be element in the AuBe layer 5 diffuses to the Au layer 6 side and precipitates on the surface of the Au layer 6 by the heat treatment in the ohmic characteristic imparting step. The deposited Be element reacts with oxygen in the air when it comes into contact with air, becomes BeO, and forms a BeO film 8.

  In the ohmic characteristic imparting step, when the heat treatment temperature is less than 300 ° C., the formation of the alloy layer 7 by the alloying reaction is insufficient and sufficient ohmic characteristics cannot be imparted to the p-side electrode 18. Conversely, when the temperature of the heat treatment exceeds 500 ° C., the alloying reaction proceeds too much, and the Ga element and As element of the p-type GaAs contact layer 3 are diffused also on the AuBe layer 5 and Au layer 6 side, and the p-side electrode The function as 18 cannot be fulfilled. Accordingly, the heat treatment temperature in the ohmic characteristic imparting step is preferably 300 ° C. or higher and 500 ° C. or lower.

  Next, as a surface treatment step, the p-side electrode 18 formed with the BeO film 8 is predetermined as a liquid mixture (volume ratio 1:10) of hydrofluoric acid (50 wt%) in which beryllium oxide is soluble and water. After being dipped and etched for a period of time, it is washed with pure water and dried. By this surface treatment step, the BeO film 8 present on the surface of the p-side electrode 18 is removed as shown in FIG.

  Next, after sequentially forming an AuGeNi layer and an Au layer on the back surface of the n-type GaAs substrate 1 by vapor deposition or the like, the n-type ohmic electrode 9 is formed by performing a predetermined heat treatment. At the time of performing this heat treatment, the BeO film 8 is not formed again on the surface of the p-side electrode 18 because the Be element sufficient to form the BeO film 8 does not remain in the p-side electrode 18. . However, when the BeO film 8 is generated again on the surface of the p-side electrode 18 by the heat treatment at the time of forming the n-type ohmic electrode 9 due to a high content of the Be element in the AuBe layer 5, the surface treatment process is performed by n You may carry out after the heat processing of the type | mold ohmic electrode 9. FIG.

  Finally, the semiconductor laser chip 12 is manufactured as shown in FIG. 1E by performing the primary cleavage and the secondary cleavage of the semiconductor wafer 10 so as to form a chip having a predetermined size.

  The semiconductor laser chip 12 manufactured by the above procedure is mounted on a base 11 such as a package as shown in FIG.

  FIG. 2A shows an example in which the p-side electrode 18 and the base 11 of the semiconductor laser chip 12 are joined by the solder material 10 provided on the base 11. 2A, the semiconductor laser chip 12 and the base 11 are joined by mounting a p-side electrode 18 of the semiconductor laser chip 12 in contact with the solder material 10 of the base 11 and then applying a predetermined pressure. The solder material 10 is melted by heating to a temperature of about 300 ° C. while being added, and the p-side electrode 18 and the solder material 10 are joined. In addition to Sn, it is possible to use a known solder material such as SnPb (tin lead), AuSn (gold tin), or In (indium) as well as Sn. When the surface layer of the p-side electrode 18 is Au, it is particularly preferable to use AuSn. Next, the semiconductor laser 14 is manufactured by joining the Au wire 13 to the n-type ohmic electrode 9 by wire bonding.

  2B, the n-type ohmic electrode 9 and the base 11 of the semiconductor laser chip 12 are joined with the conductive resin 15, and the Au wire 13 is joined to the p-side electrode 18 by wire bonding. Thus, the semiconductor laser 14a is manufactured.

  The semiconductor lasers 14 and 14 a are driven by applying a current with the p-side electrode 18 side as a positive electrode and the n-type ohmic electrode 9 side as a negative electrode, and emit laser light from the light emitting layer 2.

  As described above, in the semiconductor laser chip 12 manufactured by the manufacturing method of the present invention, the BeO film 8 formed on the surface of the p-side electrode 18 is completely removed by the surface treatment process. Therefore, in the bonding form shown in FIG. 2A, when the semiconductor laser chip 12 is mounted on the base 11, the bonding between the p-side electrode 18 and the solder material 10 by the BeO film 8 is not hindered and sufficient. The p-side electrode 18 and the solder material 10 can be joined with strength. For this reason, the mounting defects that occurred several percent to several tens of percent in the semiconductor laser chip from which beryllium oxide has not been removed are reduced to 2% or less in the semiconductor laser chip 12 manufactured by the manufacturing method of the present invention. The improvement effect was recognized.

  Further, by removing the BeO film 8, the semiconductor laser 14 is bonded to the solder material 10 over almost the entire surface of the p-side electrode 18, and the heat generated in the semiconductor laser chip 12 is effectively based on the solder material 10. Since it is conducted to the base 11, heat dissipation is extremely high. For this reason, the deterioration of the element characteristics that occurred in the semiconductor laser chip from which beryllium oxide was not removed was not observed in the semiconductor laser chip 12 manufactured by the manufacturing method of the present invention.

  Also in the bonding mode shown in FIG. 2B, the removal of the BeO film 8 does not hinder the bonding between the p-side electrode 18 and the Au wire 13, so that the beryllium oxide is removed. In the semiconductor laser chip 12 that was produced by the manufacturing method of the present invention, the wire bonding failure that occurred several percent in the semiconductor laser chip that was not produced was reduced to 1% or less, and this also showed a significant improvement effect.

  Next, as a second embodiment of the method for manufacturing a semiconductor device according to the present invention, an example in which the present invention is applied to a method for manufacturing a junction field effect transistor will be described with reference to FIGS.

First, as shown in FIG. 3A, an n-type GaAs layer 22 (Si doping concentration: 1 × 10 ¹⁷ cm ⁻³ ) having a thickness of 0.3 μm is formed on a GaAs substrate 21 by a metal organic chemical vapor deposition method or the like. It is formed by a known method.

  Next, in order to perform element isolation, a region to be an active layer of the junction field effect transistor is masked by photolithography, and a part of the n-type GaAs layer 22 and the GaAs substrate 21 in other regions is wet etched. Remove. Thereby, as shown in FIG. 3B, a convex n-type GaAs layer 22 serving as an active layer is formed on the GaAs substrate 21.

Next, as shown in FIG. 3C, the first SiN _x (silicon nitride) film 24 having a thickness of 200 nm is used on the surface of the n-type GaAs layer 22 and the GaAs substrate 21 exposed by the above etching. It is formed by a CVD (Chemical Vapor Deposition) method.

Next, as shown in FIG. 3D, the position where the gate part 26 and the gate guard ring part 27, which will be described later, are formed on the first SiN _x film 24 is positioned at a position where photolithography and a fluorocarbon gas are used. Next, the Zn element is selectively thermally diffused from the opening of the first SiN _x film 24 to a predetermined depth in the n-type GaAs layer 22 and the GaAs substrate 21. As a result, as shown in FIG. 4A, a gate portion 26 formed as a p-type semiconductor is formed on the n-type GaAs layer 22 and a gate guard ring portion 27 formed as a p-type semiconductor is formed on the GaAs substrate 21. The Zn element is preferably diffused by an open tube diffusion method using DMZn (dimethylzinc) gas and AsH ₃ (arsine) gas as a diffusion source at a temperature of about 600 ° C. It is also possible to use ZnAs ₂ as the diffusion source. Further, a sealed tube diffusion method may be used instead of the open tube diffusion method.

Next, a predetermined position of the first SiN _x film 24 on the n-type GaAs layer 22 is opened by a photolithography method and a reactive ion etching method using a fluorocarbon gas. Thereafter, an AuGeNi layer and an Au layer are sequentially formed in this opening by vapor deposition or the like, thereby forming a drain electrode 28 and a source electrode 29 on the n-type GaAs layer 22 as shown in FIG. 4B. To do.

  Next, as an electrode forming step, an AuBe layer 5 having a thickness of 100 nm and an Au layer 6 having a thickness of 200 nm are successively formed on the gate portion 26 and the gate guard ring portion 27 by using a photolithography method and a resistance heating vacuum deposition method. Form a film. As a result, as shown in FIG. 4C, the p-side electrode 18a, which is a gate electrode, is formed on the gate portion 26, and the p-side electrode 18b, which is a gate guard ring electrode, is formed on the gate guard ring portion 27, respectively.

  Next, as an ohmic property imparting step, heat treatment is performed at 400 ° C. in a nitrogen atmosphere. As a result, the Au element and the Be element contained in the AuBe layer 5 diffuse into the gate part 26 and the gate guard ring part 27, and the AuBe layers of the gate part 26 and the gate guard ring part 27 as shown in FIG. 5 is the alloy layer 7. The alloy layer 7 provides ohmic characteristics to the p-side electrodes 18a and 18b, and the p-side electrode 18a functions as a gate electrode and the p-side electrode 18b functions as a gate guard ring electrode. By this heat treatment, the Be element in the AuBe layer 5 is diffused also to the Au layer 6 side, and is deposited on the surfaces of the p-side electrodes 18a and 18b. The deposited Be reacts with oxygen in the air when it comes into contact with air to form a BeO film 8.

Next, as a surface treatment step, the buffered hydrofluoric acid in which the mixing ratio of hydrofluoric acid and ammonium fluoride is adjusted so that the etching rate of the first SiN _x film 24 is several tens of nm / min or less is predetermined time. Immerse. Thereby, as shown in FIG. 5A, the BeO film 8 formed on the surfaces of the p-side electrodes 18a and 18b is removed.

Next, as shown in FIG. 5B, a second SiN _x film 33 having a thickness of 500 nm is formed on the first SiN _x film 24 on which each electrode is formed by a CVD method using plasma.

Next, as shown in FIG. 5C, openings of a predetermined size are formed in the second SiN _x film 33 on each of the drain electrode 28, the source electrode 29, and the p-side electrode 18b that is a gate guard ring electrode. The part is formed by a photolithography method and a reactive ion etching method using a fluorocarbon-based gas.

Finally, as shown in FIG. 5 (d), photolithography and sputtering or by vapor deposition or the like for example Mo layer in the opening of the second the SiN _x film 33, Ni layer, Au layer or a Ti layer, Pt layer, A wiring metal layer 35 is formed by sequentially forming an Au layer or the like. As a result, the junction field effect transistor 36 is manufactured. This junction field effect transistor 36 has a drain electrode 28 as a positive electrode via a wiring metal layer 35, a source electrode 29 as a negative electrode, and a gate electrode p serving as a gate electrode via a p-side electrode 18b. Driving is performed by applying a positive or negative bias to the side electrode 18a.

  As described above, in the junction field effect transistor 36 manufactured by the manufacturing method of the present invention, the BeO film 8 generated on the surfaces of the p-side electrodes 18a and 18b is completely removed by the surface treatment process. Therefore, the wiring metal layer 35 is formed directly on the p-side electrode 18b, and the gate resistance value between the p-side electrode 18b and the wiring metal layer 35 does not increase or vary greatly. For this reason, the deterioration of the high frequency characteristics or the like that has occurred in the junction field effect transistor from which beryllium oxide has not been removed does not occur in the junction field effect transistor 36 manufactured by the manufacturing method of the present invention, and the characteristic failure rate. Reduction and yield improvement effect were observed.

  Next, as a third embodiment of the method for manufacturing a semiconductor device according to the present invention, an example in which the present invention is applied to a junction field effect transistor having a structure different from that of the second embodiment will be described with reference to FIGS.

First, Si is implanted into a predetermined portion of the GaAs substrate 21 using a photolithography method and an ion implantation method to form an n-type semiconductor. As shown in FIG. 6A, the active layer of the junction field effect transistor is formed. The n-type GaAs layer 22 (Si doping concentration is 1 × 10 ¹⁷ cm ⁻³ ) having a thickness of 0.3 μm is selectively formed.

Next, a first SiN _x film 24 having a thickness of 200 nm is formed on the surfaces of the GaAs substrate 21 and the n-type GaAs layer 22 by a CVD method using plasma. Next, a region where the gate portion 26 and the gate guard ring portion 27 of the first SiN _x film 24 are formed is opened using a photolithography method and a reactive ion etching method using a fluorocarbon-based gas. Next, using the first SiN _x film 24 as a mask, a Be element is ion-implanted from the opening of the first SiN _x film 24 to a predetermined depth in the n-type GaAs layer 22 and the GaAs substrate 21. Inject selectively. As a result, as shown in FIG. 6B, a gate portion 26 formed into a p-type semiconductor in the n-type GaAs layer 22 and a gate guard ring portion 27 formed into a p-type semiconductor in the GaAs substrate 21 are formed.

Next, a predetermined portion of the first SiN _x film 24 on the n-type GaAs layer 22 is opened by a photolithography method and a reactive ion etching method using a fluorocarbon-based gas. Next, an AuGeNi layer and an Au layer are sequentially formed in the opening by vapor deposition or the like, so that the drain electrode 28 and the source electrode 29 are respectively formed on the n-type GaAs layer 22 as shown in FIG. Form.

  Next, as an electrode forming step, an AuBe layer 5 having a thickness of 100 nm and an Au layer 6 having a thickness of 200 nm are successively formed on the gate portion 26 and the gate guard ring portion 27 by using a photolithography method and a resistance heating vacuum deposition method. Form. As a result, as shown in FIG. 6D, the p-side electrode 18a, which is a gate electrode, is formed on the gate portion 26, and the p-side electrode 18b, which is a gate guard ring electrode, is formed on the gate guard ring portion 27, respectively. .

Next, a second SiN _x film 33 having a thickness of 500 nm is formed on the first SiN _x film 24 on which each electrode is formed under a temperature condition of 300 ° C. or more by a CVD method using plasma. At this time, by the heat at the time of forming the second SiN _x film 33, the Au element and the Be element contained in the AuBe layer 5 are diffused into the gate portion 26 and the gate guard ring portion 27, as shown in FIG. The interface portion of the gate portion 26 and the gate guard ring portion 27 with the AuBe layer 5 becomes the alloy layer 7. The alloy layer 7 provides ohmic characteristics to the p-side electrodes 18a and 18b, and the p-side electrode 18a functions as a gate electrode and the p-side electrode 18b functions as a gate guard ring electrode. Therefore, in the manufacturing method of Example 3, the step of forming the second SiN _x film 33 also serves as the ohmic characteristic imparting step. The Be element in the AuBe layer 5 is diffused also to the Au layer 6 side by the heat at the time of forming the second SiN _x film 33, and is deposited as Be precipitates 8a on the surfaces of the p-side electrodes 18a and 18b.

Next, as shown in FIG. 7B, an opening having a predetermined size is formed in the second SiN _x film 33 on each of the drain electrode 28, the source electrode 29, and the p-side electrode 18b that is the gate guard ring electrode. The part is formed by a photolithography method and a wet etching method. In the etching at this time, buffered hydrofluoric acid in which hydrofluoric acid and ammonium fluoride are mixed at a predetermined ratio is used as an etchant. By this etching, a predetermined position of the second SiN _x film 33 is opened and the Be precipitate 8a on the surface of the p-side electrode 18b is exposed. The exposed Be precipitate 8a is oxidized to BeO. However, as described above, the etchant used here contains hydrogen fluoride that can be used in the surface treatment process. It is etched and removed quickly by the etchant. Therefore, in the manufacturing method of Example 3, the etching process for forming the opening in the second SiN _x film 33 also serves as the surface treatment process.

Finally, as shown in FIG. 7 (c), photolithography and sputtering or by vapor deposition or the like for example Mo layer in the opening of the second the SiN _x film 33, Ni layer, Au layer or a Ti layer, Pt layer, A wiring metal layer 35 is formed by sequentially forming an Au layer or the like. As a result, the junction field effect transistor 36a is manufactured.

As described above, in the junction field effect transistor 36a produced by the manufacturing method of the present invention, BeO on the surface of the p-side electrode 18b is completely removed by the etching process to the second SiN _x film 33 which also serves as a surface treatment process. Has been. Therefore, as in the second embodiment, the wiring metal layer 35 is formed directly on the p-side electrode 18b, and the gate resistance value between the p-side electrode 18b and the wiring metal layer 35 does not increase or vary greatly. For this reason, in the junction field effect transistor 36a, the high frequency characteristics and the like are not deteriorated, and the effect of reducing the characteristic defect rate and the yield is recognized.

Furthermore, in Example 3, the process of forming the second SiN _x film 33 also serves as an ohmic characteristic imparting process, and the etching process for providing an opening in the second SiN _x film 33 also serves as a surface treatment process. . For this reason, it is possible to remove BeO on the surface of the p-side electrode 18b without increasing the number of manufacturing steps, and to further improve productivity.

  From the above, according to the semiconductor element manufacturing method of the present invention, BeO generated by heat at the time of imparting ohmic characteristics to the surface of the p-side electrodes 18, 18a, 18b having the AuBe layer 5 is removed by etching. The p-side electrodes 18, 18a, and 18b having excellent bonding properties can be formed without complicating the electrode forming process.

  The etchant used in the surface treatment step can be used without particular limitation as long as it dissolves beryllium oxide and does not adversely affect the semiconductor layer. Among them, the etchant containing hydrogen fluoride used in the above examples can easily etch BeO at room temperature even in a dilute solution having a hydrogen fluoride weight ratio of several percent or less. It is particularly suitable as an etchant for the surface treatment process.

In Example 2 and Example 3, an aqueous solution containing hydrogen fluoride mixed with an appropriate amount of ammonium fluoride is used as an etchant in the surface treatment process. This is because, by mixing ammonium fluoride, rapid etching by hydrogen fluoride is alleviated and BeO is selectively removed by etching without etching the SiN _x film. Thus, other compounds can be added as appropriate to the aqueous solution containing hydrogen fluoride depending on the application. Furthermore, the mixing ratio of hydrogen fluoride and water can be appropriately changed, and the etchant solvent is not particularly limited to water.

  In this embodiment, the manufacture of the semiconductor laser and the junction field effect transistor is used as an example. However, the present invention is not particularly limited to this, and AlGaAs, AlGaInP, InP, and the like that require an ohmic electrode having an AuBe layer are used. Semiconductor elements using III-V semiconductor materials, such as high-frequency integrated elements, high-frequency diodes, light-emitting diodes, light-emitting diode arrays, semiconductor laser arrays, light-receiving elements, integrated elements having light-emitting / light-receiving elements (OEIC), etc. Besides being applicable to manufacturing, the present invention can be modified and implemented without departing from the gist of the present invention.

It is a figure explaining applying this invention to the manufacturing method of a semiconductor laser chip. It is a schematic diagram which shows joining of the semiconductor laser chip produced by this invention. It is a figure explaining applying this invention to the manufacturing method of a junction type field effect transistor. It is a figure explaining applying this invention to the manufacturing method of a junction type field effect transistor. It is a figure explaining applying this invention to the manufacturing method of a junction type field effect transistor. It is a figure explaining applying this invention to the manufacturing method of the junction field effect transistor of a 2nd form. It is a figure explaining applying this invention to the manufacturing method of the junction field effect transistor of a 2nd form. It is a figure explaining the conventional electrode formation method of a semiconductor element.

Explanation of symbols

5 AuBe layer
6 Au layer
7 Alloy layer
8 BeO film
8a Be precipitate
18, 18a, 18b p-side electrode

Claims (2)

In a method for manufacturing a semiconductor element,
An electrode forming step of forming an electrode containing Be (beryllium) in the semiconductor layer;
After the electrode formation step, the semiconductor layer and the electrode are subjected to a heat treatment to make the electrode ohmic electrode, and an ohmic property imparting step,
After the ohmic property imparting step, a surface treatment step of surface-treating the electrode with a solution in which beryllium oxide is soluble,
A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 1, wherein the solution contains hydrogen fluoride.

Images