JP2008028855A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To highly accurately A/D convert an AC component of an input voltage by including a removal function for removing sampling capacitance and a DC component of an input signal. <P>SOLUTION: A primary delta-sigma modulation circuit 1 samples an input voltage VIN under a clock signal ϕ1, performs charge transfer to an electrostatic capacitor Cs under a clock signal ϕ2, and performs voltage integrating operation. Under the clock signal ϕ2, a charge component corresponding to a DC offset voltage of the input voltage VIN is subtracted from the amount of charges to be transferred to an electrostatic capacitor Cs0, thereby removing the DC component. Actually, under the clock signal ϕ2, input-side switches S1-0 to S1-2<SP>n</SP>-1 of divided electrostatic capacitors Csd0-Csd2<SP>n</SP>-1 are changed over to either a high voltage reference voltage VT1 or a low voltage reference voltage VB1, thereby regulating the amount of charges to be transferred to the electrostatic capacitor Cs0. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for converting an analog input signal into a digital signal, and more particularly to a technique effective for analog / digital conversion using a delta-sigma modulation circuit.

  For a digital video camera or the like, a circuit that removes the DC component VDC1 of the input signal from the input signal as shown in FIG. 12 and performs analog / digital conversion (hereinafter A / D conversion) only on the AC signal component VAC1 ( For example, Patent Document 1) is widely used.

  This circuit includes, for example, first and second resistors, an amplifier, a D / A (Digital / Analog) converter, and an A / D converter. One connection portion of the first resistor is connected so that an input signal Vin output from a gyro sensor or the like is input, and the other connection portion of the first resistor is connected to the negative ( -) Side input section is connected.

  A digital value for removing an input DC component is connected to an input unit of the D / A converter. The offset data digital value for removing the input DC component is a signal that controls the value output from the D / A converter to be the same as the DC component VDC1 of the input signal.

  The positive (+) input section of the amplifier is connected to the output section of the D / A converter, and a second resistor is connected to the output section and negative (−) input section of the amplifier. ing.

  In addition, an input unit of an A / D converter is connected to the output unit of the amplifier, and a digital conversion result is output from the A / D converter.

  In this case, the conversion transfer function is expressed by the following equation.

Vad = R2 / R1 × (Vin−Vdac) + Vdac
However, Vad is an output voltage of the amplifier, and Vdac is an output value of the D / A converter.

  With such a configuration, the signal obtained by amplifying only the signal from which the DC component is removed from the input by the non-inverting circuit of the input unit is A / D converted, that is, only the AC signal component VAC1 is A / D converted.

By amplifying only the AC component, the accuracy of the subsequent A / D converter can be relaxed from n-bit to (n-log ₂ k) -bit (where n is resolution and k is amplification). Rate).

  When the DC component VDC1 is also A / D converted at the same time, it is used for conversion of a DC component that does not require n-bit resolution, but is amplified and uses all the n-bit resolution for the DC component VAC1. As a result, the resolution of the necessary signal components can be effectively improved.

The input DC component can be removed by outputting an arbitrary voltage with the D / A converter. As described above, the digital code of the offset data digital value for removing the input DC component input to the D / A converter is controlled by, for example, a microcontroller. If the input has a plurality of channels, it has a plurality of D / A converter digital codes. When the input analog channel is switched, the digital codes of the A / D converter are also switched (for example, see Patent Document 2).
JP-A-8-149363 JP-A-11-205151

  However, the present inventors have found that the technique for removing the DC component VDC1 of the input signal as described above has the following problems.

  That is, when there are a plurality of input channels and the input DC removal voltage is different, when switching channels, it is necessary to change the output of the D / A converter until the output of the D / A converter is stabilized. There is a problem that it takes time.

  Further, when the input channel is switched every sample, there is a problem that if the settling time of the D / A converter is long, the conversion time until the A / D conversion result is obtained becomes long. As a method of ignoring the settling time of the D / A converter, for example, a circuit configuration having a D / A converter and a differential amplifier for each input channel can be considered, but this is disadvantageous in terms of area and power.

  Furthermore, in addition to the A / D converter, a differential amplifier circuit for performing differential amplification and a D / A converter are required, which increases the number of components.

  For example, when a high-precision A / D converter such as a delta-sigma A / D converter is used as the A / D converter, a DC component removal circuit is not required, but a delta-sigma A / D converter Quantization noise is required for A / D conversion accuracy + gain amplification (thermal noise in terms of input is the same).

  When high-precision A / D conversion is required, the D / A converter and the differential amplifier circuit also need to be high-precision, and in the case of being mounted on a semiconductor integrated circuit device of a CMOS (Complementary Metal Oxide Semiconductor) process, In order to reduce noise, there is a problem that current consumption and element area must be increased.

  An object of the present invention is to provide a technique capable of performing A / D conversion of an AC component of an input voltage with high accuracy by having a removal function of removing a sampling capacitor and a DC component of an input signal.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a semiconductor integrated circuit device having a delta-sigma A / D converter, and the delta-sigma A / D converter includes a D / A converter that removes a DC component of an input signal. Is.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the present invention, the D / A conversion unit samples an input voltage and transfers charge to an integration capacitor, and is connected to the sampling capacitor, and is switched to an arbitrary reference voltage to transfer charge to the integration capacitor. And a switch unit for adjusting the amount.

  According to the present invention, the delta-sigma A / D converter includes an integrator including the D / A converter, a feedback D / A converter having a feedback capacitor, and an integrating amplifier. is there.

  Furthermore, the present invention changes the capacitance ratio between the sampling capacitor and the feedback capacitor, thereby amplifying the input signal by giving a gain to the integrator, and relatively reducing the delta-sigma modulator quantization noise. It is.

  In the present invention, the delta-sigma A / D converter has a plurality of input channels to which an input voltage is input, and the integrator is commonly connected to the plurality of input channels.

  Further, according to the present invention, the delta sigma A / D converter is of a double sampling type in which the input gain is doubled by alternately repeating the differential input during sampling and charge transfer.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The AC component in the analog input signal can be A / D converted with high accuracy.

  (2) Further, the semiconductor integrated circuit device can be reduced in size.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is an explanatory diagram showing a configuration of a first-order delta-sigma modulation circuit according to Embodiment 1 of the present invention, and FIG. 2 is a diagram of an A / D converter configured using the first-order delta-sigma modulation circuit of FIG. FIG. 3 is a block diagram showing an example, FIG. 3 is a timing chart of a clock signal generated by a switched capacitor circuit clock generation source provided in the primary delta sigma modulation circuit of FIG. 1, and FIG. 4 is a primary delta sigma modulation of FIG. FIG. 5 is an explanatory diagram showing a decoder result for the decoder circuit provided in the circuit to realize the DC removal voltage Vof, and FIG. 5 is a 4-bit weighted DC component removal D / A for the first-order delta-sigma modulation circuit 1 of FIG. 6 is an explanatory diagram when applied to a converter, FIG. 6 is an explanatory diagram when the first-order delta-sigma modulation circuit of FIG. 1 following FIG. 5 is applied to a 4-bit weighted DC component removal D / A converter, and FIG. Is the primary of FIG. Is a block diagram showing an example of a semiconductor integrated circuit device constructed using Rutashiguma modulation circuit.

  In the first embodiment, the n-bit first-order delta-sigma modulation circuit 1 removes the DC component of the input signal and performs analog / digital conversion on only the AC signal component. As shown in FIG. 1, the primary delta-sigma modulation circuit 1 includes an A / D converter 2, a data latch circuit 3, a feedback D / A converter 4, a switched capacitor circuit clock generation source 5, a decoder circuit 6, and a charge. The D / A converter 7 is configured.

The charge D / A conversion unit 7 includes a sampling capacitor unit 7a including electrostatic capacitance elements Csd0 to Csd2 ⁿ -1 serving as a sampling capacitor, and a DC component removal D / A including switches S1-0 to S1-2 ⁿ -1. The converter 7b is shared with the D / A converter that removes the sampling capacity and the input DC component.

One connection of the switch S1-0~S1-2 ⁿ -1 has a first to third connecting portion, the first connecting portion of the switch S1-0~S1-2 ⁿ -1, high The voltage reference voltage VT1 is connected to be supplied.

The second connecting part of the switch S1-0~S1-2 ⁿ -1, the input voltage VIN which is output from a sensor is connected as input. The third connection of the switch S1-0~S1-2 ⁿ -1, is connected to a low voltage reference voltage VB1 is supplied.

To the other connecting part of the switch S1-0~S1-2 ⁿ -1, one connection of the capacitance element Csd0~Csd2 ⁿ -1 is connected. Based on the control signal output from the decoder circuit 6, the switches S1-0 to S1-2 ⁿ -1 switch the connection destination to any one of the first to third connection units.

The decoder circuit 6 controls switching of the switches S1-0~S1-2 ⁿ -1 based on the digital code of the input DC component removing digital values of the DC component removing D / A converter 7b.

  The A / D conversion unit 2 includes an integrator amplifier circuit 2a and a comparator 2b. The integrator amplifier circuit 2a includes switches S2 and S3, a capacitance element Cs0 serving as an integration capacitor, and an amplifier Amp.

  In the first-order delta-sigma modulation circuit 1, an integrator is configured by the integrator amplifier circuit 2 a, the feedback D / A converter 4, and the charge D / A converter 7.

One connection portion of the switches S2 and S3 is connected to the other connection portion of the capacitance elements Csd0 to Csd2 ⁿ -1, respectively, and the other connection portion of the switch S2 is connected to the negative (− ) Side input section is connected. A reference potential VSS is connected to the other connection portion of the switch S3.

  A capacitive element Cs0 is connected between the negative (−) side input part and the output part of the amplifier Amp, and a reference potential VSS is connected to the positive (+) side input part of the amplifier Amp. Yes. One input portion of the comparator 2b is connected to the output portion of the amplifier Amp, and the reference potential VSS is connected to the other input portion of the comparator 2b. The data latch circuit 3 is connected to the output section of the comparator 2b. Then, the modulation circuit output signal VDS is output from the output section of the data latch circuit 3.

  The feedback D / A converter 4 includes a capacitance element Cfd0 serving as a feedback D / A converter capacitance and a switch S4. The other connection portion of the capacitance elements Csd0 to Csd2n-1 is connected to one connection portion of the capacitance element Cfd0.

  One connection part of the switch S4 is connected to the other connection part of the capacitive element Cfd0. The other connection portion of the switch S4 has first to third connection portions, and is connected to the first connection portion so that the high-voltage side reference voltage VT2 is supplied. The reference potential VSS is connected to the second connection portion of the switch S4, and the third connection portion of the switch S4 is connected so as to be supplied with the low-voltage side reference voltage VB2.

  FIG. 2 is a block diagram illustrating an example of an A / D converter ADC configured using the first-order delta-sigma modulation circuit 1.

  The A / D converter ADC includes a first-order delta sigma modulation circuit 1 and a digital filter circuit 10 as shown in the figure. In this case, a digital filter circuit 10 is connected to the subsequent stage of the primary delta sigma modulation circuit 1, and the modulation circuit output signal VDS output from the primary delta sigma modulation circuit 1 is input to the digital filter circuit 10. Connected so that.

  Here, in the first-order delta-sigma modulation circuit 1, it is known that the input voltage VIN, the quantization noise Q generated when quantizing by the comparator 2b, and the modulation circuit output signal VDS have the following relationship. Yes. It is described by an integrator z function, and z in the equation represents the z function. Q is generally expressed as white noise.

From the above equation, it can be seen that the input voltage VIN becomes a signal delayed by one sampling frequency, does not change, and the quantization noise Q is multiplied by the term (1-z ⁻¹ ) and can be expressed by a first-order differentiation. Here, it is known that the following equation is established when the sampling frequency fs is expressed as f.

  That is, the low frequency region has a value almost close to 0, and can be expressed by a sine wave that is maximum at fs / 2. Therefore, quantization noise due to delta-sigma modulation is unevenly distributed around fs / 2, and if high frequency noise is removed by a digital filter, the energy of quantization noise is reduced, and an A / D conversion result with high resolution is obtained. Can be obtained.

  FIG. 3 is a timing chart showing the timing of the clock signals φ1 and φ2 generated from the clock signal CLK input from the switched capacitor circuit clock generation source 5 to the outside.

  The primary delta-sigma modulation circuit 1 samples the input voltage VIN when the clock signal is φ1, and performs charge transfer to the electrostatic capacitance element Cs when the clock signal is φ2 to perform voltage integration.

  In the case of this clock signal φ2, DC component removal can be realized by subtracting the charge corresponding to the DC component voltage of the input voltage VIN from the amount of charge transferred to the capacitive element Cs0.

In practice, the input side of the switch S1-0~S1-2 ⁿ -1 of the divided capacitance device Csd0~Csd2 ⁿ -1 high voltage the reference voltage VT1 or undervoltage reference voltage, when the clock signal .phi.2 VB1 By switching to any of the above, the amount of charge transferred to the capacitive element Cs0 is adjusted.

  Next, it is expressed by an expression.

  Here, Qdac represents the amount of charge generated in the operation of DC component removal D / A conversion, m represents the code of the DC component removal D / A converter 7b, and DC removal of the DC component removal D / A converter 7b. The voltage Vof can be expressed as follows.

  The change voltage ΔVs of the integrator output by the input is as follows.

  From the above operation, the amount of charge integrated by the integrator is the amount of charge corresponding to the voltage value obtained by removing the DC removal voltage Vof from the input voltage VIN.

To utilize the charge transfer, the electrostatic capacitance of the DC component removing D / A converter the settling time switch S1-0~S1-2 ⁿ -1 of ON resistance and capacitance elements Csd0~Csd2 ⁿ -1, integration Determined by the settling time of the amplifier circuit 2a. This is the same as the settling time in a normal delta-sigma modulation circuit, and there is no time penalty due to the built-in D / A converter and the operation of removing the input DC component.

4, for realizing the DC removal voltage Vof of the formula 5 is an explanatory diagram showing a decoder results switch S1-0~S1-2 ⁿ -1 of the decoder circuit 6.

In FIG. 4, the clock signal φ1 is all connected to the input side. Further, at the time of the clock signal φ2, if m = 0, all are connected so that the low voltage reference voltage VB1 is supplied, and there is a switch connected so that the high voltage reference voltage VT1 is supplied as m increases. As m = 2 ⁿ −1, 2 ⁿ⁻¹ switches are connected such that the high voltage reference voltage VT1 is supplied.

  Next, an example in which the n-bit first-order delta-sigma modulation circuit 1 according to the present invention is actually applied to a 4-bit weighted DC component removal D / A converter will be described with reference to FIG. 5 and FIG. .

  Here, since the charge D / A conversion unit 7 has a 4-bit weight, the charge D / A conversion unit 7 includes switches S1-0 to S1-4 and capacitance elements Csd0 to Csd4.

  First, during the period of the clock signal φ1, the switches S1-0 to S1-4 provided in the DC component removal D / A converter 7b are in a connected state as shown in FIG. The capacitive elements Csd0 to Csd3 are all charged with the input voltage VIN.

  Subsequently, in the case of the clock signal φ2, the switches S1-0 to S1-4 are transferred to the electrostatic capacitance element Cs0 serving as an integration capacitor, and are connected as shown in FIG.

  At this time, the capacitive elements Csd0 to Csd3 are connected as shown in FIG. 6 according to the offset voltage. In the case of FIG. 6, the charge corresponding to the voltage obtained by subtracting the voltage of 11/16 (VT1-VB1) from the input voltage VIN is transferred.

  The integrator voltage is settled, the integrator output is held at the falling edge of the clock signal φ2, the comparator 2b determines the voltage, the output is fixed at the rising edge of the clock signal φ1, and the output signal VDS of the modulation circuit is fixed. It becomes.

  When the clock signal is φ1, the feedback D / A converter is placed in a charging state in which the output of the delta-sigma modulation circuit is subtracted from the input. Then, the clock signal φ1 and the clock signal φ2 are repeated, a delta-sigma modulation operation is performed, and signal processing is performed by the digital filter circuit 10 connected to the subsequent stage, thereby realizing a high-resolution A / D converter ADC. Can do.

  In addition, when the required resolution of the input signal VIN output from the sensor is high and high-precision A / D conversion is required, only the input portion of the integrator amplifier circuit 2a needs to be high-precision. Therefore, the number of parts to be made can be reduced, and current consumption and area can be reduced.

  FIG. 7 is a block diagram showing an example of a semiconductor integrated circuit device 8 configured using the first-order delta-sigma modulation circuit 1 according to the present invention.

  The semiconductor integrated circuit device 8 includes a first-order delta-sigma modulation circuit 1, an A / D converter ADC composed of an analog input channel 9 and a digital filter circuit 10, a register 11, a control circuit 12, a CPU (Central Processing Unit). ) 13, a memory 14, and a digital code storage unit 15. In addition, the register 11, the control circuit 12, the CPU 13, the memory 14, and the digital code storage unit 15 are connected to each other via a bus 16.

  The analog input channel 9 to which the analog signal is input has, for example, three channels, and the control circuit 12 controls which channel is selected. When the channel of the analog input channel 9 changes, the input DC component to be removed changes, so that the digital code to be input to the DC component removal D / A converter 7b in the first-order delta-sigma modulation circuit 1 according to the input channel Is changed by the control circuit 12.

  For example, in the analog input channel 9, D / A conversion is performed for the analog input 1 using the digital code 1 in the digital code storage unit 15, and the digital code 2 in the digital code storage unit 15 is performed for the analog input 2. D / A conversion is performed using.

  The first-order delta sigma modulation circuit 1 receives a value obtained by removing the input DC component by the output of the DC component removal D / A converter 7b, and performs delta sigma modulation.

  In some cases, the gain is selected by the control circuit 12, and the analog input from which the DC component is removed to the first-order delta-sigma modulation circuit 1 is amplified. As a result of the delta-sigma modulation, quantization noise in a high frequency band is removed by the digital filter circuit 10, and an A / D conversion result with high resolution can be obtained. The D / A conversion result output from the digital filter circuit 10 is stored in the register 11 corresponding to each channel.

  When the conversion is completed, the control circuit 12 issues an A / D conversion start signal and conversion of the next analog channel starts. The A / D conversion result is stored in the memory 14, or signal processing is performed by the CPU 13, and various processes are performed.

  Thus, according to the first embodiment, the first-order delta-sigma modulation circuit 1 can perform D / A conversion having a function of removing the input DC component of the input signal VIN and having a short settling time. The AC component of VIN can be A / D converted with high accuracy.

  Further, the settling time of the DC component removal D / A converter 7b can be made extremely shorter than the oversampling frequency.

  Further, the DC component removal D / A converter 7b can eliminate the need for an analog element such as a resistor or a capacitance element other than the circuit used in the delta-sigma modulation circuit, or an amplifier circuit, so that the semiconductor integrated circuit The apparatus 1 can be reduced in size.

Further, the delta-sigma modulation circuit 1 includes capacitance elements Csd0 to Csd2 ⁿ −1 serving as sampling capacitors of the DC component removal D / A converter 7b and a feedback D / A converter capacitor of the feedback D / A converter 4. By adjusting the capacitance ratio with the electrostatic capacitance element Cfd0, it is possible to give the delta-sigma modulation circuit gain and amplify the input signal VIN.

  Assuming that the conversion accuracy for a certain small amplitude AC signal is the same, the in-band quantization noise accuracy of the delta-sigma modulation circuit 1 can be relatively lowered by amplification.

When n-bit resolution is required for the amplitude A of the input signal VIN, when the gain is 1, the quantization noise specification of the delta-sigma modulation circuit 1 is n-bit, but the amplification is k times. In this case, (n-log ₂ k) -bit is obtained, and the quantization noise accuracy of the delta-sigma modulation circuit 1 can be relaxed.

For example, in FIG. 12, when it is necessary to perform A / D conversion of the input AC component VAC1 by n-bit, when it is not amplified, and when (VT2-VB2) / VAC1 = h, necessary A / D conversion is performed. The resolution of the device is (n + log ₂ h) -bit.

Here, when only VAC1 is multiplied by k, the resolution of the A / D converter becomes (n + log ₂ h−log ₂ K) −bit, which can be relaxed.

(Embodiment 2)
FIG. 8 is a circuit diagram showing a configuration of a first-order delta-sigma modulation circuit according to Embodiment 2 of the present invention.

  In the first embodiment, the case where the first-order delta-sigma modulation circuit 1 has a single-end configuration has been described, but it is natural that the same implementation can be performed with a delta-sigma modulation circuit with a fully differential configuration.

  In addition, by adopting a fully differential configuration for the delta-sigma modulation circuit, it is possible to cancel the switch noise and other common-mode noise components and improve the accuracy.

  FIG. 8 is a circuit diagram illustrating a configuration example of the delta sigma modulation circuit 1 having a fully differential configuration.

  In this case, the delta-sigma modulation circuit 1 includes an A / D converter 2, a data latch circuit 3, feedback D / A converters 4a and 4b, a switched capacitor circuit clock generation source 5, a decoder circuit 6, and a charge D / A converter. 7, a switch S1T, and a capacitance element Csdp serving as a sampling capacitor.

One connection portion of the switch S1T is provided with first and second connection portions. An input signal VIN is connected to the first connection portion of the switch S1T. The second connection of the switch S1T, and to the second connection of the switch S1-0~S1-2 ⁿ -1, the reference potential VSS is connected.

  The A / D conversion unit 2 includes an integrator amplifier circuit 2a1 and a comparator 2b. The integrator amplifier circuit 2a1 includes switches S2T, S2B, S3T, and S3B, capacitance elements Cs0 and Cs1 serving as integration capacitors, and an amplifier Amp.

  The feedback D / A converter 4a includes a capacitance element Cfd0 serving as a feedback D / A converter capacitance, and a switch S4T. The feedback D / A converter 4b includes a feedback D / A converter capacitance. The capacitance element Cfd1 and the switch S4B.

  One connection portion of the capacitance element Cdsp is connected to the other connection portion of the switch S1T, and one connection portion of the capacitance element Cfd0 is connected to the other connection portion of the capacitance element Cdsp. , One connecting portions of the switches S2T and S3T are respectively connected.

  The other connection portion of the switch S2T is connected to the negative (−) side input portion of the amplifier Amp and one connection portion of the capacitive element Cs0. A reference potential VSS is connected to the other connection portion of the switches S3T and S3B.

One connection portion of the switch S3B and one connection portion of the switch S2B and the other connection portions of the capacitance elements Csd0 to Csd2 ⁿ −1 and Cfd1 are connected to one connection portion of the switch S3B. The other connection portion of the switch S2B is connected to the positive (+) side input portion of the amplifier Amp and one connection portion of the capacitive element Cs1.

  Further, the positive (+) side output portion of the amplifier Amp is connected to the other connection portion of the capacitive element Cs0 and one input portion of the comparator 2b, respectively, and the negative (−) of the amplifier Amp. The other output part of the capacitive element Cs1 and the other input part of the comparator 2b are connected to the side output part, respectively.

  One connection portion of the switch S4T is connected to the other connection portion of the capacitive element Cfd0. The other connection portion of the switch S4T has first to third connection portions, and is connected to the first connection portion so that the high-voltage side reference voltage VT2 is supplied. The reference potential VSS is connected to the second connection portion of the switch S4, and the third connection portion of the switch S4T is connected to the low voltage side reference voltage VB2.

  One connection portion of the switch S4B is connected to the other connection portion of the capacitive element Cfd1. The other connection part of the switch S4B has first to third connection parts, and the first connection part is connected to be supplied with the high-voltage side reference voltage VT2, and the second connection part of the switch S4. Is connected to the reference potential VSS, and the third connection portion of the switch S4B is connected to the low voltage side reference voltage VB2.

  Other connection configurations are the same as those in FIG.

  In this case, since only the difference component of the signal is integrated in the integrator amplifier circuit 2a1 serving as a differential integrator, if the charge amount corresponding to a desired removal voltage is generated in the charge D / A conversion unit 7. The input removal voltage can be canceled out.

  Further, even if the node 1 in FIG. 8 is not fixed to the common-mode voltage and is made a floating node, a fully differential operation is possible. In this case, since the common mode level of the amplifier Amp is kept constant, it is possible to suppress fluctuations in the characteristics of the amplifier Amp due to fluctuations in the input common mode voltage.

  Thereby, also in the second embodiment, the AC component of the input signal VIN can be A / D converted with high accuracy.

(Embodiment 3)
FIG. 9 is a circuit diagram showing a configuration of a first-order delta-sigma modulation circuit according to Embodiment 3 of the present invention.

  In the third embodiment, with respect to the first-order delta-sigma modulation circuit having the fully differential configuration shown in the second embodiment, the input gain is set to 2 by alternately switching the differential input during sampling and charge transfer. The first-order delta-sigma modulation circuit 1 that can increase the gain without increasing the sampling capacity size by performing double sampling to be doubled will be described.

In this case, as shown in FIG. 9, the primary delta-sigma modulation circuit 1 includes an A / D converter 2, a data latch circuit 3, feedback D / A converters 4a and 4b, a switched capacitor circuit clock generation source 5, and a decoder. and a circuit 6, and charge the D / A converter _71.

Charge the D / A converter _71, an electrostatic capacitance element Csdp0~Csdp2 ⁿ -1 as a sampling capacitor and a sampling capacitor portion 7a consisting Csdn0~Csdn2 ⁿ -1, the switch S1T-0~S1T-2 ⁿ -1 , S1B-0 to S1B-2 ⁿ -1, and a DC component removal D / A converter 7b.

Switch S1T-0~S1T-2 ⁿ -1, the one connection of S1B-0~S1B-2 ⁿ -1 has a first to third connection portions. Switch S1T-0~S1T-2 ⁿ -1, the first connecting portion of S1B-0~S1B-2 ⁿ -1, is connected to a high voltage reference voltage VT1 is supplied.

Switch S1T-0~S1T-2 ⁿ -1, the second connecting portion of S1B-0~S1B-2 ⁿ -1, the input voltage VIN which is output from a sensor is connected to the input . Switch S1T-0~S1T-2 ⁿ -1, the third connection portion S1B-0~S1B-2 ⁿ -1, is connected to a low voltage reference voltage VB1 is supplied.

Switch S1T-0~S1T-2 ⁿ -1, to the other connecting part of S1B-0~S1B-2 ⁿ -1, the capacitance element Csdp0~Csdp2 ⁿ -1, one of Csdn0~Csdn2 ⁿ -1 Each connection is connected.

One connection portion of the capacitance element Cfd0 and one connection of the switches S2T and S3T are connected to the other connection portion of the capacitance elements Csdp0 to Csdp2 ⁿ -1. One connection portion of the capacitance element Cfd1 and one connection of the switches S2B and S3B are connected to the other connection portion of the capacitance elements Csdn0 to Csdn2 ⁿ -1.

  Other connection configurations are the same as those in FIG. 8 of the second embodiment, and a description thereof will be omitted.

In this case, the clock signal .phi.1, samples the input by capacitance device Csdp0~Csdp2 ⁿ -1, the capacitive element Csdn0~Csdn2 ⁿ -1, the digital code of the DC component removing D / A converter 7b The corresponding charge is charged.

Next, in the clock signal φ2 at the time of charge transfer to the capacitive element Cs0 and the capacitive element Cs1 which are integral capacitors, the DC component removal D / A converter 7b is converted into the capacitive elements Csdp0 to Csdp2 ⁿ −1. The switches S1T-0 to S1T-2 ⁿ -1 are selected according to the digital code of the input signal, and the input signal VIN is input to the capacitance elements Csdn0 to Csdn2 ⁿ -1. Thereby, at the time of integration, twice the amount of charge as the difference between the digital code of the input signal VIN and the DC component removal D / A converter 7b is transferred to the integration capacitor, and the input signal VIN is doubled. appear.

  Thereby, since the quantization noise of the delta-sigma modulation circuit can be relatively reduced, the AC component of the input signal VIN can be A / D converted with high accuracy also in the third embodiment.

(Embodiment 4)
FIG. 10 is a circuit diagram showing a configuration of a first-order delta-sigma modulation circuit according to Embodiment 4 of the present invention.

In the first embodiment, the capacitance element serving as the sampling capacitor is connected to 2 ⁿ resolution n-bits of the DC component removal D / A converter 7b. For example, as shown in FIG. to, be configured to take a charge D / a converter 7 ₂ a of the charge D / a converter 7 ₂ upper p-bit, the segment type of charge D / a converter 7 ₂ b of the lower q-bit Is also possible.

In this case, charge the D / A converter 7 ₂ a includes a sampling capacitor portion 7a ₁ consisting of capacitive elements Csdu0~Csdu2 ⁿ -1 as a sampling capacitor, a switch S1a-0~S1a-2 ⁿ -1 And a DC component removal D / A converter 7b ₁ .

The charge D / A converter unit 7 ₂ b includes a sampling capacitor portion 7a ₂ consisting of capacitive elements Csdb0~Csdb2 ⁿ -1 as a sampling capacitor, a switch S1b-0~S1b-2 ⁿ -1 DC and a component removing D / A converter 7b ₂ Prefecture.

The connection configuration of these charge D / A converters 7 ₂ a and 7 ₂ b is the same as that in FIG. 1 of the first embodiment. The other connection configurations are the same as in FIG.

With such a configuration, it is possible to reduce the number of units constituting cells in the charge D / A converter 7 ₂ (2 ^p +2 ^q).

For example, the 10bit, if you create simple but requires a number of constituent cells in 1023, in the configuration shown in FIG. 10, upper 6bit charge the D / A converter _71, the charge D / A converter 7 ₂ In the case of the lower 4 bits, the number of cells is 63 + 16 = 79, which can be significantly reduced.

  Accordingly, in the fourth embodiment, the AC component of the input signal VIN can be A / D converted with high accuracy while the layout area of the first-order delta-sigma modulation circuit 1 is significantly reduced.

(Embodiment 5)
FIG. 11 is a circuit diagram showing a configuration of a first-order delta-sigma modulation circuit according to the fifth embodiment of the present invention.

Wherein the primary delta-sigma modulation circuit shown in Figure 1 1 of the first embodiment, at the timing of the clock signal .phi.2, the switch S1-0~S1-2 ⁿ -1 of the DC component removing D / A converter 7b is switched However, for example, it is also possible to remove the DC component by sampling the signal with the DC component removed at the time of the clock signal φ1 and performing charge transfer with the clock signal φ2. It is.

In this case, as shown in FIG. 11, the first-order delta-sigma modulation circuit 1 has a configuration in which switches S0 and S1 are newly added to the configuration of FIG. One connection portion of the switch S1 is connected so that the input signal VIN is inputted, and the other connection portion of the switch S1 is connected to one connection portion of the switch S0 and the capacitance elements Csd0 to Csd0. One connection portion of Csd2 ⁿ −1 is connected to each other.

In addition, the other connection portion of the capacitive element Csd0~Csd2 ⁿ -1, one connection of the switch S2-0～S2-2 ⁿ are connected. The first connecting part of the switch S2-0~S2-2 ⁿ -1, is connected to a high voltage reference voltage VT1 is supplied.

The second connecting part of the switch S2-0~S2-2 ⁿ -1, the amplifier Amp minus (-) side input part is connected, switch S2-0~S2-2 ⁿ -1 The third connection portion is connected to be supplied with the low voltage reference voltage VB1. Other connection configurations are the same as those in FIG.

  Assuming that the DC removal voltage is the same as that in Equation 5, the charge amount when sampling the clock signal φ1 is as follows.

  Therefore, summing up Equation 8, the amount of charge transferred is as follows.

  Therefore, the output voltage of the integrator by the input is as follows.

  From this, it is clear that Equation 6 obtained from FIG. 1 and Equation 10 obtainable from FIG. 11 are the same, and the same effect can be obtained.

  Thereby, also in the fourth embodiment, the AC component of the input signal VIN can be A / D converted with high accuracy.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to fourth embodiments, the first-order delta-sigma modulation has been described. However, the present invention relates to a second-order 1-bit type, a third-order or higher-order delta-sigma modulation circuit, a multi-bit delta-sigma modulation circuit, The present invention can be applied to various delta-sigma modulation circuits such as a cascade type delta-sigma modulation circuit.

  The present invention is suitable for a highly accurate A / D conversion technique using first-order delta-sigma modulation in an A / D converter.

It is explanatory drawing which shows the structure of the 1st-order delta-sigma modulation circuit by Embodiment 1 of this invention. FIG. 2 is a block diagram illustrating an example of an A / D converter configured using the first-order delta-sigma modulation circuit of FIG. 1. 3 is a timing chart of a clock signal generated by a switched capacitor circuit clock generation source provided in the first-order delta-sigma modulation circuit of FIG. 1. FIG. 3 is an explanatory diagram showing a decoder result for a decoder circuit provided in the first-order delta-sigma modulation circuit of FIG. 1 to realize a DC removal voltage Vof. FIG. 2 is an explanatory diagram when the first-order delta-sigma modulation circuit 1 of FIG. 1 is applied to a 4-bit weighted DC component removal D / A converter. FIG. 6 is an explanatory diagram when the primary delta-sigma modulation circuit of FIG. 1 following FIG. 5 is applied to a 4-bit weighted DC component removal D / A converter. FIG. 2 is a block diagram illustrating an example of a semiconductor integrated circuit device configured using the first-order delta-sigma modulation circuit of FIG. 1. It is a circuit diagram which shows the structure of the 1st-order delta-sigma modulation circuit by Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the 1st-order delta-sigma modulation circuit by Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the primary delta-sigma modulation circuit by Embodiment 4 of this invention. It is a circuit diagram which shows the structure of the primary delta-sigma modulation circuit by Embodiment 5 of this invention. It is explanatory drawing explaining the DC component and DC component of an input signal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st-order delta-sigma modulation circuit 2 A / D conversion part 2a Integrator amplifier circuit 2a ₁ Integrator amplifier circuit 2b Comparator 3 Data latch circuit 4 Feedback D / A converter 4a, 4b Feedback D / A converter 5 Switched capacitor Circuit clock generation source 6 Decoder circuit 7 Charge D / A converter 7 ₁ Charge D / A converter 7 ₂ Charge D / A converter 7 ₂ a Charge D / A converter 7 ₂ b Charge D / A converter 7 a Sampling Capacitor 7a ₁ Sampling capacitor 7a ₂ Sampling capacitor 7b DC component removal D / A converter 7b ₁ DC component removal D / A converter 7b ₂ DC component removal D / A converter 7 ₂ b Charge D / A converter 8 Semiconductor integrated circuit device 9 Analog input channel 10 Digital filter circuit 11 Register 12 Control circuit 13 CPU
14 Memory 15 Digital code storage unit 16 Bus Csd0 to Csd2 ⁿ −1 Capacitance element Cs0 Capacitance element Cfd0 Capacitance element Csdp0 to Csdp2 ⁿ −1, Csdn0 to Csdn2 ⁿ −1 Capacitance element Csdu0 to Csdu2 ⁿ -1 Capacitance elements Csdb0 to Csdb2 ⁿ -1 Capacitance elements S1-0 to S1-2 ⁿ -1 Switches S0 to S4 Switches S1T, S2T, S2B, S3T, S3B Switches S4T, S4B Switches S1T-0 to S1T -2 ⁿ -1, S1B-0 to S1B-2 ⁿ -1 switch S1a-0 to S1a-2 ⁿ -1 switch S1b-0 to S1b-2 ⁿ -1 switch Amp amplifier ADC A / D converter

Claims (6)

A semiconductor integrated circuit device having a delta-sigma A / D converter,
The delta-sigma A / D converter is
A semiconductor integrated circuit device comprising a D / A converter for removing a DC component of an input signal. The semiconductor integrated circuit device according to claim 1.
The D / A converter is
A sampling capacitor that samples the input voltage and transfers charge to the integrating capacitor;
A semiconductor integrated circuit device comprising: a switching unit connected to the sampling capacitor, switching to an arbitrary reference voltage, and adjusting a charge transfer amount to the integration capacitor. The semiconductor integrated circuit device according to claim 2.
The delta-sigma A / D converter is
A semiconductor integrated circuit device comprising an integrator including the D / A converter, a feedback D / A converter having a feedback capacitor, and an integrating amplifier. The semiconductor integrated circuit device according to claim 3.
A semiconductor characterized by amplifying an input signal by changing a capacitance ratio between the sampling capacitor and the feedback capacitor, thereby amplifying an input signal and relatively reducing a delta-sigma modulator quantization noise. Integrated circuit device. The semiconductor integrated circuit device according to any one of claims 1 to 4,
The delta-sigma A / D converter is
It has multiple input channels to which input voltage is input,
The integrator is
A semiconductor integrated circuit device connected to a plurality of the input channels in common. In the semiconductor integrated circuit device according to claim 1,
The delta-sigma A / D converter is
A semiconductor integrated circuit device, characterized in that it is of a double sampling type in which the input gain is doubled by alternately repeating differential inputs during sampling and charge transfer.

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