JP2008021782A5 - - Google Patents

Description

Nonvolatile semiconductor memory and driving method thereof

  The present invention relates to a nonvolatile semiconductor memory and a driving method thereof.

An island-shaped semiconductor on the side wall of the island-shaped semiconductor layer formed on the surface of the semiconductor substrate, which can secure a sufficiently large capacitance between the charge storage layer and the gate with a small substrate occupation area and has excellent writing and erasing efficiency A flash memory composed of a memory transistor having a charge storage layer and a gate formed so as to surround the layer has been proposed (see, for example, Patent Document 1 and Non-Patent Document 1).

In the flash memory, charges are injected into the charge storage layer using hot electrons. The difference in threshold voltage due to the difference in charge storage state of the charge storage layer is stored as data “0” and “1”. For example, in the case of an N-channel memory transistor using a floating gate as a charge storage layer, in order to inject charge into the floating gate, a high voltage is applied to the gate and drain diffusion layers, and the source diffusion layer and the semiconductor substrate are grounded. To do. At this time, the energy of the electrons of the semiconductor substrate is increased by the voltage between the source and the drain, and the energy barrier of the tunnel oxide film is overcome and injected into the electric storage layer. By this charge injection, the threshold voltage of the memory transistor moves in the positive direction. Of the current flowing between the source and drain, the ratio injected into the charge storage layer is small. Therefore, the current required for writing is on the order of 100 μA per cell. In the NOR flash memory, the current that flows during reading is about 30 μA.

The flash memory cell array composed of memory transistors using the side walls of the island-like semiconductor layer uses a diffusion layer on the source line or source surface. The diffusion layer has a higher resistance than metal. When a current flows through the resistor, a potential difference is generated. Therefore, the voltage of the source diffusion layer of the memory transistor at the time of writing becomes higher than 0 V, the voltage between the source and the drain decreases, the current flowing between the source and the drain decreases, and the writing speed decreases. In reading, the voltage of the source diffusion layer of the memory transistor is higher than 0 V, the voltage between the source and the drain is decreased, the current flowing between the source and the drain is decreased, and the reading speed is decreased.

Japanese Unexamined Patent Publication No. Hei 8-48587 Howard Pein et al. IEEE Electron Device Letters, Vol.14, No.8, pp.415-417, 1993

Accordingly, it is an object of the present invention to provide a non-volatile semiconductor memory including a memory transistor using a sidewall of an island-shaped semiconductor layer that avoids a decrease in writing speed and reading speed.

In order to solve the above problems, the present invention has the following configuration. According to one aspect of the present invention, a source region, a channel region, and a drain region are formed in this order from the substrate side, and further, a charge storage layer formed outside the channel region via a gate insulating film, A non-volatile semiconductor memory in which a memory transistor having a gate formed so as to cover the charge storage layer through an insulating layer outside the charge storage layer is arranged in a matrix of n rows and m columns on the substrate There,
A plurality of primary source lines wired in the column direction to interconnect the source regions of the memory transistors aligned in the column direction of the matrix;
A plurality of parallel bit lines wired in the column direction in a layer different from the primary source line to connect the drain regions of the memory transistors aligned in the column direction to each other;
A line wired in the row direction to connect the gates of the memory transistors aligned in the row direction substantially perpendicular to the column direction is a gate line,
A p row (p <n) secondary source lines wired line by line every of the matrix, and the secondary source lines formed of metal for connecting the primary source line to each other,
A non-volatile semiconductor memory is provided.

According to still another feature of the present invention, a source region, a channel region, and a drain region are formed in this order from the substrate side, and further, a charge storage layer formed outside the channel region via a gate insulating film; A non-volatile semiconductor in which memory transistors having gates formed so as to cover the charge storage layer through an insulating layer outside the charge storage layer are arranged in a matrix of n rows and m columns on the substrate Memory,
A first common diffusion source line wired to interconnect the source regions of the memory transistors respectively aligned in the row and column directions of the matrix;
A plurality of parallel bit lines wired in the column direction in a layer different from the first common diffusion source line to connect the drain regions of the memory transistors aligned in the column direction to each other;
A line wired in the row direction to connect the gates of the memory transistors aligned in the row direction substantially perpendicular to the column direction is a gate line,
A second a primary source line, second-order source lines wired one row every row p (p <n) of the matrix formed of metal connected to the source surface,
A non-volatile semiconductor memory is provided.

According to the feature of the method for driving a nonvolatile semiconductor memory according to the present invention, there is provided a method for writing to a nonvolatile semiconductor memory,
0V or positive first voltage is applied to the selected bit line, 0V is applied to the unselected bit line , a positive second voltage is applied to the selected gate line, and 0V is applied to the unselected gate line Then, by applying 0 V to the primary source line or the first common diffusion source line and the secondary source line , the selected memory transistor is injected with charge into the charge storage layer using hot electrons. A method of writing to a nonvolatile semiconductor memory is provided.

According to another feature of the method for driving a nonvolatile semiconductor memory according to the present invention, there is provided a method for reading from a nonvolatile semiconductor memory,
A positive first voltage is applied to the selected gate lines, the gate lines of the unselected applied to 0V, 0V is applied to the first primary source line or the first common diffusion source line and the secondary source line by applying a positive second voltage to the selected bit line, read the memory transitional scan data selected, method of reading from a nonvolatile semiconductor memory is provided.

According to still another feature of the method for driving a nonvolatile semiconductor memory according to the present invention, there is provided a method for erasing a nonvolatile semiconductor memory,
By applying a positive first voltage to the bit line and the primary source line or the first common diffusion source line and the secondary source line and applying 0 V to the gate line , a FN (Fowler-Nordheim) tunnel current A method for erasing a non-volatile semiconductor memory is provided, in which charges are released from the charge storage layers of all memory transistors .

According to still another feature of the method for driving a nonvolatile semiconductor memory according to the present invention, there is provided a method for erasing a nonvolatile semiconductor memory,
A positive first voltage is applied to the bit line and the primary source line or the first common diffusion source line and the secondary source line , 0 V is applied to the selected gate line, and a positive voltage is applied to the non-selected gate line . By applying the second voltage, there is provided a method for erasing a nonvolatile semiconductor memory, in which charges are discharged from the charge storage layer of the memory transistor connected to the selected gate line using the FN tunnel current.

According to the present invention, since a predetermined number of gate lines have a secondary source line formed using metal, the resistance of the source line can be reduced, and the source diffusion layer of the memory transistor can be formed at the time of writing. 0V can be applied, a sufficient voltage can be applied between the source and the drain, a sufficient current can flow between the source and the drain, and a decrease in writing speed can be avoided. Also, at the time of reading, 0 V can be applied to the source diffusion layer of the memory transistor , a sufficient voltage can be applied between the source and the drain, and a sufficient current can be passed between the source and the drain. A decrease in speed can be avoided.

The nonvolatile semiconductor memory according to the present invention includes a number of island-like semiconductor layers formed on a semiconductor substrate. The island-like semiconductor layer includes a drain diffusion layer formed thereon, a source diffusion layer formed thereunder, and a channel region on a sidewall sandwiched between the drain diffusion layer and the source diffusion layer via a gate insulating film. And a non-volatile semiconductor memory transistor having a gate formed on the charge storage layer. The nonvolatile semiconductor memory has the nonvolatile semiconductor memory transistors arranged in a matrix, the bit lines connected to the drain diffusion layer are wired in the column direction, the gate lines are wired in the row direction, and the source diffusion layer the connected primary source line has a structure that the wiring in the column direction, one for each gate line of a predetermined number (e.g. 64), route the secondary source lines formed of metal in the row direction At this time, the secondary source line may be connected to the primary source line .

Further, in the nonvolatile semiconductor memory, the nonvolatile semiconductor memory transistors are arranged in a matrix on the first common diffusion source line formed of the diffusion layer, and the bit line connected to the drain diffusion layer is arranged in the column direction. It is also possible to have a structure in which the gate lines are wired in the row direction. Furthermore, in this nonvolatile semiconductor memory, one for each gate line of a predetermined number (e.g. 64), route the secondary source lines formed of metal in the row direction, this time, the secondary source It may have a structure that connects the lines to the first common diffusion source line.

In the driving method of the present invention, 0V or a positive first voltage is applied to a selected bit line, 0V is applied to a non-selected bit line , a positive second voltage is applied to a selected gate line , and non-selected By applying 0V to the first gate line and applying 0V to the primary source line or the first common diffusion source line and the secondary source line , the selected memory transistor is charged using hot electrons. Charge can be injected into the layer.

The driving method of the present invention, the positive first voltage is applied to the selected gate lines, the gate lines of the unselected applies a 0V, second-order and first-order source line or the first common diffusion source line By applying 0V to the source line and applying a positive second voltage to the selected bit line, the selected memory transistor can be read.

According to the driving method of the present invention, a positive first voltage is applied to the bit line and the primary source line or the first common diffusion source line and the secondary source line , and 0 V is applied to the gate line. A tunnel current can be used to release charges from the charge storage layers of all memory transistors .

According to the driving method of the present invention, a positive first voltage is applied to the bit line and the primary source line or the first common diffusion source line and the secondary source line , and 0 V is applied to the selected gate line. by applying a positive second voltage to the gate line of the selected, it is possible to release charge from the charge accumulation layer of the connected memory transistors to a gate line selected by utilizing the FN tunneling current.

  Hereinafter, the present invention will be described based on embodiments shown in the drawings. The present invention is not limited to this.

The layout and cross-sectional structure of the nonvolatile semiconductor memory according to the present invention are shown in FIGS. 1, 2, 3, and 4, respectively. In this embodiment, a primary source line 2 and a source diffusion layer 3 are formed on a silicon oxide film 1, an island-like semiconductor layer 4 is formed thereon, and a drain diffusion is formed above the island-like semiconductor layer 4. layer 5 is formed, the charge storage layer 6 formed through a gate insulating film is formed on the drain diffusion layer 5 and the source diffusion layer 3 sandwiched by the side wall of the channel region, a gate on the charge storage layer 6 Formed to form a memory transistor . A line wired in the row direction so as to connect the gates of the memory transistors to each other is referred to as a gate line 7. A bit line 8 is formed on the drain diffusion layer. Moreover, every predetermined number of gate lines (here, every 64 lines) to, on the first primary source line, second-order source lines 9 formed of metal that assigned to rows are formed.

Further, the layout and cross-sectional structure of the nonvolatile semiconductor memory according to the present invention are shown in FIGS. 5, 6, 7, and 8, respectively. In this embodiment, a first common diffusion source line 10 and a source diffusion layer 3 are formed on a silicon oxide film 1, and an island-like semiconductor layer 4 is formed on the first common diffusion source line 10 and a source diffusion layer 3. A drain diffusion layer 5 is formed, and a charge storage layer 6 formed via a gate insulating film is formed on the channel region on the side wall sandwiched between the drain diffusion layer 5 and the source diffusion layer 3, and the charge storage layer 6 is formed on the charge storage layer 6. A gate is formed to form a memory transistor . A line wired in the row direction so as to connect the gates of the memory transistors to each other is referred to as a gate line 7. A bit line 8 is formed on the drain diffusion layer. Further, a secondary source line 9 made of metal assigned to a row is formed on the first common diffusion source line for every predetermined number of gate lines (here, every 64 lines).

An example of a manufacturing process for forming the structure of the memory transistor array included in the nonvolatile semiconductor memory according to the present invention will be described below with reference to FIGS. FIG. 9 is a cross-sectional view of the SOI substrate on which the P-type silicon 100 is formed on the silicon oxide film 1, taken along the line X ₁ -X ′ ₁ . 10 is a Y ₁ -Y ′ ₁ cross-sectional view, and FIG. 11 is a Y ₂ -Y ′ ₂ cross-sectional view. The X ₁ -X ′ ₁ cross section corresponds to FIG. 2, the Y ₁ -Y ′ ₁ cross section corresponds to FIG. 3, and the Y ₂ -Y ′ ₂ cross section corresponds to FIG.

Using the resist as a mask, the P-type silicon 100 is etched by reactive ion etching to form the primary source line 2 (FIG. 12 (X ₁ -X ′ ₁ ), FIG. 13 (Y ₁ -Y ′ ₁ )). FIG. 14 (Y ₂ -Y ′ ₂ )).

An oxide film is deposited, planarized by CMP, and etched back using reactive ion etching (FIG. 15 (X ₁ -X ′ ₁ ), FIG. 16 (Y ₁ -Y ′ ₁ ), FIG. 17 ( Y ₂ -Y _'2)).

Using the resist as a mask, the P-type silicon 100 is etched by reactive ion etching to form the island-shaped semiconductor layer 101 (FIG. 18 (X ₁ -X ′ ₁ ), FIG. 19 (Y ₁ -Y ′ ₁ ), FIG. 20 (Y ₂ -Y ′ ₂ )). The lower part of the island-like semiconductor layer 101 becomes a primary source line .

Subsequently, oxidation is performed to form a tunnel insulating film 102 (FIG. 21 (X ₁ -X ′ ₁ ), FIG. 22 (Y ₁ -Y ′ ₁ ), FIG. 23 (Y ₂ -Y ′ ₂ )).

Subsequently, a polycrystalline silicon film 103 is deposited (FIG. 24 (X ₁ -X ′ ₁ ), FIG. 25 (Y ₁ -Y ′ ₁ ), FIG. 26 (Y ₂ -Y ′ ₂ )).

Subsequently, the polycrystalline silicon film is etched by reactive ion etching, and left as a sidewall spacer on the island-like semiconductor sidewall to form a charge storage layer 6 (FIG. 27 (X ₁ -X ′ ₁ )) FIG. 28 (Y ₁ -Y ′ ₁ ) and FIG. 29 (Y ₂ -Y ′ ₂ )).

Subsequently, oxidation is performed to form an interpoly insulating film 104 (FIG. 30 (X ₁ -X ′ ₁ ), FIG. 31 (Y ₁ -Y ′ ₁ ), FIG. 32 (Y ₂ -Y ′ ₂ )). An insulating film may be deposited by CVD.

Subsequently, a polycrystalline silicon film 105 is deposited (FIG. 33 (X ₁ -X ′ ₁ ), FIG. 34 (Y ₁ -Y ′ ₁ ), FIG. 35 (Y ₂ -Y ′ ₂ )).

Subsequently, the polycrystalline silicon film is planarized by CMP and then etched back (FIG. 36 (X ₁ -X ′ ₁ ), FIG. 37 (Y ₁ -Y ′ ₁ ), FIG. 38 (Y ₂ -Y ′ ₂ ). )).

Subsequently, a resist 106 patterned by a known photolithography technique is formed (FIG. 39 (X ₁ -X ′ ₁ ), FIG. 40 (Y ₁ -Y ′ ₁ ), FIG. 41 (Y ₂ -Y ′ ₂ )). ).

Subsequently, using the resist as a mask, the polycrystalline silicon film 105 is etched by reactive ion etching to remain in the shape of a sidewall spacer on the side wall of the charge storage layer, thereby forming the gate line 7 (FIG. 42 (X ₁ − X ′ ₁ ), FIG. 43 (Y ₁ -Y ′ ₁ ), FIG. 44 (Y ₂ -Y ′ ₂ )).

Subsequently, the primary source line 2, the source diffusion layer 3, and the drain diffusion layer 5 are formed by ion implantation or the like (FIG. 45 (X ₁ -X ′ ₁ ), FIG. 46 (Y ₁ -Y ′ ₁ )), FIG. 47 (Y ₂ -Y ′ ₂ )).

Subsequently, an interlayer insulating film 107 such as a silicon oxide film is deposited and planarized using CMP or the like, and then the interlayer insulating film is etched by reactive ion etching using a resist as a mask (FIG. 48 (X _1- X ′ ₁ ), FIG. 49 (Y ₁ -Y ′ ₁ ), FIG. 50 (Y ₂ -Y ′ ₂ )).

Subsequently, a metal 108 is deposited by sputtering or the like (FIG. 51 (X ₁ -X ′ ₁ ), FIG. 52 (Y ₁ -Y ′ ₁ ), FIG. 53 (Y ₂ -Y ′ ₂ )).

Subsequently, the metal is etched by reactive ion etching to form the secondary source line 9 (FIG. 54 (X ₁ -X ′ ₁ ), FIG. 55 (Y ₁ -Y ′ ₁ ), FIG. 56 (Y ₂ -Y ' ₂ )).

Subsequently, an interlayer insulating film 109 is deposited (FIG. 57 (X ₁ -X ′ ₁ ), FIG. 58 (Y ₁ -Y ′ ₁ ), FIG. 59 (Y ₂ -Y ′ ₂ )).

Subsequently, the drain diffusion layer is exposed using CMP or the like (FIG. 60 (X ₁ -X ′ ₁ ), FIG. 61 (Y ₁ -Y ′ ₁ ), FIG. 62 (Y ₂ -Y ′ ₂ )).

Subsequently, metal is deposited by sputtering or the like, and the metal is etched using a resist as a mask to form the bit line 8 (FIG. 63 (X ₁ -X ′ ₁ ), FIG. 64 (Y ₁ -Y ′ ₁ )). FIG. 65 (Y ₂ -Y ′ ₂ )).

Hereinafter, a method of driving the nonvolatile semiconductor memory transistor array of the present invention will be described with reference to FIGS.

The operation of injecting (writing) charges into the charge storage layer of the selected memory transistor M1 by hot electrons is performed as shown in FIG. Apply 0V or a voltage that generates hot electrons (5V) to the selected bit line 200, apply 0V to the unselected bit line 201, and apply a high voltage (9V) to the selected gate line 202 Then, 0V is applied to the unselected gate line 203, and 0V is applied to the primary source line 204 and the secondary source line 205. With the above operation, charges can be injected into the charge storage layer using hot electrons.

The data read operation of the selected memory transistor M1 is performed as shown in FIG. Applying a voltage (3V) to the gate line 202 selected, 0V is applied to the gate line 203 non-selected, the primary source line 204 to 0V is applied to the second-order source line 205, the selected bit line 200 The selected memory transistor can be read by applying a voltage (0.5V) to.

The operation of discharging (erasing) the charges from the charge storage layers of all the memory transistors in the memory transistor array by the FN tunnel current is performed as shown in FIG. Applying erase voltage (18V) to all bit lines, all primary source lines, and secondary source lines , and applying 0V to all gate lines , the charge storage of all memory transistors using FN tunnel current Charge can be released from the layer.

The operation of discharging (erasing) charges from the charge storage layer of the memory transistor connected to the selected gate line of the memory transistor array by the FN tunnel current is performed as shown in FIG. An erase voltage (18V) is applied to all bit lines, the primary source line, and the secondary source line , 0V is applied to the selected gate line 202, and an unselected gate line 203 can be prevented from being erased. By applying (9V), charges can be discharged from the charge storage layer of the memory transistor connected to the selected gate line using the FN tunnel current.

Further, in the embodiment, a memory having a structure of a single charge storage layer surrounding the island-shaped semiconductor via a gate insulating film on a channel region on a side wall sandwiched between the drain diffusion layer and the source diffusion layer of the island-shaped semiconductor layer. Although a transistor is used, the charge storage layer does not necessarily have to be a single charge storage layer. As shown in FIG. 70, one or more charge storage layers are formed on a part of the channel region of the island-shaped semiconductor sidewall. The layer 300 may surround it. In addition, one or a plurality of particulate charge storage layers 301 or a non-volatile semiconductor memory transistor having a structure capable of writing using hot electrons having a charge storage region between the gate and the island-shaped semiconductor layer ( 71) may be used (FIG. 72).

As described above, according to the present invention, since the secondary source line formed using metal is provided for each predetermined number of gate lines , the resistance of the source line can be reduced, and the memory transistor can be used during writing. 0V can be applied to the source diffusion layer, sufficient voltage can be applied between the source and drain, sufficient current can flow between the source and drain, and a decrease in writing speed can be avoided. . Also, at the time of reading, 0 V can be applied to the source diffusion layer of the memory transistor , a sufficient voltage can be applied between the source and the drain, and a sufficient current can be passed between the source and the drain. A decrease in speed can be avoided.

1 is a layout of a nonvolatile semiconductor memory according to the present invention. FIG. 2 is a cross-sectional view corresponding to the X ₁ -X ′ ₁ cross-sectional view in FIG. 1 of the nonvolatile semiconductor memory according to the present invention. FIG. 2 is a cross-sectional view corresponding to the Y ₁ -Y ′ ₁ cross-sectional view in FIG. 1 of the nonvolatile semiconductor memory according to the present invention. FIG. _{2 is a} cross-sectional view corresponding to the Y ₂ -Y ′ ₂ cross-sectional view in FIG. 1 of the nonvolatile semiconductor memory according to the present invention. 1 is a layout of a nonvolatile semiconductor memory according to the present invention. FIG. 2 is a cross-sectional view corresponding to the X ₁ -X ′ ₁ cross-sectional view in FIG. 1 of the nonvolatile semiconductor memory according to the present invention. FIG. 2 is a cross-sectional view corresponding to the Y ₁ -Y ′ ₁ cross-sectional view in FIG. 1 of the nonvolatile semiconductor memory according to the present invention. FIG. _{2 is a} cross-sectional view corresponding to the Y ₂ -Y ′ ₂ cross-sectional view in FIG. 1 of the nonvolatile semiconductor memory according to the present invention. FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. ₁₀ is an X ₁ -X ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention. FIG. ₁₀ is a Y ₁ -Y ′ ₁ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; FIG. 10 is a Y ₂ -Y ′ ₂ cross-sectional process drawing showing the manufacture example of the memory transistor array according to the present invention; It is a figure which shows the electric potential relationship at the time of data writing. It is a figure which shows the electric potential relationship at the time of data reading. It is a figure which shows the electric potential relationship at the time of erasing all the memory transistors . It is a figure which shows the electric potential relationship at the time of memory transistor erasure | elimination connected to the selected gate line . It is a bird's-eye view which shows the other Example which concerns on this invention. It is a bird's-eye view which shows the other Example which concerns on this invention. It is sectional drawing which shows the other Example which concerns on this invention.

1 silicon oxide film 2 primary source line ( 1st SL)
3 Source diffusion layer 4 Island-like semiconductor layer 5 Drain diffusion layer 6 Charge storage layer 7 Gate line (WL)
8 Bit line 9 Secondary source line (2ndSL)
10 first common diffusion source line 100 P-type silicon 101 island-like semiconductor layer 102 tunnel insulating film 103 polycrystalline silicon film 104 interpoly insulating film 105 polycrystalline silicon film 106 resist 107 interlayer insulating film 108 metal 109 interlayer insulating film 200 Selected bit line 201 Unselected bit line 202 Selected gate line 203 Unselected gate line 204 Primary source line 205 Secondary source line 300 Charge storage layer 301 Particulate charge storage layer

Claims (8)

  A memory transistor selection line is arranged for each row connected to the gates of the memory transistors arranged in the row direction, and a primary source line is arranged for each column connected to the sources of the memory transistors arranged in the column direction, A non-volatile memory, wherein a secondary source line arranged in a row direction connected to a plurality of primary source lines is a metal.   A memory in which a source region, a channel region, and a drain region are formed in this order from the substrate side, and nonvolatile memory transistors having a charge storage layer outside the channel region are arranged in a matrix on the substrate and arranged in a row direction A memory transistor selection line is arranged for each row connected to the gate of the transistor, a primary source line is arranged for each column connected to the source of the memory transistor arranged in the column direction, and a plurality of primary source lines A non-volatile memory, wherein the second source line arranged in the row direction connected to the metal is metal.   A nonvolatile memory in which at least a plurality of the nonvolatile memories according to claim 1 are arranged in a column direction.   A nonvolatile memory in which at least a plurality of the nonvolatile memories according to claim 1 are arranged in a row direction.   A nonvolatile memory in which at least a plurality of the nonvolatile memories according to claim 1 are arranged in a column direction and a row direction.   A nonvolatile memory in which at least a plurality of the nonvolatile memories according to claim 2 are arranged in a column direction.   A nonvolatile memory in which a plurality of the nonvolatile memories according to claim 2 are arranged in the row direction.   A nonvolatile memory in which at least a plurality of the nonvolatile memories according to claim 2 are arranged in a column direction and a row direction.