JP2008017413A - Receiver, transmission system, and reception method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver, a transmission system, and a reception method that achieves clock reproduction with less jitter with a simple circuit configuration even at a high-speed data transmission rate in amplitude-directional multilevel-modulation communication. <P>SOLUTION: The receiver 3 sets 2<SP>n</SP>-1 thresholds in a range between a minimum value and a maximum value of a received signal, obtains 2<SP>n</SP>-1 comparator outputs by respectively comparing each of the set thresholds with the received signal by a comparator, and reproduces a clock when a first threshold close to the minimum value of the received signal is changed from a first level L to a second level H, and when a second threshold close to the maximum value of the received signal is changed from the second level to the first level, so as to latch the 2<SP>n</SP>-1 comparator outputs in synchronization with a clock CLK2 obtained by phase adjusting the reproduced clock. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a transmission device that transmits a multilevel signal such as an optical signal corresponding to the amount of light, a reception device that receives a multilevel signal, a transmission system that transmits and receives a multilevel signal, and a reception method.

In recent years, with the widespread use of digital broadcasting and streaming video distribution, high-speed communication technology is required even in the home, and therefore, technical development related to optical communication is widely performed.
For example, Patent Document 1 below discloses an optical signal data transmission technique that enables high-density transmission by modulating the data signal on the receiving side based on the amplitude of the reference signal added to the data signal on the transmitting side. Is disclosed.

JP 2000-244586 A

By the way, in the technique disclosed in the above-mentioned Patent Document 1, data is reproduced through an analog-digital converter (ADC) on the receiving device side.
For example, it is conceivable to employ a multi-level modulation communication method in the amplitude direction to perform high-speed communication in the GHz band. However, the ADC in the GHz band consumes a large amount of power, and the sampling clock of the ADC approaches the data transmission speed ( At low speed, the sampling clock is sufficiently faster than the data transmission speed, so phase alignment is not necessary), which has the disadvantage of requiring severe phase adjustment.

Further, as shown in FIG. 18, in the GHz band, there is a disadvantage that jitter after clock reproduction becomes large due to the influence of the rising speed and falling speed of the signal.
As shown in FIG. 18A, when the rising speed and falling speed of the signal are sufficiently high, the clock reproduced from the received signal contains almost no jitter.
On the other hand, as shown in FIG. 18B, when the rising speed and falling speed of the signal are slow, the clock reproduced from the received signal has a large jitter.

  The present invention provides a receiving apparatus, a transmission system, and a receiving method capable of realizing a clock reproduction with little jitter with a simple circuit configuration even in a multi-level modulation communication in an amplitude direction even at a high data transmission speed. It is to provide.

A first aspect of the present invention is a receiving apparatus that receives an n-bit multi-level signal that is multi-level modulated in the amplitude direction, and 2 ⁿ −1 signals between the minimum value and the maximum value of the received signal. Of the comparison unit including 2 ⁿ -1 comparators for comparing the threshold value and the received signal, and among the 2 ⁿ -1 comparator outputs of the comparison unit, The timing at which the comparator output based on the first threshold value close to the minimum value of the received signal changes from the first level to the second level, and the comparator output based on the second threshold value close to the maximum value of the received signal is A clock recovery unit that recovers a clock from two timings at a timing of changing from the second level to the first level, and a latch that latches 2 ⁿ -1 comparator outputs of the comparison unit in synchronization with the recovered clock Part.

According to a second aspect of the present invention, there is provided a receiving apparatus for receiving an n-bit signal that is multi-level modulated in the amplitude direction, wherein 2 ⁿ −1 signals are received between the minimum value and the maximum value of the received signal. A threshold value is set, and the comparator includes 2 ⁿ -1 comparators for comparing the threshold value and the received signal, and the smallest of the 2 ⁿ -1 comparator outputs of the comparator. The clock is recovered from two timings: the timing at which the comparison output by the threshold changes from the first level to the second level and the timing at which the comparison output by the largest threshold changes from the second level to the first level. The clock recovery unit, the latch unit that latches the 2 ⁿ -1 comparator outputs of the comparison unit in synchronization with the recovery clock, and the reproduction so that the data input and clock input phases of the latch unit are aligned. Adjust the clock phase And an adjusting unit.

A transmission system according to a third aspect of the present invention includes a transmission device that transmits an n-bit multi-level signal that is multi-level modulated in the amplitude direction to a transmission line, and an n-bit multi-level signal that is multi-level modulated in the amplitude direction. 2 ⁿ -1 threshold values are set between the minimum value and the maximum value of the received signal, and the receiving device receives the threshold value and the received signal. a comparison unit comprising 2 ⁿ -1 one comparator for comparing, among the 2 ⁿ -1 one comparator output of the comparator unit, the comparison output by the smallest threshold the second level from the first level A clock regeneration unit that regenerates a clock from two timings, i.e., a timing at which the comparison output by the largest threshold value changes from the second level to the first level, and la the 2 ⁿ -1 one comparator output of the comparator unit Comprising a latch portion for switch, a phase adjustment unit for the phase adjustment of the reproduced clock as a data input and a clock input of the phase of the latch portion are aligned, a.

A fourth aspect of the present invention is a reception method for receiving an n-bit multilevel signal that is multilevel modulated in the amplitude direction, and 2 ⁿ −1 signals between the minimum value and the maximum value of the received signal. One of the step of setting the threshold value, the step of comparing the set threshold value and the received signal to obtain 2 ⁿ -1 comparison outputs, and the 2 ⁿ -1 comparison output Clock from two timings, the timing at which the comparison output by the smallest threshold changes from the first level to the second level and the timing at which the comparison output by the largest threshold changes from the second level to the first level a step of reproducing the steps and, the phase adjustment of the reproduced clock as a data input and a clock input of the phase when the latch is aligned to latching synchronization with 2 ⁿ -1 pieces of comparison output to the reproduction clock And a step that.

  According to the present invention, in multilevel modulation communication in the amplitude direction, clock reproduction with less jitter can be realized with a simple circuit configuration even at a high data transmission rate of GHz or higher.

Hereinafter, an embodiment of a transmission system of the present invention will be described with reference to the accompanying drawings.
In the present embodiment, an optical transmission system using an optical multilevel signal will be described as an example. The present invention is not limited to optical communication, but includes telecommunications.

  FIG. 1 is a diagram illustrating a configuration example of an optical transmission system 1 according to an embodiment of the present invention.

An optical transmission system 1 according to the present embodiment includes a transmission device 2 that transmits data, a reception device 3 that receives data, a data processing device 4 that generates data to be transmitted, and an optical transmission path 5.
The optical transmission system 1 performs signal transmission and reception processing of n bits (for example, eight values in the case of n = 3) that are multi-level modulated in the amplitude direction. Note that n is an integer of 2 or more.

The data processing device 4 generates desired digital data such as a computer device or an image generation device.
In FIG. 1, the data processing device 4 generates serial data DATA as digital data, for example, and transmits it to the transmission device 2. In the transmission system 1 of the present embodiment, it is assumed that serial data DATA is transmitted to the transmission device 2 in, for example, a MAC (Media Access Control) frame format.
In addition, the data processing device 4 supplies the transmission device 2 with a clock signal CLK that serves as a reference for operation.

For example, the transmission device 2 processes the data of the MAC frame transmitted from the data processing device 4 in units of n bits (2 bits, 3 bits, 4 bits, or 8 bits) in order from the LSB. Then, the n-bit unit data is photoelectrically converted, and an optical signal is sent to the optical fiber line or the optical transmission line 5 in the air. This optical signal is a multilevel signal corresponding to the amount of light (light intensity).
The transmission device 2 processes the MAC frame of data to be transmitted and generates various signals to be transmitted in synchronization with the clock signal CLK acquired from the data processing device 4.
As will be described later, the transmission device 2 of the present embodiment includes so-called AC coupling and is configured as a circuit that transmits an AC signal.

  In the following description, data obtained from the data processing device 4 and converted from data to be transmitted into an optical signal is referred to as a data signal. In addition to this data signal, the transmitter 2 generates a reference signal as an optical signal for its own LD (laser diode) power control and clock recovery on the receiving side, for example, as will be described later. It is added to the data signal and transmitted to the receiving device 3.

The interval of the reference signal can be set as appropriate, but it depends on the allowable level of clock deviation between the transmission device 2 and the reception device 3, the fluctuation speed of the loss due to the optical transmission path 5, and the fluctuation speed of the LD power accompanying the temperature change. Thus, the upper limit required for the system is determined.
In the optical transmission system 1 according to the present embodiment, a reference signal is added to the head of a data signal and transmitted in units of n bits.

The receiving device 3 includes a photodiode PD1 that receives the optical signal transmitted from the transmitting device 2.
The receiving device 3 sets 2 ⁿ −1 threshold values between the minimum value and the maximum value of the received signal, compares the set threshold value with the received signal by a comparator, and 2 ⁿ -Has a function of obtaining one comparator output.
Then, the receiving device 3 outputs a comparison output with the first threshold value close to the minimum value of the received signal, preferably the comparison value with the smallest threshold value among the 2 ⁿ -1 comparator outputs at the first level ( The timing (rise timing) when changing from the low level in the present embodiment to the second level (the high level in the present embodiment) and the second threshold value that is close to the maximum value of the received signal, preferably the largest The clock is regenerated from two timings of the timing at which the comparison output by the threshold changes from the second level to the first level (falling timing), and 2 ⁿ -1 comparison outputs are synchronized with the regenerated clock. Has a function of latching.
Note that the receiving device 3 has a function of adjusting the phase of the recovered clock so that the phases of the data input and the clock input are aligned when latching.
Then, the receiving device 3 takes in the latched 2 ⁿ -1 comparator outputs, counts the least significant bit (0) to the most significant bit (2 ⁿ -1) in order, up to the most significant bit. Has a data reproduction function in which the count value is a received value (composite value).

Next, a specific configuration of the transmission device 2 will be described.
FIG. 2 is a diagram illustrating an example of a circuit configuration of the transmission device 2.

  As shown in FIG. 2, the transmission device 2 includes a serial / parallel converter 21, an auto power controller (APC) 22, a current controller 23, a resolution setting unit 24, and a digital / analog converter (DAC). 25, a laser diode LD1 as a light emitting element, and a photodiode PD2 as a light receiving element for monitoring.

The serial / parallel converter 21 converts the serial data DATA synchronized with the clock signal CLK1 into an n-bit (data D0 to D2) parallel signal in order to process the MAC frame received from the data processing device 4 in units of n bits. To do. Further, a signal corresponding to the level of the n-bit data D0 to D2 is given to the current control unit 23.
In FIG. 2, for example, when the data D2 is “1”, the signal S211 becomes “L level (low level)”, and the signal S212 becomes “H level”. For example, when the data D2 is “0”, the signal S211 becomes “H level” and the signal S212 becomes “L level”. The same applies to the other data D1 and D0.

As shown in FIG. 2, the current control unit 23 includes control circuits 230 to 232 that control the current corresponding to the n-bit output (data D0 to D2) of the serial / parallel conversion unit 21 to flow through the laser diode LD1, And a current control circuit 233 that generates a bias current of the laser diode LD1.
As shown in FIG. 2, since the current control circuits 230 to 232 corresponding to the data D0 to D2 have the same configuration, only the current control circuit 232 will be described below.

As shown in FIG. 2, the current control circuit 232 includes load resistors R1 and R2, emitter-common npn transistors Q1 and Q2, an npn transistor Q3 as a constant current source, an operational amplifier OPA1, and a resistor R3.
When the data D2 is “1”, the signal S211 is at L level and the signal S212 is at H level, so that the transistor Q1 is turned off and the transistor Q2 is turned on. The collector of transistor Q2 is coupled to the cathode side of laser diode LD1 via capacitor C7. Therefore, a current substantially equal to the emitter current of the transistor Q3, which is a constant current source, is passed (pulled) from the laser diode LD1 side through the transistor Q2.
When the data D2 is “0”, the signal S211 is at the H level and the signal S212 is at the L level, so that the transistor Q1 is turned on and the transistor Q2 is turned off. Therefore, no current flows (does not pull) from the laser diode LD1 side.

  When the data D2 is “1”, the current flowing through the emitter of the transistor Q3, which is a constant current source, is set by a signal S2 set to one of the input terminals of the operational amplifier OPD1. That is, since the output terminal of the operational amplifier OPA1 is fed back to the input side via the base of the transistor Q3, in the balanced state, the other voltage level of the input terminal of the operational amplifier OPA1 is equivalent to the signal S2, and the emitter current I2 Becomes (voltage level of S2) / R3.

  The collector of the transistor Q2 connected to the resistor R2 of the other current control circuits 230 and 231 is connected to the cathode side of the laser diode LD1 via different capacitors C0 and C1, respectively.

  The current control circuit 233 that generates the bias current of the laser diode LD1 includes, for example, the transistor Q3, the resistor R3, the npn transistor Q4 corresponding to the operational amplifier OPA1, the resistor R4, the operational amplifier OPA2, and the laser diode of the current control circuits 230 to 232. Inductor L1 connected between the cathode side of LD1, the connection point of capacitors C0 and C1, and the collector of transistor Q4 is included.

In the present embodiment, the reason why the current control circuits 230 to 237 are driven by the voltage change generated by the resistor R2 is as follows.
For example, when the transistor Q2 of each of the current control circuits 230 to 232 is connected to the cathode side of the laser diode LD1 as a so-called open collector without passing through a capacitor, in order to perform multi-value and high-speed modulation, The output capacity of the open collector becomes a bottleneck.
That is, the output impedance varies greatly, and when a certain bit outputs current, the load changes depending on whether or not other bits output current, and the current flowing through the laser diode LD1 that is a light emitting element becomes unstable. There is a risk. That is, there is a possibility of affecting each bit.
Further, the output impedance is capacitive, and current is drawn not only from the laser diode LD1 but also from the capacitance of the output stage of other bits during high-speed modulation, the optical output signal is lowered in multiple values and the rise is delayed. There is a fear. That is, there is a possibility that the modulation speed becomes slow due to the parasitic capacitance.
Therefore, in this embodiment, the laser diode LD1 is driven by a voltage change generated by the resistor R2 so that the output of the transistor Q2 is not affected by the parasitic capacitance of the transistor, and reflection of the high-frequency signal between the bit outputs is performed. In order to prevent this, impedance is matched with the transmission line 5.
By adding a resistor, the DC potential of the laser diode LD1 and the DC potential of the driver output are not balanced, so a configuration is adopted in which AC coupling is performed via the capacitors C0 to C2.

As described above, in the current control unit 23 of the optical multilevel transmission transmitter 2 in the present embodiment, the current control circuits 230 to 232 as the light emitting element driving circuits for each bit do not affect each other in terms of high frequency. Further, the output impedance of the circuit is configured to be constant regardless of the on / off state of the circuit, and the current output stage is connected to the reference potential (power supply potential VCC in the present embodiment) via a resistor. When a current is output with a certain bit, load fluctuation due to the current output state of other bits is eliminated, and the current flowing through the light emitting element is stabilized.
Further, in the current control unit 23, the output impedance of the circuit is a necessary band of the frequency component of the drive current so that the current control circuits 230 to 232 as the light emitting element drive circuits of each bit do not affect each other in terms of high frequency. The current output stage is connected to a reference potential (power supply potential VCC in this embodiment) via a resistor, and the resistance value of the current output stage is By making the impedance smaller than the capacitance, the rise and fall of the optical output signal becomes faster.
Further, in the current control unit 23, the output impedance of the circuit is changed to the laser diode LD1 which is a light emitting element so that the current control circuits 230 to 232 as the light emitting element driving circuits of each bit do not affect each other in terms of high frequency. The current output stage is connected to a reference potential (in this embodiment, the power supply potential VCC) via a resistor, and the resistance value is set to a laser diode (light emitting element). By making it equal to the characteristic impedance of the transmission line connecting the LD 1 and the current output stage, reflection due to impedance mismatch between the current output stage and the transmission line (wiring) on the substrate can be suppressed.

As shown in FIG. 2, each of the current control circuits 230 to 232 has a configuration in which the laser diode LD1 is driven by only one transistor of the differential output stage formed by the transistors Q1 and Q2, and FIG. B), the collector of the transistor Q2 is connected to the cathode side of the laser diode LD1 via the capacitor C11, and the collector of the transistor Q1 connected to the resistor R2 is connected to the anode side of the laser diode LD1 via the capacitor C12. It is also possible to connect to and drive both differential output stages.
In the example of FIG. 3B, a configuration is adopted in which the inductor L2 on the anode side of the laser diode LD1 is connected to improve the matching.

The resolution setting unit 24 includes a digital-to-analog converter (DAC) 241 and a plurality of operational amplifiers 242, and converts the adjustment signal S _mod generated by the auto power control unit 22 into the analog signal S2, and the analog signal. The voltage level of S2 is halved in order. Thereby, signals S1 and S0 are generated in order.
That is, S1 = (1/2) × S2 and S0 = (1/2) × S1.

As described above, the current control circuits 230 to 232 of the current control unit 23 generate the constant currents I0 to I2 corresponding to the voltage levels of the signals S0 to S2 when the corresponding data D0 to D2 is “1”. Is done. Then, by setting the signals S2, S1, and S0 described above, the current values of the constant currents I2, I1, and I0 are sequentially multiplied by 1/2.
That is, I1 = (1/2) × I2 and I0 = (1/2) × I1.

The digital / analog converter (DAC) 25 converts the constant bias signal _Sbias generated by the auto power control unit 22 into an analog signal S3.
In response to the analog signal S3, the current control circuit 233 of the current control unit 23 generates a constant current I3. The constant current I3 is a current for securing an optical signal having a constant light amount without depending on the serial data DATA input to the data rearrangement unit 21.

A current obtained by integrating a constant current flowing through each current control circuit of the current control unit 23 flows through the laser diode LD1. That is, the current I _LD1 flowing through the laser diode LD1 is I0 + I1 + I2 + I3. As a result, a multi-value current corresponding to the 3-bit parallel data D0 to D2 flows through the laser diode LD1 as a light emitting element, and a multi-value optical signal is transmitted.
As described above, in the transmission device 2, each current control circuit 230-232 gives a bit weight to each bit of the parallel data D <b> 0-D <b> 2, and an amplitude-multiplexed multilevel optical signal is transmitted to the optical transmission line 5. Sent out.

The photodiode PD2 and the auto power control unit 22 constitute a feedback loop for power control of the laser diode LD1. That is, the optical signal generated by the laser diode LD1 is received by the photodiode PD2, photoelectrically converted and fed back to the auto power control unit 22, and the adjustment signal S _mod is changed according to the value.
The LD power control is a calibration process of the transmission apparatus 2 that is periodically performed to compensate for a change in output characteristics of the laser diode caused by an environmental change such as a temperature change. Usually, LD power control is performed at long intervals of 1 second to 10 seconds.
After the LD power control is completed, data to be transmitted (for example, 8-bit MAC frame data) is provided to the data rearrangement unit 21. At this time, the signal of the adjustment signal S _mod of the auto power control unit 22 is provided. The level is fixed and the feedback loop does not function.

Next, a reference signal transmitted by the transmission device 2 will be described.
The reference signal is inserted into a data signal of a predetermined data unit such as an 8-bit unit of the MAC frame, and the purpose thereof is LD power control and clock signal reproduction on the receiving side.
As described above, the LD power control may be performed every long period of 1 second to 10 seconds in order to cope with an environmental change. However, the clock signal regeneration on the receiving side is performed by using, for example, an optical fiber line in the optical transmission line 5. In this case, since it is affected by physical factors such as bending and pulling on the optical fiber line, for example, a 1-gigabit-second optical signal corresponding to a standard such as Gigabit Ethernet (registered trademark) once every 100 samples. It is necessary to carry out at very short intervals such as (once every 100 nanoseconds).

4A and 4B are optical signal waveform diagrams showing an example of the reference signal. FIG. 4A shows a case where LD power control is performed, and FIG. 4B shows a case where LD power control is not performed.
As shown in FIG. 4, when LD power control is performed (FIG. 4 (A)), it takes time until the output of the laser diode LD1 is stabilized especially when the power is turned on or reset. In order to perform the control, a long period is required as the reference signal SREF.
On the other hand, when the LD power control is not performed (FIG. 4B), the reference signal SREF may be at least one pulse for reproducing the clock signal on the receiving device 3 side (for clock reproduction). ) Is sufficient, and the reference signal SREF does not require a long period.
Thus, the reference signal SREF is a signal with a different signal period depending on the transmission timing.

  In the optical transmission system 1 according to the present embodiment, the reference signal SREF includes a function of transmitting the frame number of the MAC frame transmitted in units of 8 bits to the receiving side. This frame number is defined by the number of pulses for clock signal reproduction described above.

FIG. 5 is an optical signal waveform diagram showing an example of a reference signal defining a frame number.
In the example shown in FIG. 5, the number of pulses of the reference signal SREF added to the head of the n-bit data signal changes in order of 4 → 3 → 2. The number of pulses is counted on the receiving device 3 side and associated with the frame number.

In addition to the frame number, a base signal (adjustment pulse) for calibration of the optical signal on the receiving side may be included in the reference signal.
The amount of light of the transmitted optical signal is the same due to a change in transmission characteristics (non-linear characteristics) affected by physical factors (bending, pulling) of the optical transmission path (for example, optical fiber line) 5. However, the reception level of the optical signal on the receiving device 3 side may change greatly. In order to compensate for this change, the process of adjusting the reception level on the receiving device 3 side is calibration.

FIG. 6 is a diagram illustrating an example of an optical signal waveform of a reference signal including the adjustment pulse and a pulse indicating a frame number.
For easy understanding, the reference signal shown in FIG. 6 has a ternary pulse including a maximum value and a minimum value of an optical signal as a data signal in order to correct a nonlinear characteristic of a transmission characteristic. . Selection of the digital value corresponding to these three values needs to be performed in advance between the transmission device 2 and the reception device 3 in terms of the communication protocol.
In the reference signal shown in FIG. 6, a reference signal including three pulses of amplitude levels a, b, and c corresponding to three digital values is transmitted to the receiving device 3 for correction (calibration) of the data signal. Used.

As shown in FIG. 6, in the reference signal, when the adjustment pulse APLS is inserted before the plurality of pulses indicating the frame number, or the first three pulses among the plurality of pulses indicating the frame number are used as the adjustment pulse. In this case, since the clock signal can be reproduced on the receiving side based on the adjustment pulse, the pulse indicating the frame number may be a multi-value pulse.
That is, instead of associating the number of pulses with the frame number, the frame number can be defined by a plurality of pulses having different amplitudes. As a result, even when the number of frame numbers is very large, the frame number can be expressed with a small number of pulses, and efficient communication becomes possible.

Next, a specific configuration of the receiving device 3 will be described.
FIG. 7 is a diagram illustrating an example of a circuit configuration of the receiving device 3.

  As shown in FIG. 7, the receiver 3 includes a photodiode PD1 as a light receiving element, a resistor R31, a coupling capacitor C31, a buffer amplifier 31, a peak / bottom detection hold circuit 32, a threshold setting circuit 33, and a comparison latch unit 34. A clock unit 35 and a data reproduction unit (DSP) 36.

  The buffer amplifier 31 performs photoelectric conversion by the photodiode PD1 and the resistor R31, takes in a signal via the capacitor C31, and generates an analog reception signal Vrx.

  The peak / bottom detection hold circuit 32 detects the peak value PV and the bottom value BV of the 8-value received signal Vrx with n (3 in this embodiment) bits, and stores the detected peak value PV and bottom BV value. The held peak value PV and bottom value BV are output to the threshold value setting circuit 33 together with the reception signal Vrx as the maximum value signal Vmax and the minimum value signal Vmin, respectively.

  FIG. 8 is a block diagram showing a configuration example of the peak / bottom detection hold circuit according to the present embodiment.

  The peak / bottom detection hold circuit 32 in FIG. 8 includes a peak value detection unit 321, a bottom value detection unit 322, a peak value hold circuit 323, and a bottom value hold circuit 324.

The peak value detection unit 321 detects the peak value PV of the reception signal Vrx through the low-pass filter LPF through the 8-level reception signal Vrx with n (3 in this embodiment) bits.
The bottom value detection unit 321 detects the bottom value BV of the reception signal Vrx by passing the 8-level reception signal Vrx with n (3 in the present embodiment) through the low-pass filter LPF.
The peak value hold circuit (PH) 323 holds the peak value PV detected by the peak value detection unit 321 and outputs the held peak value PV to the threshold value setting circuit 33 as the maximum value signal Vmax.
The bottom value hold circuit (BH) 324 holds the bottom value BV detected by the bottom value detection unit 322, and outputs the held bottom value MV to the threshold value setting circuit 33 as the minimum value signal Vmin.

The threshold setting circuit 33 receives the maximum value signal Vmax and the minimum value signal Vmin of the reception signal Vrx supplied from the peak / bottom detection hold circuit 32, and receives 2 between the minimum value and the maximum value of the reception signal. ⁿ −1 threshold values are set and supplied to the comparison latch unit 34 together with the reception signal Vrx.
In this example, since n = 3, as shown in FIG. 9, seven threshold values Vth01, Vth12, Vth23, Vth34, Vth45, and Vth56 are obtained in ascending order with respect to the received signal Vrx.

  FIG. 10 is a circuit diagram showing a configuration example of the threshold setting circuit according to the present embodiment.

10 is formed by resistance elements 331 to 338 connected in series between a supply line for the maximum value signal Vmax and a supply line for the minimum value signal Vmin. A voltage obtained by dividing the resistance by the node) is generated as a threshold value.
The resistance values of the resistance elements 331 and 338 at both ends are set to R, and the resistance values of the remaining resistance elements R332 to 337 are set to 2R.

The threshold setting circuit 33 generates and outputs a threshold Vth01 having a predetermined voltage at the connection node ND11 between the resistance elements 338 and 337.
Similarly, threshold setting circuit 33 generates and outputs threshold Vth12 having a predetermined voltage at connection node ND12 between resistance elements 337 and 336.
The threshold setting circuit 33 generates and outputs a threshold Vth23 having a predetermined voltage at the connection node ND13 between the resistance elements 336 and 335.
The threshold setting circuit 33 generates and outputs a threshold Vth34 having a predetermined voltage at the connection node ND14 between the resistance elements 335 and 334.
The threshold setting circuit 33 generates and outputs a threshold Vth45 having a predetermined voltage at the connection node ND15 between the resistance elements 334 and 333.
The threshold setting circuit 33 generates and outputs a threshold Vth56 having a predetermined voltage at the connection node ND16 between the resistance elements 333 and 332.
The threshold setting circuit 33 generates and outputs a threshold Vth67 having a predetermined voltage at a connection node ND17 between the resistance elements 332 and 331.

The comparison latch unit 34 compares each of the 2 ⁿ -1 threshold values Vth01 to Vth67 set by the threshold value setting unit 33 with the received signal Vrx by a comparator, and 2 ⁿ -1 In the embodiment, 7 comparator outputs are obtained, and the clock unit 35 generates the comparator outputs based on the two comparison outputs, and latches each comparator output in synchronization with the phase-adjusted clock CLK2. In addition, the data is output to the data reproducing unit 36 in synchronization with the clock CLK2.

The clock unit 35 outputs a comparison output with a first threshold value close to the minimum value of the received signal, preferably the smallest threshold value Vth01, out of 2 ⁿ -1 comparator outputs of the comparison latch unit 34. The timing (rise timing) when the first level (low level in the present embodiment) changes to the second level (high level in the present embodiment), and a second threshold value close to the maximum value of the received signal, preferably The clock is regenerated from two timings at which the comparison output with the largest threshold Vth67 changes from the second level to the first level (falling timing).
The clock unit 35 also adjusts the phase of the recovered clock so that the phase of the data input and the clock input are aligned when the comparison latch unit 34 latches 2 ⁿ -1 comparator outputs in synchronization with the recovered clock. A clock CLK2 is generated.

  FIG. 11 is a diagram illustrating a configuration example including a comparison latch unit, a clock unit, and a data reproduction unit according to the present embodiment.

In FIG. 11, the comparison latch unit 34 includes 2 ⁿ −1 (seven in this embodiment) comparators 341 to 347 and a latch unit 348 including 7-bit D-type flip-flops (DFFs). .

The comparator 341 compares the received signal Vrx and the threshold value Vth01, and outputs a high level or low level comparison result to the latch unit 348 and the clock unit 35 as a signal S341 according to the comparison result.
The comparator 342 compares the received signal Vrx and the threshold value Vth12, and outputs a high level or low level comparison result to the latch unit 348 as a signal S342 according to the comparison result.
The comparator 343 compares the received signal Vrx and the threshold value Vth23, and outputs a high level or low level comparison result to the latch unit 348 as a signal S343 according to the comparison result.
The comparator 344 compares the received signal Vrx and the threshold value Vth34, and outputs a high level or low level comparison result to the latch unit 348 as a signal S344 according to the comparison result.
The comparator 345 compares the received signal Vrx and the threshold value Vth45, and outputs a high level or low level comparison result to the latch unit 348 as a signal S345 according to the comparison result.
The comparator 346 compares the received signal Vrx and the threshold value Vth56, and outputs a high level or low level comparison result to the latch unit 348 as a signal S346 according to the comparison result.
The comparator 347 compares the received signal Vrx with the threshold value Vth67, and outputs a high level or low level comparison result as a signal S347 to the latch unit 348 and the clock unit 35 according to the comparison result.

The latch unit 348 has seven input terminals DIN0 to DIN6 and seven output terminals DOUTO to DOUT6.
The latch unit 348 inputs and latches the output signal S341 of the comparator 341 from the input terminal DIN0 in synchronization with the clock CLK2, and the data reproduction unit uses the latch signal as the signal CD0 from the output terminal DOUT0 in synchronization with the clock CLK2. 36.
Similarly, the latch unit 348 inputs and latches the output signal S342 of the comparator 342 from the input terminal DIN1 in synchronization with the clock CLK2, and also latches the latch signal from the output terminal DOUT1 as the signal CD1 in synchronization with the clock CLK2. The data is output to the data reproducing unit 36.
The latch unit 348 inputs and latches the output signal S343 of the comparator 343 from the input terminal DIN2 in synchronization with the clock CLK2, and the data reproduction unit converts the latch signal from the output terminal DOUT2 to the signal CD2 in synchronization with the clock CLK2. 36.
The latch unit 348 inputs and latches the output signal S344 of the comparator 344 from the input terminal DIN3 in synchronization with the clock CLK2, and the data reproduction unit converts the latch signal from the output terminal DOUT3 to the signal CD3 in synchronization with the clock CLK2. 36.
The latch unit 348 inputs and latches the output signal S345 of the comparator 345 from the input terminal DIN4 in synchronization with the clock CLK2, and the data reproduction unit converts the latch signal from the output terminal DOUT4 to the signal CD4 in synchronization with the clock CLK2. 36.
The latch unit 348 inputs and latches the output signal S346 of the comparator 346 from the input terminal DIN5 in synchronization with the clock CLK2, and the data reproduction unit converts the latch signal from the output terminal DOUT5 to the signal CD5 in synchronization with the clock CLK2. 36.
The latch unit 348 inputs and latches the output signal S347 of the comparator 347 from the input terminal DIN6 in synchronization with the clock CLK2, and the data reproduction unit converts the latch signal from the output terminal DOUT to the signal CD6 in synchronization with the clock CLK2. 36.

The clock unit 35 includes a clock generation unit 351 and a phase adjustment unit 352.
The clock generation unit 351 is configured by, for example, a PLL or DLL, and the timing (rise timing) at which the comparison output S341 based on the smallest threshold value Vth01 of the reception signal changes from the low level L to the high level H, and one of the reception signals. The clock is regenerated from two timings at which the comparison output by the largest threshold Vth67 changes from the second level to the low level (falling timing).
The phase adjustment unit 352 receives the reproduction clock generated by the clock generation unit 351, and uses the reference clock Refclk as a data input when latching 2 ⁿ -1 comparator outputs in synchronization with the reproduction clock. A clock CLK2 in which the phase of the reproduction clock is adjusted so that the phases of the clock inputs are aligned is generated and output to the latch unit 348 and the data reproduction unit 36.

The data recovery unit 36 fetches 2 ⁿ -1 comparator outputs latched in synchronization with the clock CLK2, and sequentially counts the least significant bit (0) to the most significant bit (2 ⁿ -1), It has a data reproduction function that uses the count value up to the most significant bit as a received value (composite value).

The data reproducing unit 36 is formed by a DSP, for example.
12 to 15 are diagrams schematically illustrating the configuration and function of the data reproducing unit according to the present embodiment.

As shown in the drawing, the data reproducing unit 36 includes seven 7-bit registers Reg0 to Reg6 and seven counters 361 to 367.
For example, if the comparator output is latched as data CD0 to CD6 by the latch unit 348 at time t0, the data reproducing unit 36 takes in the data CD0 into the register Reg0 in synchronization with the clock at time t1, for example, as shown in FIG. The counter 361 counts this.
Subsequently, at time t2, the data CD1 is taken into the register Reg1 in synchronization with the clock, and for example, as shown in FIG.
Similarly, at time t7, data CD6 is fetched into the register Reg6 in synchronization with the clock, and for example, as shown in FIG.
Then, as shown in FIG. 14, the counter 341 from the least significant bit to the most significant bit is used as the received value (composite value).
The same counting operation is performed for the other counters 362 to 367.

FIG. 16 is a diagram illustrating another configuration example of the data reproducing unit according to the present embodiment.
The data reproducing unit 36A in FIG. 16 is configured to simplify the circuit without using a DSP. Note that the registers and counters, which are the components of FIGS. 12 to 15, are the same, and are therefore denoted by the same reference numerals.

  The data reproducing unit 36A includes a 7 to 7 switch circuit 368, a 7 to 1 selector 369, and a received value buffer 370 in addition to the registers Reg0 to Reg6 and counters 361 to 367.

The 7-to-7 switch circuit 368 has seven input terminals I0 to I6 and seven output terminals O0 to O6.
The data held in the register Reg0 is supplied to the input terminal I0, the data held in the register Reg1 is supplied to the input terminal I1, the data held in the register Reg2 is supplied to the input terminal I2, and the data stored in the register Reg3 is supplied to the input terminal I3. The holding data is supplied, the holding data of the register Reg4 is supplied to the input terminal I4, the holding data of the register Reg5 is supplied to the input terminal I5, and the holding data of the register Reg6 is supplied to the input terminal I6.
The 7 to 7 switch circuit 368 is configured to be selectively connectable between the seven input terminals I0 to I6 and the seven output terminals O0 to O6, for example, like a crossbar circuit.

The 7-to-1 selector 369 has seven input terminals S0 to S6 and one output terminal SO.
The count value of the counter 361 is supplied to the input terminal S0, the count value of the counter 362 is supplied to the input terminal S1, the count value of the counter 363 is supplied to the input terminal S2, and the count value of the counter 364 is supplied to the input terminal S3. The count value is supplied, the count value of the counter 365 is supplied to the input terminal S4, the count value of the counter 366 is supplied to the input terminal S5, and the count value of the counter 367 is supplied to the input terminal S6.
The 7-to-1 selector 369 selectively outputs the count values of the counters 361 to 367 supplied to the input terminals S0 to S6 to the reception value buffer 370 from the output terminal SO.

  Counters 361 to 367 are asynchronously reset by reset signals RST1 to RST7.

  FIG. 17 is a diagram illustrating a correspondence relationship between the 7-to-7 switch circuit and the 7-to-1 selector in FIG. 16 at each time.

At time t1, the 7-to-7 switch circuit 368 has the input terminal I0 and the output terminal O0 connected, the input terminal I6 and the output terminal O1 connected, the input terminal I5 and the output terminal O2 connected, and the input terminal I4 and The output terminal O3 is connected, the input terminal I3 and the output terminal O4 are connected, the input terminal I2 and the output terminal O5 are connected, and the input terminal I1 and the output terminal O6 are connected.
At this time, the 7-to-1 selector 369 selects the count value to the input terminal S1, that is, the count value of the counter (B) 362, and outputs it to the reception value buffer 370.

Then, after the counter (B) 362 is reset, at time t2, the 7-to-7 switch circuit 368 has the input terminal I1 and the output terminal O0 connected, the input terminal I0 and the output terminal O1 connected, and the input terminal I6 and output terminal O2 are connected, input terminal I5 and output terminal O3 are connected, input terminal I4 and output terminal O4 are connected, input terminal I3 and output terminal O5 are connected, and input terminal I2 and output terminal O6 are connected Connected.
At this time, the 7-to-1 selector 369 selects the count value to the input terminal S2, that is, the count value of the counter (C) 363, and outputs it to the reception value buffer 370.

Next, after the counter (C) 363 is reset, at time t3, the 7-to-7 switch circuit 368 has the input terminal I2 connected to the output terminal O0, the input terminal I1 connected to the output terminal O1, and the input. The terminal I0 and the output terminal O2 are connected, the input terminal I6 and the output terminal O3 are connected, the input terminal I5 and the output terminal O4 are connected, the input terminal I4 and the output terminal O5 are connected, and the input terminal I3 and the output terminal O6. Is connected.
At this time, the 7-to-1 selector 369 selects the count value to the input terminal S3, that is, the count value of the counter (D) 364, and outputs it to the received value buffer 370.

Next, after the counter (D) 364 is reset, at time t4, the 7-to-7 switch circuit 368 has the input terminal I3 connected to the output terminal O0, the input terminal I2 connected to the output terminal O1, and the input. The terminal I1 and the output terminal O2 are connected, the input terminal I0 and the output terminal O3 are connected, the input terminal I6 and the output terminal O4 are connected, the input terminal I5 and the output terminal O5 are connected, and the input terminal I4 and the output terminal O6. Is connected.
At this time, the 7-to-1 selector 369 selects the count value to the input terminal S4, that is, the count value of the counter (E) 365, and outputs it to the reception value buffer 370.

Next, after the counter (E) 365 is reset, at time t5, the 7-to-7 switch circuit 368 has the input terminal I4 and the output terminal O0 connected, the input terminal I3 and the output terminal O1 connected, and the input Terminal I2 and output terminal O2 are connected, input terminal I1 and output terminal O3 are connected, input terminal I0 and output terminal O4 are connected, input terminal I6 and output terminal O5 are connected, input terminal I5 and output terminal O6 Is connected.
At this time, the 7-to-1 selector 369 selects the count value to the input terminal S5, that is, the count value of the counter (F) 366, and outputs it to the reception value buffer 370.

Next, after the counter (F) 366 is reset, at time t6, the 7-to-7 switch circuit 368 has the input terminal I5 connected to the output terminal O0, the input terminal I4 connected to the output terminal O1, and the input. Terminal I3 and output terminal O2 are connected, input terminal I2 and output terminal O3 are connected, input terminal I1 and output terminal O4 are connected, input terminal I0 and output terminal O5 are connected, input terminal I6 and output terminal O6 Is connected.
At this time, the 7-to-1 selector 369 selects the count value to the input terminal S6, that is, the count value of the counter (G) 367, and outputs it to the reception value buffer 370.

Next, after the counter (G) 367 is reset, at time t7, the 7-to-7 switch circuit 368 has the input terminal I6 connected to the output terminal O0, the input terminal I5 connected to the output terminal O1, and the input. The terminal I4 and the output terminal O2 are connected, the input terminal I3 and the output terminal O3 are connected, the input terminal I2 and the output terminal O4 are connected, the input terminal I1 and the output terminal O5 are connected, and the input terminal I0 and the output terminal O6. Is connected.
At this time, the 7-to-1 selector 369 selects the count value to the input terminal S0, that is, the count value of the counter (A) 361, and outputs it to the reception value buffer 370.

Next, after the counter (A) 361 is reset, for example, at time t8 (t0), the 7-to-7 switch circuit 368 has the input terminal I0 and the output terminal O0 connected, and the input terminal I6 and the output terminal O1 connected to each other. Connected, input terminal I5 and output terminal O2, input terminal I4 and output terminal O3 connected, input terminal I3 and output terminal O4 connected, input terminal I2 and output terminal O5 connected, input terminal I1 Are connected to the output terminal O6.
At this time, the 7-to-1 selector 369 selects the count value to the input terminal S1, that is, the count value of the counter 362, and outputs it to the reception value buffer 370.

  Next, the operation of the optical transmission system 1 will be described.

First, simultaneously with the activation of the system, the transmitter 2 starts LD power control. As a result, the value of the current flowing through the laser diode LD1 is adjusted so that an optical signal having a constant light amount is transmitted with respect to the digital signal to be transmitted.
In the transmitter 2, the data to be transmitted is converted into parallel data D0 to D2 by the serial / parallel converter 21, and the current value is adjusted by the current controller 23 and transmitted from the laser diode LD1.
A reference signal SREF is also sent out.

In the receiving device 3, a signal that is photoelectrically converted by the photodiode PD 1 and the resistor R 31 and is taken in by the buffer amplifier 31 is captured by the buffer amplifier 31, and an analog received signal Vrx is generated and output to the peak / bottom detection hold circuit 32. .
In the peak / bottom detection hold circuit 32, the peak value PV and the bottom value BV of the eight-value received signal Vrx are detected and held by n (3 in this embodiment) bits, and the maximum value signal Vmax and the minimum value signal value are respectively held. Vmin is output to the threshold setting circuit 33 together with the reception signal Vrx.

The threshold value setting circuit 33 receives the maximum value signal Vmax and the minimum value signal Vmin of the reception signal Vrx supplied from the peak / bottom detection hold circuit 32, and 2 between the minimum value and the maximum value of the reception signal. ⁿ⁻ 1 threshold values Vth01, Vth12, Vth23, Vth34, Vth45, and Vth56 are set and supplied to the comparison latch unit 34 together with the reception signal Vrx.
In the comparison latch unit 34, each of the 2 ⁿ -1 threshold values Vth01 to Vth67 set by the threshold value setting unit 33 is compared with the received signal Vrx by a comparator, and 2 ⁿ -1 (this In the embodiment, 7) comparator outputs are obtained.

In the clock unit 35, of the 2 ⁿ -1 comparator outputs of the comparison latch unit 34, the timing at which the comparison output based on the smallest threshold value Vth01 of the received signal changes from the low level L to the high level H (rising timing) ) And the timing at which the comparison output based on the largest threshold value Vth67 of the received signal changes from the high level H to the low level L (falling timing), the clock is regenerated.
Further, in the clock unit 35, when the comparison latch unit 34 latches 2 ⁿ -1 comparator outputs in synchronization with the recovered clock, the phase of the recovered clock is adjusted so that the phases of the data input and the clock input are aligned. The generated clock CLK2 is generated.

  In the comparison latch unit 34, each comparator output is latched in synchronization with the clock CLK2 that is generated based on the two comparison outputs of the comparison outputs in the clock unit 35 and further phase-adjusted, and in synchronization with the clock CLK2. The data is output to the data reproducing unit 36.

In the data recovery unit 36, 2 ⁿ −1 comparator outputs latched in synchronization with the clock CLK2 are taken into the register, and the least significant bit (0) to the most significant bit (2 ⁿ −1) are sequentially ordered. The count value up to the most significant bit is held in the buffer as a received value (composite value).

As described above, in the optical transmission system 1 according to the present embodiment, the receiver 3 sets and sets 2 ⁿ −1 threshold values between the minimum value and the maximum value of the received signal. thresholds and give each compared to 2 ⁿ -1 one comparator output by the comparator and a reception signal, 2 n ^-1 pieces of comparator output, the first Works close to the minimum value of the received signal A timing (rising timing) at which the comparison output by the threshold, preferably the smallest threshold, changes from the first level (low level in the present embodiment) to the second level (high level in the present embodiment); From two timings, the timing at which the comparison output by the second threshold value close to the maximum value of the received signal, preferably the largest threshold value changes from the second level to the first level (falling timing). Play the clock and this Raw clock in synchronization with the clock CLK2 which is phase adjustment latches 2 ⁿ -1 pieces of comparison outputs the latched 2 ⁿ -1 or incorporation comparator output, the most significant bits from the least significant bit (0) ( Since 2 ⁿ -1) are counted in order, and the count value up to the most significant bit is used as the received value (composite value), the following effects can be obtained.
In other words, no ADC is required, and clock reproduction with little jitter can be realized with a simple circuit configuration even at a high data transmission rate of GHz or higher in multi-level modulation communication in the amplitude direction.

In addition, the transmitting device 2 transmits a reference signal including a number of pulses corresponding to the frame number of the MAC frame before, for example, an 8-bit or 4-bit data signal, and the receiving device 3 receives the received reference signal. It is also possible to perform clock recovery for sampling based on this pulse, count the pulse to recognize the frame number, and associate it with a data signal received every 8 bits.
Therefore, it is not necessary to set a frame number identification pulse separately from the clock regeneration pulse, so that an optical signal can be transmitted efficiently.

The embodiments of the present invention are not limited to the above-described embodiments, and those skilled in the art can make various modifications without departing from the scope of the present invention. For example, the optical reception method according to the embodiment can also be applied to optical space transmission.
In addition, various reference signals and processes described in the above embodiments can be realized in combination.

It is a figure which shows the structural example of the optical transmission system 1 which concerns on embodiment of this invention. It is a figure which shows an example of the circuit structure of the transmitter in this embodiment. It is a circuit diagram which shows the other structural example of the current control circuit of a transmitter. It is an optical signal waveform diagram which shows an example of a reference signal. It is an optical signal waveform diagram which shows an example of the reference signal which prescribed | regulated the frame number. It is an optical signal waveform diagram which shows an example of the reference signal which added the signal for adjustment. It is a block diagram which shows an example of the circuit structure of the receiver which concerns on this embodiment. It is a block diagram which shows the structural example of the peak / bottom detection hold circuit which concerns on this embodiment. It is a figure which shows the relationship between the threshold value set between the minimum value and the maximum value of the received signal in this embodiment. It is a circuit diagram which shows the structural example of the threshold value setting circuit which concerns on this embodiment. It is a figure which shows the structural example containing the comparison latch part which concerns on this embodiment, a clock part, and a data reproduction | regeneration part. It is a figure which shows typically the structure and function of the data reproduction part which concern on this embodiment. It is a figure which shows typically the structure and function of the data reproduction part which concern on this embodiment. It is a figure which shows typically the structure and function of the data reproduction part which concern on this embodiment. It is a figure which shows typically the structure and function of the data reproduction part which concern on this embodiment. It is a figure which shows the other structural example of the data reproduction part which concerns on this embodiment. It is a figure which shows the corresponding relationship in each time of the 7 to 7 switch circuit of FIG. 16, and a 7 to 1 selector. It is a figure for demonstrating a subject.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Optical transmission system, 2 ... Transmission apparatus, 21 ... Serial / parallel conversion part, 22 ... Auto power control part, 23 ... Current control part, 24 ... Resolution setting part, 25... Digital-to-analog converter (DAC), 3... Receiver, 31... Buffer amplifier, 32... Peak / bottom detection hold circuit, 33. Comparison latch unit, 35... Clock unit, 36... Data recovery unit, LD1... Laser diode, PD1, PD2.

Claims (12)

A receiving apparatus that receives an n-bit multilevel signal that is multilevel modulated in the amplitude direction,
2 ⁿ -1 threshold values are set between the minimum value and the maximum value of the received signal, and a comparison unit including 2 ⁿ -1 comparators for comparing the threshold value with the received signal; ,
Of the 2 ⁿ -1 comparator outputs of the comparator, the timing at which the comparator output by the first threshold value close to the minimum value of the received signal changes from the first level to the second level, and the reception A clock recovery unit for recovering a clock from two timings of a timing at which the comparator output by the second threshold value close to the maximum value of the signal changes from the second level to the first level;
And a latch unit that latches 2 ⁿ -1 comparator outputs of the comparison unit in synchronization with the recovered clock. A detection unit for detecting a peak value and a bottom value of the received signal;
A hold circuit for storing the detected peak value and bottom value;
The receiving apparatus according to claim 1, further comprising: a setting circuit that sets the 2 ⁿ −1 threshold values from the stored peak value and bottom value. The 2 ⁿ -1 comparator outputs latched in the latch unit are fetched, the least significant bit (0) to the most significant bit (2 ⁿ -1) are counted in order, and the count value up to the most significant bit is counted. The receiving device according to claim 1, further comprising: a data reproducing unit that takes a value as a received value (composite value). The receiving apparatus according to claim 1, further comprising a phase adjustment unit that adjusts a phase of the reproduction clock so that a phase of a data input and a clock input of the latch unit are aligned. The receiving apparatus according to claim 2, further comprising: a phase adjusting unit that adjusts a phase of the reproduction clock so that a phase of a data input and a clock input of the latch unit are aligned. The receiving apparatus according to claim 3, further comprising: a phase adjusting unit that adjusts a phase of the reproduction clock so that a phase of a data input and a clock input of the latch unit are aligned. A receiving device that receives an n-bit signal that is multi-level modulated in the amplitude direction,
2 ⁿ -1 threshold values are set between the minimum value and the maximum value of the received signal, and a comparison unit including 2 ⁿ -1 comparators for comparing the threshold value with the received signal; ,
Of the 2 ⁿ -1 comparator outputs of the comparator, the timing at which the comparison output with the smallest threshold value changes from the first level to the second level and the comparison output with the largest threshold value is the first. A clock recovery unit for recovering a clock from two timings of the timing of changing from the second level to the first level;
A latch unit that latches 2 ⁿ -1 comparator outputs of the comparison unit in synchronization with the reproduction clock;
And a phase adjusting unit that adjusts the phase of the recovered clock so that the phase of the data input of the latch unit and the phase of the clock input are aligned. A detection unit for detecting a peak value and a bottom value of the received signal;
A hold circuit for storing the detected peak value and bottom value;
The receiving apparatus according to claim 7, further comprising: a setting circuit that sets the 2 ⁿ −1 threshold values from the stored peak value and bottom value. The counter has a counter that takes in 2 ⁿ -1 comparator outputs latched in the latch unit and counts the least significant bit (0) to the most significant bit (2 ⁿ -1) in order. The receiving apparatus according to claim 8, further comprising a data reproducing unit configured to receive values (composite values). The counter has a counter that takes in 2 ⁿ -1 comparator outputs latched in the latch unit and counts the least significant bit (0) to the most significant bit (2 ⁿ -1) in order. The receiving apparatus according to claim 9, further comprising a data reproducing unit configured to receive values (composite values). A transmission device that transmits an n-bit multilevel signal that is multilevel modulated in the amplitude direction to the transmission line;
A receiving device that receives an n-bit multi-level signal that is multi-level modulated in the amplitude direction,
The receiving device is
2 ⁿ -1 threshold values are set between the minimum value and the maximum value of the received signal, and a comparison unit including 2 ⁿ -1 comparators for comparing the threshold value with the received signal; ,
Of the 2 ⁿ -1 comparator outputs of the comparator, the timing at which the comparison output with the smallest threshold value changes from the first level to the second level and the comparison output with the largest threshold value is the first. A clock recovery unit for recovering a clock from two timings of the timing of changing from the second level to the first level;
A latch unit that latches 2 ⁿ -1 comparator outputs of the comparison unit in synchronization with the reproduction clock;
A phase adjustment unit that adjusts the phase of the recovered clock so that the phase of the data input of the latch unit and the phase of the clock input are aligned. A receiving method for receiving an n-bit multilevel signal that is multilevel modulated in the amplitude direction,
Setting 2 ⁿ −1 threshold values between a minimum value and a maximum value of the received signal;
Comparing the set threshold value with the received signal to obtain 2 ⁿ −1 comparison outputs;
Of the 2 ⁿ -1 comparison outputs, the comparison output with the smallest threshold value changes from the first level to the second level, and the comparison output with the largest threshold value changes from the second level to the second level. A step of regenerating the clock from two timings of timing changing to one level;
Latching 2 ⁿ -1 comparison outputs in synchronization with the recovered clock;
And a step of adjusting the phase of the recovered clock so that the phases of the data input and the clock input are aligned when the data is latched.

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