JP2008011320A - Semiconductor switch circuit and communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor switch circuit with reduced occurrence of distortion of high-frequency signals. <P>SOLUTION: In the semiconductor switch circuit 101 for controlling conduction and interruption of the high-frequency signals, gate width of a part of a field effect transistor 1 is set smaller than gate width Wg of other field effect transistors 2-4 among the serially connected multi-step field effect transistors 1-4, and a fixed displacement compressor Cp is connected between a gate G and a drain D, and between the gate G and a source S of the field effect transistor 1 whose gate width Wg is set small. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor switch circuit that switches high-frequency signals, and more particularly to a semiconductor switch circuit that suppresses the occurrence of distortion of a high-frequency signal while maintaining high-frequency signal cutoff characteristics.

  Some communication devices such as mobile phones use a semiconductor switch circuit that controls conduction and blocking of a high-frequency signal in order to cope with a plurality of different carriers.

  As this semiconductor switch circuit, a through field effect transistor (hereinafter referred to as a through FET) that is inserted in series with respect to the signal path to control the conduction and interruption of the signal, and is inserted in parallel with the signal path. Some devices use a combination of shunt field-effect transistors (hereinafter referred to as shunt FETs) that control signal conduction and interruption by controlling short-circuiting and opening of the signal path.

  A semiconductor switch circuit that controls conduction and interruption of this signal requires low on-resistance in order to efficiently receive weak signals, and has low distortion characteristics in order to efficiently convert received signals into data. It is requested.

  Conventionally, in order to reduce the insertion loss and distortion of the semiconductor switch circuit, the pinch-off voltage of the first field effect transistor stage connected in series with the signal path is used as the second electric field connected between the signal path and the ground potential. An invention is known in which the potential is set to a lower potential than the pinch-off voltage of the effect transistor stage (see, for example, Patent Document 1).

  In the semiconductor switch circuit described in Patent Document 1, the first field effect transistor and the second field effect transistor connected between the ground potential and the first field effect transistor are prevented from operating with the same operation characteristics. Only the first field effect transistor connected in series to the signal path can be turned on without generating leakage power between the drain and the source.

  In addition, in order to equalize the operation of a multi-stage field effect transistor (hereinafter referred to as FET), a resistor is connected between the drain and source of a plurality of FETs connected in series, and all FETs are connected. 2. Description of the Related Art A switch semiconductor integrated circuit configured so that drain and source bias points can be arbitrarily determined from the outside is known (for example, see Patent Document 2).

According to the switch semiconductor integrated circuit described in Patent Document 2, since the distortion is improved by equalizing the operation of each FET, it is possible to reduce the distortion in the high-frequency signal from medium power to high power. Has been.
JP-A-7-106937 JP 2005-323030 A

  The semiconductor switch circuit described in Patent Document 1 is an invention that improves distortion generated when a high-frequency signal applied between a drain and a source exceeds the pinch-off voltage of the shunt FET when the shunt FET is in a high impedance state. It is.

  On the other hand, the switch semiconductor integrated circuit described in Patent Document 2 is an invention that reduces distortion by preventing an operation imbalance of the FET caused by fluctuations in the voltage at the intermediate point of a multi-stage shunt FET.

  However, the distortion of the high-frequency signal caused by the shunt FET set to the high impedance state is caused by the parasitic capacitance existing between the gate-drain and the gate-source of the shunt FET in addition to the above. There is distortion. The distortion of the high frequency signal caused by the parasitic capacitance of the FET will be described with reference to FIG.

  FIG. 9 shows a circuit diagram of a general FET and an equivalent circuit in the operating state of the FET.

  As shown in FIG. 9, when a voltage higher than a threshold value is applied to the gate G of the FET so that the drain D and the source S are in a low impedance state, the equivalent circuit between the drain D and the source S is several Ω. Can be expressed by the on-resistance Ron.

  On the other hand, when a voltage sufficiently lower than the threshold value is applied to the gate G of the FET, the drain D and the source S are set in a high impedance state and can be expressed by an equivalent circuit having a cutoff capacitance of several hundred fF. .

  As described above, the FET having the high-resistance element Rg connected to the gate exhibits resistance in the low-impedance state and capacitance in the high-impedance state, and thus has excellent characteristics as a basic unit of the quasi-microwave band switch circuit. It has.

  However, as shown in FIG. 9, a parasitic capacitance Cg having voltage dependency exists between the gate G and the drain D and between the gate G and the source S of the FET. In addition, a certain capacitance Cds exists between the drain D and the source S.

  Since the parasitic capacitance Cg changes according to the thickness of the depletion layer existing in the vicinity of the gate electrode of the FET, the parasitic capacitance Cg has a voltage dependency that the parasitic capacitance increases as the voltage increases. Therefore, when an AC high frequency signal is applied between the drain D and the source S, the parasitic capacitance Cg changes according to the AC voltage, distortion occurs in the signal waveform, and harmonics are generated. Further, when high frequency signals having a plurality of frequencies are applied to both ends of the semiconductor switch circuit, an IMD (Inter Modulation Distortion) is generated, which causes a malfunction in the receiving circuit.

  Accordingly, an object of the present invention is to provide a semiconductor switch circuit in which the occurrence of high-frequency signal distortion is small and a communication device with few malfunctions in order to reduce malfunctions in the receiving circuit.

  In order to solve the above problems, the semiconductor switch circuit of the present invention is composed of a plurality of stages of FETs connected in series, and the gate width of some of the FETs of the plurality of stages is set to be larger than the gate widths of other FETs. A fixed-capacitance capacitor was connected between the gate and the drain and between the gate and the source of the FET which was set narrow and the gate width was set narrow.

  In the semiconductor switch circuit of the present invention, the capacitance of the capacitor is set such that the gate-source or gate-drain capacitance of the FET having a narrow gate width and the gate-source or gate- The capacitance was the difference between the capacitance between the drains.

  In order to solve the above problems, the communication device of the present invention includes a communication unit that transmits or receives a signal, a communication port that transmits or receives a signal to another communication device, a communication unit, and the communication A semiconductor switch circuit between the plurality of FETs connected in series, and the gate width of some of the FETs of the plurality of FETs is set to the gate of another FET. A fixed capacitor is connected between the gate and the drain and between the gate and the source of the FET set narrower than the width and narrowly set the gate width.

  According to the present invention, in a semiconductor switch circuit in which several FETs are connected in series, the size of some FETs is set to be smaller than that of other FETs, and between the gate and drain of smaller FETs, and Since a fixed-capacitance capacitor is connected between the gate and the source, it is possible to reduce harmonic distortion and IMD caused by FET-dependent parasitic capacitance when set to a high impedance state. .

  In addition, by using the semiconductor switch circuit described above for a communication device, it is possible to transmit a high-frequency signal with little distortion. Further, by reducing the occurrence of signal distortion caused by the semiconductor switch circuit, malfunctions in the receiving circuit can be reduced.

  A semiconductor switch circuit according to an embodiment of the present invention includes a plurality of FETs connected in series, and sets the gate width of some of the FETs of the plurality of FETs to be narrower than the gate width of other FETs. At the same time, a fixed-capacitance capacitor is connected between the gate and drain and between the gate and source of the FET having a narrow gate width. By using the semiconductor switch circuit configured in this way for the signal path of communication equipment such as a cellular phone, the conduction and blocking of high-frequency signals are controlled, so that the loss of signal transmission is suppressed and the voltage-dependent FET is controlled. Harmonic distortion and IMD generated due to parasitic capacitance can be reduced. Therefore, it is possible to improve the reception sensitivity of the communication device corresponding to a plurality of different carriers.

  Further, in the semiconductor switch circuit according to the embodiment of the present invention, the capacitance of the capacitor is set such that the capacitance between the gate and the source or the gate and drain of the FET with the narrow gate width is set, and the gate and source of the other FET. Or the difference between the capacitance between the gate and the drain. By configuring in this way, it is possible to cancel the increase in the impedance of the FET caused by setting the gate width narrow, and to make the voltage amplitude divided between the FETs uniform. Harmonic distortion caused by a certain parasitic capacitance and IMD can be reduced.

  The communication device according to the embodiment of the present invention includes a communication unit that transmits or receives a signal, a communication port that transmits or receives a signal to another communication device, a communication unit, and the communication port. The semiconductor switch circuit is composed of a plurality of FETs connected in series, and the gate width of some of the FETs of the plurality of FETs is larger than the gate width of other FETs. A fixed capacitor is connected between the gate and the drain and between the gate and the source of the FET which is set narrow and the gate width is narrow. Furthermore, the capacitance of the capacitor is determined by the difference between the gate-source or gate-drain capacitance of the FET having a narrow gate width and the gate-source or gate-drain capacitance of the other FET. It is good also as capacity.

  By configuring communication equipment in this way to control conduction and cutoff of high-frequency signals, while suppressing signal transmission loss, harmonic distortion generated due to voltage-dependent parasitic capacitance and IMD are reduced. Can be reduced. Therefore, it is possible to reduce the occurrence of distortion of a signal to be transmitted and improve the reception sensitivity of the signal.

  An example of use of a semiconductor switch circuit for conducting and blocking a high-frequency signal will be described with reference to FIG.

  FIG. 1 is a block diagram of a transmission / reception part of a mobile phone (one form of communication device) capable of switching a plurality of radio wave bands used for communication.

  The mobile phone shown in FIG. 1 includes semiconductor switch circuits SW1 to SW3 for switching between a radio wave band used in GSM (Global System for Mobile Communications) and a radio wave band of WCDMA (Wideband Code Division Multiple Access). I have. The semiconductor switch circuits SW1 to SW3 are provided between the antenna 20 (one form of communication port) that transmits and receives radio waves and the duplexer 22.

  In the mobile phone shown in FIG. 1, when information is transmitted and received using the WCDMA frequency band, the semiconductor switch circuit SW1 is set in a conducting state, and the antenna 20 and the duplexer 22 are brought into conduction.

  When the semiconductor switch circuit SW1 is set to a conductive state, for example, the gate voltage (Vg10) of the semiconductor switch circuit 101 is set to Lo, and the high impedance is generated between the drain D of the FET1 and the source S of the FET4 of the semiconductor switch circuit 101. At the same time, the gate voltage (Vg11) of the semiconductor switch circuit 111 is set to Hi so that the drain D and the source S of the semiconductor switch circuit 111 are in a low impedance state, and the antenna 20 and the duplexer 22 are made conductive. .

  On the other hand, the unused semiconductor switch circuits SW2 and SW3 in the GSM frequency band are set in a cut-off state. For example, when the semiconductor switch circuit SW2 is set to the cut-off state, the gate voltage (Vg20) of the semiconductor switch circuit 102 is set to Hi so that the drain D and the source S of the semiconductor switch circuit 102 are in a low impedance state. The gate voltage (Vg21) of the semiconductor switch circuit 112 is set to Lo so that the drain D and the source S of the semiconductor switch circuit 112 are in a high impedance state, the GSM circuit is disconnected from the antenna 20, and the GSM duplexer The input signal is interrupted by shorting the input terminal (not shown) to ground. Similarly, the semiconductor switch circuit SW3 is also set to a cut-off state.

  The duplexer 22 transmits a WCDMA transmission signal Tx having a frequency of 1.95 GHz output from the power amplifier 26 (one form of communication means for transmission) to the antenna 20, and receives a 2.14 GHz WCDMA reception signal received from the antenna 20. It has a function of transmitting Rx to the low noise amplifier 24 (one form of communication means for reception), and for example, a signal is branched for each frequency using a trap filter. In the embodiment shown in FIG. 1, the antenna 20 is used as a communication port for transmitting and receiving signals. However, the communication port is not limited to the antenna 20. A communication port can be used.

  FIG. 2 shows a configuration example of the semiconductor switch circuit SW1 according to the embodiment of the present invention.

  The RF0 terminal of the semiconductor switch circuit SW1 shown in FIG. 2 is connected to the antenna 20 as shown in FIG. The RF1 terminal is connected to the duplexer 22.

  In the example shown in FIG. 2, a semiconductor switch circuit 111 that functions as a through FET and a semiconductor that functions as a shunt FET in order to cut off a signal having a large amplitude and reduce the capacitance existing between the drain D and the source S. The switch circuit 101 is composed of FETs connected in a plurality of stages (four stages) in series. Further, the gates G of the FETs 5 to 8 constituting the semiconductor switch circuit 111 are connected in common via a resistor Rg to constitute the gate of the semiconductor switch circuit 111. Further, the gates G of the FET1 to FET4 constituting the semiconductor switch circuit 101 are connected in common via a resistor Rg to constitute the gate of the semiconductor switch circuit 101.

  In the embodiment shown in FIG. 2, among the FETs of a plurality of stages inserted in parallel in the RF (Radio Frequency) signal path, the gate width Wg of one FET 1 is 2 mm, and the gate width Wg of the other FETs 2 to 3. It is narrower than (4 mm). Further, a fixed capacitor Cp is connected between the gate G and the drain D and between the gate G and the source S of the FET 1 having a narrow gate width Wg.

  The reason for configuring the FET 1 in this way will be described with reference to FIGS. The fixed-capacitance capacitor Cp may be configured with an MIM capacitor (Metal-Insulator-Metal Capacitor) or the like.

  FIG. 3 is a diagram illustrating IMD power generated when the semiconductor switch circuit 101 is set to a high impedance state. FIG. 3 shows the relationship between the gate width Wg (mm) of all the FETs 1 to 4 constituting the semiconductor switch circuit and the IMD power generated by the presence of the semiconductor switch circuit 101.

  As shown in FIG. 3, when the gate width Wg of all the FETs 1 to 4 is narrowed, harmonic distortion and IMD generation tend to decrease, so malfunctions in the receiving circuit that receives the RF signal tend to decrease. . However, if the gate width Wg is reduced for all of the FETs 1 to 4, the on-resistance of the semiconductor switch circuit 101 increases, so that the RF signal is cut off and isolation with other receiving circuits is deteriorated. This causes a malfunction. Next, the relationship between the gate width Wg (mm) of all the FETs 1 to 4 constituting the semiconductor switch circuit 101 and the on-resistance Ron (Ω) of the semiconductor switch circuit 101 will be described with reference to FIG.

  4, the horizontal axis represents the gate width Wg (mm) of all the FETs 1 to 4 constituting the semiconductor switch circuit 101, the vertical axis represents the ON resistance Ron of the semiconductor switch circuit 101, and the gate width Wg (mm) FIG. 3 is a diagram showing a relationship with an on-resistance Ron (Ω) of a semiconductor switch circuit 101.

  As shown in FIG. 4, the on-resistance Ron of the semiconductor switch circuit 101 increases substantially in inverse proportion to the gate width Wg (mm) of all the FETs 1 to 4. Therefore, when the gate width is set narrow for the purpose of reducing harmonic distortion and IMD generated when the semiconductor switch circuit 101 is set to the high impedance state, the on-resistance increases, and the semiconductor switch circuit 101 is set to the low impedance state. This causes problems such as poor isolation.

  Therefore, in the semiconductor switch circuit according to the embodiment of the present invention, by setting the gate width Wg of some of the FETs 1-4 connected in series to be narrower than the gate width Wg of other FETs. , The increase in on-resistance Ron is kept low. Further, by connecting a fixed capacitor Cp between the gate G and the drain D and between the gate G and the source S of the FET whose gate width Wg is set narrow, generation of harmonic distortion or IMD is reduced. Yes.

  Here, an equivalent circuit of a semiconductor switch circuit in which the gate width Wg of some of the FETs 1-4 connected in series is set to be narrower than the gate width Wg of other FETs will be described with reference to FIG. To do.

  FIG. 5 is a diagram showing an equivalent circuit in a high impedance state when the gate width Wg of the FET 1 is set to 2 mm and the gate widths of the other FETs 2 to 4 are set to 4 mm in the semiconductor switch circuit 101 shown in FIG. is there.

  As shown in FIG. 5, a capacitance t × Cds having no voltage dependency exists between the drain D and the source S of the FET 1 set in the high impedance state, and the voltage between the drain D and the source S of the FETs 2 to 4 is present. There is a capacitance Cds without dependency. Note that t is a constant obtained by dividing the gate width Wg of the FET 1 by the gate width Wg of the FETs 2 to 3. For example, if the gate width Wg of the FET 1 is 2 mm and the gate width Wg of the FETs 2 to 3 is 4 mm, the value of t is t = 0.5.

  Further, a parasitic capacitance t × Cg having voltage dependency exists between the gate G and the drain D and between the gate G and the source S of the FET 1. Similarly, a parasitic capacitance Cg having voltage dependency exists between the gate G and the drain D and between the gate G and the source S of the FETs 2 to 4.

  As shown in FIG. 5, when each FET is set to a high impedance state, the cutoff capacitance is a parasitic capacitance Cg having a voltage dependency between the gate G and the source S or between the gate G and the drain D, and the drain D−. This is a combined capacitance in which a capacitor Cds having no voltage dependency between the sources S is connected in parallel.

  As shown in FIG. 5, in the case where the combined capacitance is different between FET1 and FET2-4, when a high frequency RF signal is applied to both ends of the semiconductor switch circuit 101, vcg1 is applied to both ends of the parasitic capacitance t × Cg. The voltage vcg2 is generated at both ends of the parasitic capacitance Cg. Here, from the relationship of t <1, vcg1 and vcg2 have a relationship of vcg1> vcg2.

  Here, the voltage amplitude applied between the drain D− of the FET1 of the semiconductor switch circuit 101 and the source S of the FET4 is Vrf (V), and the voltage amplitude divided by the parasitic capacitance t × Cg of the FET1 is vcg1 (V ) If the voltage amplitude divided by the parasitic capacitances Cg of the FETs 2 to 4 is vcg2 (V), vcg1 and vcg2 can be expressed by the following equations.

但し、ｔ＝（ＦＥＴ１のゲート幅Ｗｇ）／（ＦＥＴ２〜４のゲート幅Ｗｇ）
なお、上記の各式におけるＣｇ（Ｖ）は、寄生容量Ｃｇの両端に印加される電圧によって静電容量が変化すること（電圧依存性）を表している。

However, t = (Gate width Wg of FET1) / (Gate width Wg of FET2-4)
In addition, Cg (V) in each of the above formulas represents that the capacitance changes (voltage dependency) depending on the voltage applied to both ends of the parasitic capacitance Cg.

  For the purpose of reducing harmonic distortion and IMD, if the gate width of the semiconductor switch circuit 101 is narrowed (that is, t is made smaller than 1), the capacitance change amount ΔCg of the parasitic capacitance Cg of the FET 1 with respect to the voltage amplitude is reduced. Can be expected to reduce harmonic distortion and IMD. However, as the parasitic capacitance t × Cg of the FET 1 decreases, the impedance of the parasitic capacitance t × Cg increases, and the voltage amplitude vcg1 divided across the parasitic capacitance t × Cg also increases.

  The relationship between the gate width Wg of the FET and the capacitance change amount ΔCg of the parasitic capacitance Cg will be described with reference to FIG.

  FIG. 6 is a diagram showing the relationship between the voltage amplitude vcg (horizontal axis) divided across the parasitic capacitance Cg (vertical axis) and the capacitance change amount ΔCg.

  In the example shown in FIG. 6, the change of the parasitic capacitance Cg when the gate width Wg = 4 mm and the parasitic capacitance t × Cg when the gate width Wg = 2 mm is shown.

  As shown in FIG. 6, the parasitic capacitance t × Cg when the gate width Wg = 2 mm is a half value of the parasitic capacitance Cg when the gate width Wg = 4 mm in accordance with the scaling rule of the gate width Wg. Therefore, if the voltage amplitude divided across the parasitic capacitance is the same, the capacitance change amount ΔCg when the gate width Wg = 2 mm is about half of the capacitance change amount ΔCg when the gate width Wg = 4 mm. It becomes.

  However, since the voltage amplitude divided at both ends of the parasitic capacitance Cg has a relationship of vcg1> vcg2 as described above, the capacitance change amount ΔCg when the gate width Wg = 2 mm does not decrease so much, and harmonic distortion and IMD cannot be reduced.

  Therefore, in the embodiment of the present invention, as shown in FIG. 5, the gate width Wg of some of the FETs 1 of the plurality of FETs constituting the semiconductor switch circuit 101 is set to be greater than the gate widths Wg of the other FETs 2 to 4. Also, the parasitic capacitance Cg is reduced by setting it to be narrow, and the fixed capacitor Cp is connected between the gate G and the drain D and between the gate G and the source S of the FET 1 whose gate width Wg is set to be narrow. Since the impedance is reduced by connecting the capacitor Cp, the voltage amplitude vcg1 divided across the parasitic capacitance Cg is reduced.

  A capacitance change ΔCg when a fixed capacitor Cp is connected between the gate G and the drain D and between the gate G and the source S of the FET 1 having a narrow gate width will be described with reference to FIG.

  FIG. 7 is a diagram showing the relationship between the voltage amplitude vcg (horizontal axis) divided across the parasitic capacitance Cg (vertical axis) and the capacitance change amount ΔCg.

  As shown in FIG. 7, when a fixed capacitor Cp is connected to the parasitic capacitance t × Cg of the FET 1 having a gate width Wg = 2 mm, the impedance of the combined capacitance t × Cg + Cp decreases, and both ends of the combined capacitance t × Cg + Cp. The voltage amplitude vcg1 that is divided into two decreases. Here, when the capacitance of the capacitor Cp is adjusted such that vcg1 and vcg2 are substantially equal, the capacitance change amount ΔCg of the combined capacitance t × Cg + Cp in the FET1 decreases. Therefore, it is possible to reduce harmonic distortion and IMD generated when the semiconductor switch circuit 101 is set to the high impedance state while suppressing an increase in the on-resistance Ron when the semiconductor switch circuit 101 is set to the low impedance state.

  Here, the capacitance of the capacitor Cp is defined as the gate-source capacitance or gate-drain capacitance t × Cg of the FET having a narrow gate width and the gate-source capacitance or the gate-drain capacitance of the other FET. The difference capacity is good. Further, as the capacitance of the capacitor Cp, a value proportional to Cg × (1-t) can be used. As shown in the above (Expression 1) and (Expression 2), t = (narrow gate width Wg) / (wide gate width Wg). Therefore, the capacitance of the capacitor Cp is expressed by using the difference in gate width. , Cg × ((wide gate width Wg) − (narrow gate width Wg)) can be used.

  In the above description, the gate width Wg of a part of the FETs in the plurality of stages is set to be narrower than the gate width Wg of the other FETs, and between the gate G and the drain D of the FET having the gate width Wg set to be narrow, In the embodiment, the semiconductor switch circuit in which the fixed capacitor Cp is connected between the gate G and the source S is applied to the shunt FET that is inserted in parallel to the signal path to control the short circuit and the open circuit of the signal path. However, the semiconductor switch circuit according to the present invention can also be applied to a through FET (for example, the semiconductor switch circuit 111 shown in FIG. 2). By using the semiconductor switch circuit according to the present invention for the through FET, it is possible to reduce harmonic distortion and IMD generated in the high impedance state while suppressing an increase in the on-resistance Ron in the low impedance state.

  Of the FETs used in the semiconductor switch circuit, the number of FETs that reduce the gate width Wg is not limited to one. Further, as the FET, a junction type field effect transistor (JFET), a high electron mobility transistor HEMT (Hi Electron Mobility Transistor), or the like can be used.

  Next, another embodiment of the semiconductor switch circuit according to the present invention is shown in FIG.

  FIG. 8 shows the gate G-drain of FETs in which the gate width Wg of some of the FETs connected in series is set narrower than the gate width Wg of other FETs and the gate width Wg is set narrower. FIG. 4 is a diagram showing an embodiment in which a fixed capacitor Cp is connected between D and between a gate G and a source S, and a resistor Ra is connected in parallel between the drain D and the source S of each FET.

  If a resistor Ra is connected in parallel between the drain D and source S of each FET in a semiconductor switch circuit in which FETs are connected in series, the drain D of the semiconductor switch circuit is set when the semiconductor switch circuit is set to a high impedance state. -It is known that the distortion generated between the sources S is reduced.

  As shown in FIG. 8, also in the semiconductor switch circuit 201 in which the resistor Ra is connected in parallel between the drain D and the source S of each FET, the gate width Wg of some of the FETs 1 constituting the semiconductor switch circuit 201 is set to other values. By connecting a fixed capacitor Cp between the gate G and the drain D and between the gate G and the source S of the FET 1 which is set narrower than the gate width Wg of the FETs 2 to 4 and the gate width Wg is narrowed, The distortion generated between the drain D and the source S of the semiconductor switch circuit 201 can be reduced.

It is a block diagram of a transmission / reception part of a mobile phone capable of switching a plurality of radio wave bands. It is a figure which shows the structural example of the semiconductor switch circuit which concerns on embodiment of this invention. It is a figure showing the power of IMD generated when a semiconductor switch circuit is made into a high impedance state. It is a figure showing the value of on-resistance Ron when a semiconductor switch circuit is made into a low impedance state. It is a figure which shows the equivalent circuit in a high impedance state at the time of setting the gate width Wg of FET1 to 2 mm, and setting the gate width of other FET2-4 to 4 mm. It is a figure which shows the relationship between voltage amplitude vcg divided by the both ends of the parasitic capacitance Cg, and capacitance variation | change_quantity (DELTA) Cg. It is a figure which shows the relationship between voltage amplitude vcg divided by the both ends of the parasitic capacitance Cg, and capacitance variation | change_quantity (DELTA) Cg. It is a figure which shows embodiment which connected resistance Ra between the drain D-source S of each FET which comprises a semiconductor switch circuit in parallel. It is a figure which shows the circuit diagram of a general FET, and the equivalent circuit in the operating state of the FET.

Explanation of symbols

20 Antenna 22 Duplexer 24 Low Noise Amplifier 26 Power Amplifier 101, 102, 103, 104 Semiconductor Switch Circuit 111, 112, 113, 114 Semiconductor Switch Circuit 201 Semiconductor Switch Circuit 211 Semiconductor Switch Circuit Cp Capacitor Cds Capacitance Cg Parasitic Capacitance ΔCg Capacitance Change Tx Transmission signal Rx Reception signal Ron ON resistance SW1, SW2, SW3 Semiconductor switch circuit Wg Gate width

Claims (5)

In a semiconductor switch circuit that controls conduction and interruption of signals,
The semiconductor switch circuit is composed of a plurality of stages of field effect transistors connected in series,
The gate width of some of the field effect transistors among the plurality of field effect transistors is set to be narrower than the gate width of other field effect transistors, and the gate of the field effect transistor having a narrow gate width − A semiconductor switch circuit in which a fixed capacitor is connected between the drain and gate-source.   The capacitance of the capacitor includes a capacitance between a gate and a source or a gate and a drain of a field effect transistor having a narrow gate width, and a capacitance between a gate and a source or a gate and a drain of the other field effect transistor. The semiconductor switch circuit according to claim 1, wherein the capacitance is a difference between the first and second capacitors. A communication device that transmits or receives signals with other communication devices,
A communication means for transmitting or receiving the signal;
A communication port for transmitting or receiving the signal to the other communication device;
A semiconductor switch circuit disposed between the communication means and the communication port and controlling passage and blocking of the signal;
The semiconductor switch circuit is composed of a plurality of stages of field effect transistors connected in series, and the gate width of some of the field effect transistors of the plurality of stages of field effect transistors is set to that of other field effect transistors. A communication device using a semiconductor switch circuit in which a fixed-capacitance capacitor is connected between a gate and a drain and between a gate and a source of a field effect transistor which is set to be narrower than a gate width. A through field effect transistor that is inserted in series with respect to the signal path to control the conduction and interruption of the signal, and a signal conduction and In a semiconductor switch circuit having a shunt field effect transistor for controlling the cutoff,
The semiconductor switch circuit is composed of a plurality of stages of shunt field effect transistors connected in series,
A shunt field-effect transistor in which the gate width of some of the shunt field-effect transistors among the plurality of stages of shunt field-effect transistors is set narrower than that of other shunt field-effect transistors and the gate width is set narrower A semiconductor switch circuit in which a fixed capacitor is connected between the gate and drain of a transistor and between the gate and source.   The capacitance of the capacitor includes a gate-source capacitance or a gate-drain capacitance of a shunt field effect transistor having a narrow gate width, and a gate-source or gate-drain capacitance of the other shunt field effect transistor. The semiconductor switch circuit according to claim 4, wherein the capacitance is a difference between the capacitance and the capacitance.

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