JP2008010499A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a protective circuit for protecting an internal circuit against static electricity input to an input/output terminal connected with the internal circuit, which can improve electrostatic resistance of the protective circuit with a simple structure. <P>SOLUTION: The semiconductor integrated circuit has the protective circuit (113) for protecting the internal circuit (111) against static electricity input to the input/output terminal (T11) connected with the internal circuit (111). The protective circuit (113) is constituted of a transistor (TR11) whose drain-source is connected between the input/output terminal (T11) and a ground terminal (T13), and whose gate and back gate are connected with a source. Impedance (R11) is provided between the drain of the transistor (TR11) and the back gate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a protection circuit that protects an internal circuit from static electricity input to an input / output terminal connected to the internal circuit.

  In a semiconductor integrated circuit, each input / output terminal is provided with a protection circuit that protects an internal circuit by static electricity from the input / output terminal (see, for example, Patent Document 1).

  Conventionally, as this type of protection circuit, a protection circuit using a field effect transistor (referred to as a transistor system) and a protection circuit using a diode (a diode system) are used. At this time, in a semiconductor integrated circuit manufactured by a MOS process, it is difficult to form a diode having a large electrostatic resistance, and a transistor type protection circuit is generally mounted.

  FIG. 8 is a block diagram showing an example of a conventional transistor type protection circuit.

Terminal T11 is an input / output terminal, and terminal T13 is a ground terminal. Terminals T11 and T13 are connected to the internal circuit 11. The protection circuit 12 is composed of an n-channel MOS field effect transistor, and has a drain-source connected between the terminal T11 and the terminal T13 and a gate connected to the terminal T13. When an electrostatic surge is input to the terminal T11, the protection circuit 12 is turned on to release the electrostatic surge to the terminal T13 that is a ground terminal. This prevents the electrostatic surge from being input to the internal circuit 11 and protects the internal circuit 11 from the electrostatic surge.
JP 2003-249625 A

  However, in recent years, the electrostatic resistance of electrostatic protection elements has been reduced due to miniaturization of processes, making it difficult to meet the standards. For this reason, it is required to improve the electrostatic resistance of the electrostatic protection element in as small a space as possible.

  The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor integrated circuit capable of improving the electrostatic resistance of a protection circuit with a simple configuration.

  The present invention relates to a protection circuit (112) in a semiconductor integrated circuit having a protection circuit (113) for protecting the internal circuit (111) from static electricity inputted to an input / output terminal (T11) connected to the internal circuit (111). Has a drain-source connected between the input / output terminal (T11) and the ground terminal (T13), a gate and a back gate connected to the source, and an impedance between the drain and back gate of the transistor. (R11) is provided.

  The impedance (R11) is set according to the distance (L) between the drain region (123) of the transistor (TR11) and the back gate electrode region (124). The impedance is set according to the area of the region where the drain region (123) of the transistor (Tr11) and the back gate electrode region (124) are in contact with each other.

  The back gate electrode region (124) is arranged to surround the protection circuit (113, 200, 300).

  The protection circuit (112) is characterized in that a plurality of transistors are arranged in parallel.

  In addition, the said reference code is a reference to the last, and description of a claim is not limited by this.

  According to the present invention, the protection circuit includes a transistor having a drain-source connected between the input / output terminal (T11) and the ground terminal (T13), and a gate and a back gate connected to the source. By providing an impedance between the back gate and the back gate, electrostatic surge energy can be absorbed by the set impedance, thereby improving electrostatic resistance.

  FIG. 1 is a plan view of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a semiconductor device according to the present invention.

  The semiconductor integrated circuit 100 according to this embodiment includes an internal circuit 111 on a p-type semiconductor substrate 101 and a protection circuit 113 that protects the internal circuit 111 from static electricity input to an input / output terminal T11 connected to the internal circuit 111. It is assumed that the configuration is installed.

  The internal circuit 111 is driven by a power supply voltage Vdd applied between power supply terminals (not shown), and exchanges signals with external circuits via the input / output terminal T11.

  FIG. 3 shows a configuration diagram of the protection circuit 113.

  The protection circuit 113 includes a MOS field effect transistor TR11 having a drain-source connected between the input / output terminal T11 and the ground terminal T13, and a gate and a back gate connected to the source. Between the gate, there is a resistor R11 which is an impedance. The protection circuit 113 forms a p-type well region 121 on the p-type semiconductor substrate 101, and further, a high-concentration n-type source region 122, an n-type drain region 123, and a high-concentration p-type back gate on the p-type well region 121. An electrode region 124 is formed, and a gate electrode 126 is wired between the source region 122 and the drain region 123 through a gate oxide film 125. In the n-type drain region 123, a high-concentration n-type drain electrode region 129 is further formed.

  The high concentration p-type back gate electrode region 124 is formed so as to surround the entire circumference around the protection circuit 113. The n-type drain region 123 is formed on the inner peripheral side of the high-concentration p-type back gate electrode region 124 so that the distance from the high-concentration p-type back gate electrode region 124 is at least L. As a result, a resistor R11, which is an impedance, is formed between the n-type drain region 123 and the high-concentration p-type back gate electrode region 124.

  The resistance R11 is substantially determined by the distance L between the n-type drain region 123 and the high-concentration p-type back gate electrode region 124. By providing the resistor R11, the energy of the electrostatic surge can be absorbed by the resistor R11, thereby improving the electrostatic resistance.

  The high concentration p-type back gate electrode region 124 is connected to the back gate electrode 130 through a contact hole 128 formed in the oxidation protection film 127. The back gate electrode 130 is connected to the ground terminal T13.

  FIG. 4 is a characteristic diagram of current with respect to the voltage applied to the terminal T11, and FIG. 5 is a diagram illustrating characteristics of electrostatic resistance with respect to the resistor R11.

  As shown in FIG. 4, when the voltage applied to the terminal T11 increases, the current flowing into the terminal T11 increases. When the applied voltage becomes the breakdown voltage Vbd, the transistor TR11 of the protection circuit 113 is turned on. When the transistor TR11 is turned on, the applied voltage is reduced to the snapback voltage Vsb. In the snapback state, the parasitic transistor TR12 is turned on to suppress the increase in the voltage applied to the terminal T11.

  Thus, by increasing the resistance R11 in proportion to the distance L between the n-type drain region 123 and the high-concentration p-type back gate electrode region 124, the electrostatic surge energy consumed by the resistor R11 is increased. The load applied between the n-type drain region 123 and the high-concentration p-type back gate electrode region 124 can be reduced below the breakdown energy. That is, the electrostatic resistance of the transistor TR11 can be improved.

  Further, the base potential of the parasitic transistor TR12 increases due to the increase in the resistance R11. As the base potential of the parasitic transistor TR12 increases, the parasitic transistor TR12 is easily turned on, and the transition to the snapback state is facilitated. By shifting to the snapback state, electrostatic surge can be absorbed through the parasitic transistor TR12, so that the electrostatic resistance of the transistor TR11 can be improved.

  As described above, by increasing the resistance R11, it is possible to improve the electrostatic resistance as shown in FIG. 5, and thereby the protection of the internal circuit 111 can be enhanced. FIG. 5 shows the electrostatic resistance when the distance L between the n-type drain region 123 and the high-concentration p-type back gate electrode region 124 is changed from 5 μm to 25 μm.

  Furthermore, according to the present embodiment, the electrostatic resistance of the transistor TR11 can be improved only by changing the pattern so that the distance L between the high-concentration p-type back gate electrode region 124 and the n-type drain region 123 can be increased. Therefore, the electrostatic resistance of the transistor TR11 can be easily improved without changing the process.

  In this embodiment, the resistance R11 is increased by increasing the distance L between the n-type drain region 123 and the high-concentration p-type back gate electrode region 124. However, the resistance R11 can be increased. For example, it is not limited to this.

  FIG. 6 shows a configuration diagram of a modified example of the protection circuit 113. In the figure, the same components as those in FIG.

  In the protection circuit 200 of this modification, the contact hole 128 for connecting the high-concentration p-type back gate electrode region 124 to the back gate electrode 130 has a large pitch at a position close to the n-type drain region 123, that is, (d3 > D2> d1).

  As a result, the resistance R11 between the n-type drain region 123 and the high-concentration p-type back gate electrode region 124 can be increased.

  As a result, the same effects as the protection circuit 113 are obtained. In addition, according to this modification, since the pitch of the contact holes 128 is only changed so as to satisfy (d3> d2> d1), the electrostatic breakdown voltage can be improved with the same shape as the conventional one. That is, the protection circuit 200 can improve the electrostatic withstand voltage without taking a large size.

  FIG. 7 shows a configuration diagram of another modification of the protection circuit 113. In the figure, the same components as those in FIG.

  The protection circuit 300 of this modification is configured such that the low concentration region 311 is intermittently formed in the p type well region 121 between the n type drain region 123 and the high concentration p type back gate electrode region 124. .

  The low concentration region 311 is formed by the formation pattern of the p-type well region 121. By providing the low concentration region 311, the resistance R11 between the n-type drain region 123 and the high concentration p-type back gate electrode region 124 can be increased.

  Further, in order to increase the resistance R11 between the n-type drain region 123 and the high-concentration p-type back gate electrode region 124, the impurity concentration between the n-type drain region 123 and the high-concentration p-type back gate electrode region 124 is reduced. It may be lowered. In short, it is sufficient that the resistance R11 between the n-type drain region 123 and the high-concentration p-type back gate electrode region 124 can be increased.

  Moreover, although the said Example demonstrated the example which applied this invention to the LOCOS, ie, the high voltage | pressure-resistant type field effect transistor which has the oxidation protective film 127, it can be applied also to the normal field effect transistor which does not have LOCOS. Needless to say.

  In addition, this invention is not limited to the said Example, It cannot be overemphasized that a various modified example can be considered in the range which does not deviate from the summary of this invention.

It is a top view of the semiconductor integrated circuit of this invention. It is a block block diagram of the semiconductor integrated circuit of this invention. 2 is a configuration diagram of a protection circuit 113. FIG. 6 is a characteristic diagram of current with respect to an applied voltage at terminal T11. It is a figure which shows the characteristic of the electrostatic tolerance with respect to resistance R11. 10 is a configuration diagram of a modified example of the protection circuit 113. FIG. FIG. 10 is a configuration diagram of another modification of the protection circuit 113. It is a block block diagram of an example of the conventional transistor type protection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor integrated circuit 101 Semiconductor substrate, 112 Internal circuit, 113, 200, 300 Protection circuit 121 Well region, 122 Source region, 123 Drain region 124 Back gate electrode region, 125 Gate oxide film, 126 Gate electrode 127 Oxidation protection film, 128 Contact hole 311 Low concentration region

Claims (5)

In a semiconductor integrated circuit having a protection circuit for protecting the internal circuit from static electricity input to an input / output terminal connected to the internal circuit,
The protection circuit includes a transistor having a drain-source connected between the input / output terminal and a ground terminal, and a gate and a back gate connected to the source,
A semiconductor integrated circuit, wherein an impedance is provided between the drain and the back gate of the transistor.
2. The integrated circuit according to claim 1, wherein the impedance is set according to a distance between a drain region and a back gate electrode region of the transistor. 2. The semiconductor integrated circuit according to claim 1, wherein the impedance is set according to an area of a region where a drain region and a back gate electrode region of the transistor are in contact with each other. 4. The semiconductor integrated circuit according to claim 2, wherein the back gate electrode region is arranged so as to surround the periphery of the protection circuit. 5. The semiconductor integrated circuit according to claim 1, wherein the protection circuit has a configuration in which a plurality of the transistors are arranged in parallel.

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