JP2008097774A - Shift register, electro-optical device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a unit circuit which constitutes a shift register, by reduced number of elements. <P>SOLUTION: The shift register is arranged such that a plurality of unit circuits 150 are cascaded. Each of unit circuits 150 includes TFTs 151-154, the source electrode of the TFT 151 is connected to a clock signal branch line 145 which supplies one side of complementary clock signals, and the gate electrode of the TFT 152 is connected to a clock signal branch line 146 which supplies another one of the complementary clock signals. The source electrode of this TFT 152 is grounded to a potential Gnd, and drain electrodes of the TFTs 151, 152 are connected to an output end Out. The TFT 153 is turned on when a shift signal Y(i-1) from the unit circuit of one stage before becomes an H level, and the TFT 154 is arranged to be turned on when a shift signal Y(i+1) from the unit circuit of one stage after becomes H level. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for simplifying the configuration of a shift register that sequentially transfers pulses.

In an electro-optical device such as a liquid crystal, pixels are provided corresponding to intersections of a plurality of scanning lines and a plurality of columns of data lines. When the scanning line corresponding to the pixel is selected and becomes active level, the pixel has a gradation corresponding to the voltage or current of the data line corresponding to the pixel. Even when the level is reached, the gradation is maintained. Accordingly, a plurality of scanning lines are selected in a predetermined order, and the selected scanning line is set to an active level, while a voltage or current corresponding to the gradation is applied to the pixel located on the selected scanning line. By supplying through a line, the target image can be displayed.

By the way, selecting a plurality of scanning lines in a predetermined order and bringing the selected scanning lines to an active level is called a scanning line driving circuit to which a shift register is applied. The so-called peripheral circuit built-in type configured with the same switching element as the pixel is more advantageous in terms of manufacturing efficiency than mounting with an external integrated circuit.
On the other hand, in recent years, as typified by mobile phones, display with a small size and high definition is desired. A small and high-definition display increases the number of pixels per unit area, which inevitably reduces the pitch (interval) of scanning lines and data lines. In a scanning line driving circuit, the number of constituent elements per row Is required to be reduced.
Although the main purpose is to improve the reliability and life, the number of constituent elements (transistors) per row is only nine, and a technique that can reduce the number of constituent elements in a secondary manner has been proposed. (See Patent Document 1).
Japanese Patent Laid-Open No. 2004-103226 (especially refer to FIG. 7)

However, the demand for miniaturization of the display device and high-definition display is not known, and the scanning line driving circuit is required to further simplify the configuration.
The present invention has been made in view of such circumstances, and an object thereof is to provide a technique capable of simplifying a circuit configuration.

In order to achieve the above object, a shift register according to the present invention cascades a plurality of unit circuits and outputs a shift signal that becomes an active level exclusively and sequentially from the output terminals of the unit circuits of each stage. The unit circuit of each stage includes a first and a second transistor, a set switch, and a reset switch. In the unit circuit of each stage, the source electrode of the first transistor is a pair of Connected to one of the clock signal branch lines for supplying a complementary clock signal, the gate electrode of the second transistor is connected to the other of the clock signal branch lines, and the source electrode serves as a power supply line for supplying one of the logic levels. The first switch and the drain electrode of the second transistor are connected to the output terminal; The first transistor is turned on by turning on when the shift signal from the unit circuit of the previous stage becomes the active level. The voltage to be applied is applied to the gate electrode of the first transistor, and the reset switch is turned on when the shift signal by the unit circuit at the next stage becomes an active level, thereby turning off the first transistor. A voltage is applied to the gate electrode of the first transistor, and in the odd-numbered unit circuit, one of the pair of complementary clock signals is supplied to one of the clock signal branch lines, and the other of the complementary clock signals is In the even-numbered unit circuit, one of the complementary clock signals is supplied to the other of the complementary clock signal branch lines. Is supplied to the person,
The other of the complementary clock signals is supplied to one of the clock signal branch lines. According to this configuration, since the elements constituting the unit circuit are the first and second transistors, the set switch, and the reset switch, the circuit configuration can be simplified.

In the shift register according to the present invention, an auxiliary capacitor may be interposed between the gate and drain electrodes of the first transistor. According to this configuration, the change in the gate electrode potential of the first transistor is suppressed as the one logic level of the clock signal branch line changes.
In addition, the output terminal of the unit circuit is set to the non-active level for a part or all of the period in which one of the clock signal branch lines is in the active level during the period in which the shift signal from the unit circuit is not in the active level. It is also possible to have a structure having a holding circuit for holding the signal. Thereby, the voltage change when the output terminal is in a high impedance state is suppressed.
In the set switch, the gate electrode and the source electrode are connected, a shift signal from the unit circuit of the previous stage is supplied to the connection point, and the drain electrode is connected to the gate electrode of the first transistor. A third transistor connected to the reset switch; the gate electrode is supplied with a shift signal from the unit circuit of the next stage; the source electrode is connected to a power supply line that supplies one of the logic levels; The drain electrode may be a fourth transistor connected to the gate electrode of the first transistor.
In this configuration, in accordance with the transfer direction of the shift signal, a shift signal from the unit circuit of the previous stage is supplied to the connection point of the source electrode and the gate electrode of the third transistor, and the fourth transistor If the gate electrode has a selector that supplies a shift signal from the unit circuit at the next stage, transfer can be performed in one direction or the other in cascade connection.
The present invention can be conceptualized not only as a shift register but also as an electro-optical device or as an electronic apparatus having the electro-optical device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the entire electro-optical device to which the shift register according to the embodiment is applied will be described. FIG. 1 is a block diagram showing the configuration of the electro-optical device.
As shown in this figure, the electro-optical device 10 has a display area 100, and a control circuit 20, a scanning line driving circuit 140, and a data line driving circuit 190 are arranged around the display area 100. ing. Among these, the display area 100 is an area in which the pixels 110 are arranged. In the present embodiment, 320 scanning lines 112 extend in the row (X) direction, and 240
The column data lines 114 are respectively provided so as to extend in the column (Y) direction, and among these, at each intersection between the scanning lines 112 in the 1st to 320th rows and the data lines 114 in the 1st to 240th columns. Correspondingly, a pixel 110 is provided. Therefore, in this embodiment, the pixel 1
10 are arranged in a matrix of 320 rows × 240 columns in the display area 100, but the present invention is not limited to this arrangement.

Here, for convenience of description, the configuration of the pixel 110 will be described. FIG. 2 is a diagram illustrating the configuration of the pixel 110, i rows and (i + 1) rows adjacent thereto, j columns and adjacent thereto (
The configuration of a total of 4 pixels of 2 × 2 corresponding to the intersection with the j + 1) column is shown.
In the description of this figure, i and (i + 1) are symbols for generally indicating two consecutive rows among the rows in which the pixels 110 are arranged without specifying the rows, 3, ...
320. On the other hand, j and (j + 1) are symbols for generally indicating two consecutive columns out of the columns in which the pixels 110 are arranged without specifying a column, and are 1, 2, 3,.
It is.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (thin fil
m transistor: hereinafter simply abbreviated as “TFT”) 116 and pixel capacitance (liquid crystal capacitance) 120
And a storage capacitor 130. Since each pixel 110 has the same configuration, a description will be given by representatively assuming that it is located in i row and j column.
The gate electrode 116 is connected to the scanning line 112 in the i-th row, the source electrode is connected to the data line 114 in the j-th column, and the drain electrode is the pixel electrode 1 that is one end of the pixel capacitor 120.
18 and one end of the storage capacitor 130.
The other end of the pixel capacitor 120 is a common electrode 108. The common electrode 108 is common to all the pixels 110 as shown in FIG. 1, and is maintained at a constant voltage LCcom with respect to time in this embodiment.
On the other hand, the other end of the storage capacitor 130 is a capacitor line 132. Although not shown in FIG. 1, the capacitor line 132 is maintained at the same voltage LCcom as the common electrode 108, for example.
The capacitor line 132 may be configured to be maintained at a voltage other than the voltage LCcom.

In the display region 100, a pair of substrates, an element substrate on which the pixel electrode 118 is formed and a counter substrate on which the common electrode 108 is formed, are bonded to each other with a certain gap so that the electrode formation surfaces face each other. The liquid crystal 105 is sealed in the gap. For this reason, the pixel capacitor 120 has a structure in which the liquid crystal 105 which is a kind of dielectric is sandwiched between the pixel electrode 118 and the common electrode 108 and holds a differential voltage between the pixel electrode 118 and the common electrode 108. ing. In this configuration, the amount of light transmitted through the pixel capacitor 120 changes according to the effective value of the holding voltage. In the present embodiment, for convenience of explanation, if the effective voltage value held in the pixel capacitor 120 is close to zero, the light transmittance is maximized to display white, while the effective voltage value is increased. Assume that it is a normally white mode in which the amount of light decreases and finally the black display with the minimum transmittance is achieved.

Returning to FIG. 1 again, the control circuit 20 outputs various control signals to output the electro-optical device 1.
In addition to controlling each unit at 0, the above-described voltage LCcom is applied to the common electrode 108. In particular, for the scanning line driving circuit 140, in addition to the transfer start pulse Dy, the clock signal Φ is applied to the signal main line 141. The inverted clock signal / Φ is supplied to the signal trunk line 142, respectively. That is, the clock signal Φ and the inverted clock signal / Φ have a complementary relationship in which when one is at the H level, the other is at the L level and when one is at the L level, the other is at the H level. Note that “/” of the inverted clock signal / Φ indicates inversion of “Φ”.

Around the display area 100, peripheral circuits such as a scanning line driving circuit 140 and a data line driving circuit 190 are provided.
Among these, the scanning line driving circuit 140 applies the shift register according to the embodiment, and a scanning signal (shift signal) that sequentially becomes H level exclusively over a period of one frame in accordance with control by the control circuit 20. Y1, Y2, Y3,..., Y320 are each 1
2, 3,..., 320 are supplied to the scanning lines 112.
Note that since the TFT 116 is an n-channel type, when the scanning line 112 is at an H level, the TFT 116 is turned on in each row of pixels 110 corresponding to the scanning line 112. For this reason, in this embodiment, the H level of the scanning signal becomes the active level,
L level becomes non-active level.

FIG. 3 is a block diagram illustrating a configuration of the scanning line driving circuit 140. As shown in this figure, the scanning line driving circuit 140 is a shift register in which 321 stage unit circuits 150, which are “1” more than the number of rows of the scanning lines 112, are cascade-connected.
Here, the i-th unit circuit 150 outputs a shift signal Yi corresponding to its own stage, and the shift signal Y (i−1) by the (i−1) -th unit circuit 150 one stage before. ) And the shift signal Y (i + 1) from the unit circuit 150 in the (i + 1) th stage after the first stage. However, in the first stage unit circuit 150 which is the first stage, there is no unit circuit 150 one stage before that, so the transfer start pulse Dy is supplied from the control circuit 20, and the unit circuit of the 321st stage Reference numeral 150 is only responsible for supplying the shift signal Y321 after one stage to the 320th stage unit circuit 150 corresponding to the scanning line 112 of the last row.

On the other hand, the unit circuit 150 in each stage has a clock signal Φ and its inverted clock signal /
Clock signal branches 145 and 146 are provided to input Φ, and odd numbers (1, 3, 5,...
, 321) For the unit circuit 150 in the stage, the clock signal branch line 145 is the signal trunk line 141.
And the clock signal branch 146 is connected to the signal trunk 142 while the even number (2, 4
, 6,..., 320), the clock signal branch line 145 is connected to the signal trunk line 142, and the clock signal branch line 146 is connected to the signal trunk line 141.
Therefore, in the odd-numbered unit circuit 150 and the even-numbered unit circuit 150, the relationship between the clock signal Φ and the inverted clock signal / Φ to be supplied is switched in the clock signal branch lines 145 and 146.
In the odd-numbered unit circuit 150 and the even-numbered unit circuit 150, the clock signal Φ and the inverted clock signal / Φ supplied to the clock signal branch lines 145 and 146 are interchanged.
The structure is the same.

Therefore, the configuration of the unit circuit 150 will be described with reference to FIG. FIG. 4 is a diagram illustrating a configuration of the odd-numbered i-th unit circuit 150.
As shown in this figure, the unit circuit 150 includes four n-channel TFTs 151 to 15.
It is composed of four. These TFTs 151 to 154 are the TFTs 116 in the pixel 110.
And manufactured by a common process.
First, the source electrode of the TFT 151 (first transistor) is connected to the clock signal branch line 145, while the gate electrode of the TFT 152 (second transistor) is connected to the clock signal branch line 146. On the lower side of the voltage, it is grounded to a potential Gnd corresponding to the L level of the logic level. Further, the connection point between the drain electrodes of the TFTs 151 and 152 becomes the output stage Out of the own stage, and the shift signal Yi is output from the output terminal Out.

On the other hand, the gate electrode of the TFT 153 (set switch, third transistor) is connected to its own source electrode, and this connection point is connected to the output end of the previous (i-1) stage unit circuit. The shift signal Y (i-1) is supplied. The drain electrode of the TFT 153 is connected to the gate electrode of the TFT 151 and the drain electrode of the TFT 154, and this connection point is referred to as a node A for convenience.
The gate electrode of the TFT 154 (reset switch, fourth transistor) is the next (i
The shift signal Y (i + 1) is supplied by being connected to the output terminal of the unit circuit of the (+1) stage. The source electrode of the TFT 154 is grounded to the potential Gnd.

C1 is a parasitic capacitance between the gate and source electrodes of the TFT 151, and C2 is
This is a capacitance parasitic between the gate and drain electrodes of the TFT 151. Also, in FIG.
Although the odd-numbered unit circuits 150 have been described, the even-numbered unit circuits 150 are
As described above or as shown in brackets in FIG.
5 is supplied with the inverted clock signal / Φ and the clock signal branch line 146 is supplied with the clock signal Φ.

In FIG. 1, the data line driving circuit 190 includes data signals X 1, X 2, X with voltages corresponding to the gray levels of the pixels 110 located on the scanning lines 112 that are set to the H level by the scanning line driving circuit 140.
3,..., X240 are supplied to the data lines 114 in the 1, 2, 3,.
Here, the data line driving circuit 190 has storage areas (not shown) corresponding to a matrix arrangement of 320 rows × 240 columns, and each storage area has a gradation value (pixel level) of the corresponding pixel 110 (not shown). Display data Da for designating (brightness) is stored. The display data Da stored in each storage area is rewritten by the display circuit Da after the change together with the address by the control circuit 20 when the display contents are changed.
The data line driving circuit 190 has the scanning line 1 that has been set to the H level by the scanning line driving circuit 140.
The display data Da of the pixel 110 located at 12 is read from the storage area, converted into a voltage data signal corresponding to the gradation value, and supplied to the data line 114. Execute for each of the 1st to 240th columns.

As will be described in detail later, by shifting the transfer start pulse Dy in accordance with the clock signal Φ and the inverted clock signal / Φ, the scanning signals Y1, Y2, Y3, Y4,
Since Y320 is output, the start timing of the period when the logic level of a certain scanning line is H level is the timing at which the logic levels of the clock signal Φ and the inverted clock signal / Φ transition.
For this reason, for example, the data line driving circuit 190 can know the start timing and end timing of a period during which any of the scanning lines is at the H level by detecting the timing. Further, for example, the control circuit 20 resets to zero by the output of the transfer start pulse Dy, and notifies the count value counted up each time the logic level of the clock signal Φ and the inverted clock signal / Φ transitions, thereby causing the data line Drive circuit 190
Can know which scanning line is at the H level.
The voltage corresponding to the gradation value here is the voltage LCco applied to the common electrode 108.
There are two types, positive polarity that is higher than m and negative polarity that is lower, and the data line driving circuit 190 has positive and negative polarity for the same pixel, for example, every one frame period. Switch alternately. Note that the write polarity is based on the voltage LCcom, but the voltage is based on the ground potential Gnd of the power supply unless otherwise specified.

Next, the operation of the electro-optical device 10 according to this embodiment will be described. FIG. 5 is a diagram illustrating vertical scanning in the electro-optical device 10.
As shown in this figure, in the transfer start pulse Dy, the duty ratio of the clock signal Φ and the inverted clock signal / Φ is 50%, and the scanning line of one row is H level 1
This corresponds to the horizontal scanning period (H). The transfer start pulse Dy has a pulse width (H level) corresponding to a half cycle of the clock signal Φ (and inverted clock signal / Φ), and is a timing prior to the start of the frame period, The signal Φ is output over a period during which it becomes L level.
In the scanning line driving circuit 140, the transfer start pulse Dy is shifted by the unit circuit 150 in each stage every time the logic levels of the clock signal Φ and the inverted clock signal / Φ transition, and these shift signals are directly used as the scanning signal. Y1, Y2, Y3,..., Y320 are output. In practice, the shift signal may be output as a scanning signal through a buffer circuit or a level shifter. However, since this is not important in this case, this embodiment is described as a shift signal equal scanning signal.

First, the operation of the electro-optical device will be described. At the beginning of a certain n frame, the scanning signal Y1 becomes H level. When the scanning signal Y1 becomes H level, the data line driving circuit 190
Is the first row and the display data Da of the pixels in the first, second, third,..., 240th columns is read out, and only the voltage specified by the read display data Da is high or low with reference to the voltage LCcom. Converted into voltage, and data signals X1, X2, X3,.
, 240 are supplied to the data lines 114 in 240 columns.
On the other hand, when the scanning signal Y1 becomes the H level, the TF in the pixels in the first row and the first column to the first row and the 240th column is displayed.
Since T116 is turned on, the data signals X1, X2, X3,
..., X240 is applied. For this reason, the pixel capacitance 120 of 1 row 1 column to 1 row 240 column includes
A differential voltage between the data signals X1 to X240 and the voltage LCcom is written.

Next, the scanning signal Y2 becomes H level. When the scanning signal Y2 becomes H level, the data line driving circuit 190 reads the display data Da of the pixels in the second row and the columns 1, 2, 3,. Only the generated voltage is converted into a high or low voltage with reference to the voltage LCcom, and as data signals X1, X2, X3,.
, 240 are supplied to the data lines 114 of 1, 2, 3,.
On the other hand, when the scanning signal Y2 becomes H level, the TF in the pixels of 2 rows 1 column to 2 rows 240 columns
Since T116 is turned on, the data signals X1, X2, X3,
..., X240 is applied. For this reason, the pixel capacitor 120 of 2 rows 1 column to 2 rows 240 columns has
A differential voltage between the data signals X1 to X240 and the voltage LCcom is written.
When the scanning signal Y2 becomes H level, the scanning signal Y1 becomes L level. When the scanning signal Y1 becomes L level, the TFT 116 in the pixels in the first row and first column to the first row and 240th column is turned off, but the voltage written in the pixel capacitor 120 is held in the storage capacitor 130 connected in parallel with the capacitance. Therefore, the pixel capacitors 120 in the 1st row and 1st column to the 1st row and 240th column maintain the gradation corresponding to the written voltage.

In the same manner, voltage writing via the data signal is performed by scanning signals Y3, Y4,.
The process is repeated until 320 becomes the H level, whereby a voltage corresponding to the gradation value is written to all the pixels. Note that, in the next (n + 1) frame, voltage writing is executed in the same manner with the writing polarity reversed. That is, when attention is paid to a certain pixel, if the voltage corresponding to the gradation value is one higher or lower than the voltage LCcom in the n frame, then in the (n + 1) frame, it is higher than the voltage LCcom. The other polarity, high or low. By such polarity reversal, application of a direct current component to the liquid crystal 105 is avoided, and deterioration is prevented.

In FIG. 5, a period Fa is the scanning signal Y1 to Y32 in one frame period.
The effective display period in which the level up to 0 is the H level is shown, and the remaining period is the blanking period, but this blanking period is not necessary.
FIG. 6 is a diagram showing a change in the voltage Pix (i, j) of the pixel electrode 118 in the i row and the j column in relation to the scanning signal Yi. In this figure, when the scanning signal Yi becomes H level, the voltage LCcom is higher or lower than the voltage LCcom by the amount corresponding to the gradation value for the pixel in i row and j column (indicated by ↑ or ↓ in the figure). The data signal Xj is supplied to the data line 114 in the j-th column and written to the pixel electrode 118 in the i-th row and j-th column.

Next, regarding the shift operation in the scanning line driving circuit 140, the odd-numbered i-th unit circuit 15
A description will be given by taking 0 as an example. FIG. 7 shows an i-th unit circuit 15 in the scanning line driving circuit 140.
It is a voltage waveform diagram for explaining the operation of 0.
As described above, the transfer start pulse Dy output over the period when the clock signal Φ is at the L level is transferred by the unit circuit 150 of each stage every time the logic levels of the clock signal Φ and the inverted clock signal / Φ are shifted. Therefore, the period in which the shift signal Yi by the odd-numbered i-th unit circuit 150 is at the H level is a period in which the clock signal Φ is at the H level (the inverted clock signal / Φ is at the L level).
In the odd-numbered i-th stage, the clock signal branch line 145 is connected to the signal trunk line 141, and the clock signal branch line 146 is connected to the signal trunk line 142, so that the clock signal Φ is supplied to the clock signal branch line 145, The inverted clock signal / Φ is supplied to the clock signal branch line 146. Therefore, the shift signal Y (i−1) from the (i−1) th unit circuit 150 one stage before the ith stage and the (i + 1) th stage unit one stage after the ith stage. The period in which the shift signal Y (i + 1) from the circuit 150 is at the H level is a period in which the clock signal branch line 145 is at the L level (the clock signal branch line 146 is at the H level).

In the following, the odd-numbered i-th stage will be described. However, in the even-numbered stage, the clock signal branch line 145 is connected to the signal trunk line 142 and the clock signal branch line 146 is connected to the signal trunk line 141. The clock signal branch line 145 is at the L level (clock signal branch line) during the period when the shift signal from the unit circuit one stage before the even stage and the shift signal from the unit circuit 150 after the first stage are at the H level. 146 becomes H level), which is the same as the odd-numbered stage. Accordingly, if attention is paid to the logic levels of the clock signal branch lines 145 and 146 in the odd-numbered stage and the even-numbered stage, the operation of the unit circuit is exactly the same.

In the odd-numbered i-th stage, the shift signal Y (i−1) is a period in which the clock signal branch lines 145 and 146 are at the L and H levels (the clock signal Φ is at the L level and the inverted clock signal / Φ is at the H level). In the period (a) when) is at the H level, the unit circuit 150 at the i-th stage is as shown in FIG.
More specifically, since the TFT 153 is turned on when the shift signal Y (i−1) becomes the H level, the node A is more than the voltage Vdd corresponding to the H level due to a voltage drop due to the ON resistance of the TFT 153. Although the voltage Va is slightly lower (see FIG. 7), the threshold voltage of the TFT 152 is exceeded. For this reason, the TFT 151 is turned on.
Further, the clock signal branch line 146 becomes H level in accordance with the supply of the inverted clock signal / Φ, so that the TFT 152 is turned on. Since the shift signal Y (i + 1) is at the L level, the TFT 154 is off.
Therefore, the output terminal Out in the i-th unit circuit 150 becomes the level of the clock signal Φ supplied to the clock signal branch line 145 when the TFTs 151 and 152 are turned on.
Since the potential Gnd is grounded, the shift signal Yi is at the L level.
At this time, the source electrode (clock signal branch line 145) of the TFT 151 is L
Since the level of the gate electrode (node A) is the voltage Va, the capacitor Va parasitic between the gate and source electrodes of the TFT 151 is charged with the voltage Va with the gate electrode at the higher side.
In FIG. 8, the thin line indicates the portion at the L level, and the middle thick line indicates the portion at the H level (
(Including the portion where the voltage is Va) (the same applies to FIGS. 9 to 12).

The period (a) is followed by the period (b). In this period (b), the clock signal branch 14
5, 146 become H and L level (clock signal Φ is H level and inverted clock signal / Φ is L level). In the period (b), the i-th stage unit circuit 150 is as shown in FIG.
Specifically, the TFT 153 is turned off when the shift signal Y (i−1) becomes the L level, and the shift signal Y (i + 1) is still at the L level.
Is continuously off from period (a).
For this reason, the node A is in a high impedance state that is not electrically connected to any part, but the clock signal branch line 145 becomes H level with the supply of the clock signal Φ.
The node A becomes a voltage obtained by adding the voltage Va charged to the capacitor C1 to the voltage Vdd corresponding to the H level (see FIG. 7).
Therefore, since the TFT 151 is turned on continuously from the period (a), the output terminal Out in the i-th unit circuit 150 has the same logic level as that of the clock signal Φ supplied to the clock signal branch line 145, thereby The shift signal Yi becomes H level.
Note that the shift signal Yi is at the H level means that the shift signal by the next unit circuit has become an active level when viewed from the unit circuit at the (i-1) stage. For the unit circuit at the (i + 1) th stage, this means that the shift signal by the previous unit circuit has become an active level. Also, in FIG.
A portion where the voltage Va is added to the voltage Vdd corresponding to the H level is shown.

Period (c) follows period (b). In this period (c), the clock signal branch line 145,
146 is L, H level (clock signal Φ is L level, inverted clock signal / Φ is H level)
The i-th stage unit circuit 150 is as shown in FIG.
Specifically, since the shift signal Y (i−1) becomes L level after the period (b), T
The FT 153 is turned off continuously from the period (a), but the TFT 154 is turned on when the shift signal Y (i + 1) becomes the H level. Therefore, the node A is in the on state T
The TFT 151 is turned off because it is grounded to the potential Gnd via the FT154. Also,
As the inverted clock signal / Φ is supplied, the clock signal branch line 146 becomes H level, and the TFT 152 is turned on.
Therefore, the output terminal Out in the i-th unit circuit 150 is turned on.
Since it is grounded to the potential Gnd via 152, the shift signal Yi becomes L level.
Since the clock signal branch line 145 is set to the L level by the supply of the clock signal Φ, the voltage charged in the capacitor C1 parasitic on the TFT 151 is also reset to zero. That is, when the TFT 153 is turned on, the voltage Va is set in the capacitor C1, and when the TFT 154 is turned on, the voltage set in the capacitor C1 is reset to zero.

Next to period (c) is period (d). In this period (d), the clock signal branch 145,
146 is H, L level (clock signal Φ is H level, inverted clock signal / Φ is L level)
Thus, the i-th stage unit circuit 150 is as shown in FIG.
Specifically, since the shift signal Y (i−1) is at the L level after the period (b), T
The FT 153 is turned off continuously from the period (a), and the shift signal Y (i + 1) becomes the L level, so that the TFT 154 is also turned off. For this reason, the node A is in a high impedance state, but if the capacitor C2 is sufficiently larger than the capacitor C1, the node A is maintained in the previous state, that is, the L level state in the period (c). State is maintained.
Further, since the clock signal branch line 146 becomes L level by the supply of the inverted clock signal / Φ, the TFT 152 is also turned off.
Accordingly, the output terminal Out in the i-th unit circuit 150 is also in a high impedance state, but the scanning line 112 connected to the output terminal Out has various capacitances (for example, the capacitance C2 shown in the figure, and others). Since the coupling capacitance between the common electrode 108 and the data line 114 is parasitic, it is maintained at the L level in the immediately preceding state, that is, the period (c), and the potential fluctuation that cannot be overlooked does not occur.

Next to period (d) is period (e). In this period (e), as in the period (c), the clock signal branch lines 145 and 146 become L and H levels (the clock signal Φ is L level and the inverted clock signal / Φ is H level). This is different from the period (c) in that the shift signal by the unit circuit 150 in the second stage is at the L level. In the period (e), the i-th unit circuit 150 is as shown in FIG.
That is, the clock signal branch line 146 becomes H level by the supply of the inverted clock signal / Φ, so that the TFT 152 is turned off. Therefore, the output terminal Out in the i-th unit circuit 150 is grounded to the potential Gnd, and the shift signal Yi becomes L level.

Hereinafter, every time the logic level of the clock signal Φ (inverted clock signal / Φ) is inverted, the period (
The operation state of d) and the operation state of period (e) are repeated alternately. For this reason, the output terminal Out in the i-th unit circuit 150 is, if the clock signal branch 146 is at the H level,
It is grounded to the potential Gnd via the turned-on TFT 152 and is fixed at the L level. On the other hand, if the clock signal branch line 146 is at the L level, it becomes a high impedance state, but is almost held at the L level which is the immediately preceding state. The

In the even-numbered stage, as described above, when attention is paid to the logic levels of the clock signal branch lines 145 and 146, the operation of the even-numbered unit circuit is exactly the same as that of the odd-numbered unit circuit.
Therefore, according to the configuration in which such unit circuits 150 are cascaded and the clock signal Φ and the inverted clock signal / Φ are interchanged in the odd and even stages, as shown in FIG. Each time the logic level of (inverted clock signal / Φ) is inverted, the transfer signals Y1, Y2, Y3,. Y320 is output from the unit circuit 150 at the 1, 2, 3,..., 320th stage.

Incidentally, the unit circuit 150 at the 321st stage supplies the shift signal Y321 to the unit circuit 150 at the 320th stage to turn on the TFT 154 at the 320th stage.
Since the next stage does not exist in the unit circuit 150 of the first stage, the TFT 154 does not turn on at the 321st stage, and the node A does not appear to be at the L level.
However, when the shift signal Y320 from the unit circuit 150 in the 320th stage changes from H to L level, the L level continues for almost one frame period, so the TFT 153 in the 321st stage is turned off over the period in which it goes to the L level. Will remain. For this reason,
In the 321st stage, the potential of the node A in the high impedance state, that is, the potential of the gate electrode of the TFT 151 is gradually decreased due to a leakage current or the like, so that it eventually becomes lower than the off voltage and the TFT 151 is turned off. It will be.
Therefore, at the 320th stage, the shift signal Y of the previous stage passes after the period of one frame has elapsed.
When 319 becomes H level, the shift signal Y321 at the next stage does not yet become H level.
Alternatively, a configuration may be employed in which the gate of the TFT 151 is lowered to the off voltage by positively connecting the gate of the TFT 154 in the 321st stage to the gate of the TFT 151 so that the TFT 154 is in a half-on state. In this configuration, the TFT 154 is turned on when the TFT 153 is turned on.
However, by setting the transistor shape so that the on-resistance of the TFT 154 is larger than the on-resistance of the TFT 153, the operation when the TFT 153 is on is maintained.
Further, a signal corresponding to the shift signal by the unit circuit 150 at the 320th stage or the 321st stage may be supplied from the control circuit 20. In particular, when the shift signal Y321 from the 320th stage unit circuit 150 is supplied from the control circuit 20, the 321st stage unit circuit 150 becomes unnecessary.

In the shift register according to the present embodiment, the elements constituting the unit circuit of each stage are:
Four elements of TFTs 151 to 154 are sufficient, and the number is reduced to less than half compared with the nine elements described in the background art described above. For this reason, not only can the structure be simplified and the yield rate in the manufacturing process can be improved, but also the pitch of the scanning lines 112 can be easily reduced, and high-definition display can be achieved by minimizing the pixels.

In the shift register according to the embodiment, it has been described that the node A is in the high impedance state in the period (d), and thus is maintained in the state of the L level immediately before. However, the clock signal branch line 145 is in the period. When the capacitance C1 is not sufficiently smaller than the capacitance C2 when changing from L to H level from (c) to the period (d), the node A that should be at L level
This voltage may rise as indicated by * in FIG. 7, which may result in a state where the off-resistance of the TFT 151 becomes small (half-on state).

Therefore, as shown in FIG. 13, the auxiliary capacitor Ca may be inserted between the gate and drain electrodes of the TFT 151. With this configuration, the node A can increase the capacitive coupling of the output end Out (scanning line 112), and thus can suppress a voltage change when the node A enters a high impedance state.
Such suppression of voltage change can also be achieved by a configuration in which the auxiliary capacitor Ca is interposed between the node A and the clock signal branch line 146 as shown in FIG. Since the voltage of the clock signal branch line 146 changes in the opposite direction to the clock signal branch line 145 that increases the voltage to the node A, the capacity required for the auxiliary capacitor Ca can be small, but the voltage of the clock signal branch line 146 is accompanied. There is also an aspect that electric power is wasted for the charge / discharge.
In any case, the specific capacitance value of the auxiliary capacitor Ca depends on various conditions such as the parasitic capacitances C1 and C2 of the TFT 151 and the threshold voltage. What is necessary is just to obtain a value that can be ignored.

In the embodiment, the output terminal Out of the unit circuit 150 in the i-th stage is the previous (i
-1) stage, the i stage corresponding to itself, and the shift signal by the next (i + 1) stage unit circuit are all at L level, and if the clock signal branch 146 is at H level, the potential Although it is determined to be Gnd (L level), if the clock signal branch 146 is at L level, a high impedance state is set. That is, the output terminal Out of the i-th unit circuit 150 is the next (
After the shift signal by the (i + 1) stage unit circuit becomes H level, the state determined to L level and the high impedance state are alternately switched every horizontal scanning period (H). .
Even when the scanning line is in a high impedance state, various capacitances are parasitic on the scanning line 112 as described above, so that the scanning line 112 is maintained at the L level, which is the previous state. From the viewpoint of suppressing the fluctuation and preventing the deterioration of the display quality, the scanning line 11
It can be said that it is desirable to avoid 2 becoming a high impedance state.

Therefore, as shown in FIG. 15, in the unit circuit 150 of each stage, the TFT 1
A holding circuit 160 including 61 to 163 may be provided.
In this figure, each of the TFTs 161 to 163 is an n-channel type. Among these, the gate electrode of the TFT 161 is connected to the output terminal Out, and the source electrode thereof is connected to the potential Gnd.
Is grounded. Further, a shift signal Y (i + 1) at the next (i + 1) stage is supplied to the gate electrode of the TFT 162, and its source electrode is connected to a power supply line of the voltage Vdd. The gate electrode of the TFT 163 is connected to the common drain electrode of the TFTs 161 and 162, the source electrode is grounded to the potential Gnd, and the drain electrode is connected to the output terminal Out.

In such a configuration, the shift signal Yi changes from H to L level, and the shift signal Y (
When i + 1) becomes H level, that is, when a period corresponding to the period (c) described above is reached,
Since the TFT 161 and the TFT 162 are turned off and on, respectively, the voltage Vdd is applied to the gate electrode of the TFT 163, so that the TFT 163 is turned on. Therefore, the i-th unit circuit 1
The output terminal Out at 50 is grounded to the potential Gnd via the turned-on TFT 163, and the voltage Vdd is charged to the capacitor C 5 parasitic on the TFT 163.
When the shift signal Y (i + 1) becomes the L level, the gate electrode of the TFT 163 enters a high impedance state, but the voltage Vdd is held by the capacitor C5.
The ON state of 63 is maintained. On the other hand, when the shift signal Yi of the own stage becomes H level, the TFT
161 is turned on, and the gate electrode of the TFT 163 changes from the held voltage Vdd to the ground potential Gnd, whereby the TFT 163 is turned off.
Therefore, according to such a holding circuit 160, the output terminal Out of the unit circuit 150 in the i-th stage shifts to its own stage after the shift signal Y (i + 1) of the next stage becomes H level. Until the signal Yi becomes H level, the TFT 163 is turned on to determine the potential Gnd at L level.

In the embodiment, the output terminal Out of the i-th unit circuit 150 is fixed to the potential Gnd (L level) if the clock signal branch line 146 is at the H level, and therefore the gate electrode of the TFT 161 has a self-stage. The shift signal Y (i−1) of the immediately preceding stage may be supplied instead of the shift signal Yi of the previous stage, or the output terminal Out of the own stage does not become the H level, and the clock signal branch line When 146 is at L level (clock signal branch 145 is at H level), TFT 163
It is also possible to supply a control signal from the outside to the gate electrode of the TFT 163 so that is turned on.

By the way, in recent years, a type in which a display panel can be rotated by 180 degrees, such as a viewfinder such as a video camera or a digital still camera, is emerging. When the rotation angle of the display panel is 0 degree and when it is 180 degrees, the vertical scanning direction is reversed when viewed from a fixed point of the panel.
For this reason, in the scanning line driving circuit 140 that drives the scanning lines, the order of selecting the scanning lines needs to correspond to both directions from one to the other and from the other to the one. In the scanning line driving circuit 140 shown in FIG. 3, the transfer start pulse Dy is applied to the clock signal Φ (
Each time the logic level of the inverted clock signal / Φ) transitions, it can be shifted in order only in one direction, ie, 1, 2, 3,.
Therefore, the scanning line driving circuit 140 that can transfer not only in one direction but also in other directions will be described.

FIG. 16 is a block diagram showing a configuration of the scanning line driving circuit 140 capable of bidirectional transfer.
FIG. 17 is a diagram showing this unit circuit.
As shown in FIG. 16, “3” is “2” more than “320” which is the number of rows of the scanning lines 112.
The unit circuit 150 of 22 ”stages is connected in cascade. This is because the transfer start pulse D
When the transfer direction of y is changed to the downward transfer from Y1 to Y320, the shift signal Y321 by the unit circuit 150 at the 321st stage is required as the next stage of the unit circuit 150 at the 320th stage that outputs the shift signal Y320. In the same manner, when the transfer direction of the transfer start pulse Dy is changed from Y320 to Y1 upward, 0 is set as the next stage of the unit circuit 150 of the first stage that outputs the shift signal Y1. This is because the shift signal Y0 by the stage unit circuit 150 is further required.
The number of stages 0, 1, 2, 3,..., 320, 321 is fixedly handled regardless of the transfer direction, but the concept of the previous stage and the next stage is a shift signal. Considering the transfer direction, it becomes a relative relationship. That is, in the downward transfer, the shift signal Y (i−1),
Since it becomes the H level in the order of Yi, Y (i + 1), when the i-th stage is taken as a reference, (i
The -1) stage is the previous stage, and the (i + 1) stage is the next stage. In the upward transfer, the shift signals Y (i + 1), Yi, Y (i-1) Since the i-th stage is the reference, the (i + 1) -th stage is the previous stage, and the (i-1) -th stage is 1
It becomes the relationship of the next stage.

In the scanning line driving circuit 140, whether to perform the downward transfer or the downward transfer is designated by the transfer direction designation signals Dir-d and Dir-u. Specifically, when downward transfer is designated, the transfer direction designation signal Dir-d is at H level and the transfer direction designation signal Dir-u is at L level, while upward transfer is designated. On the contrary, the transfer direction designation signal Dir-d
Becomes L level, and the transfer direction designation signal Dir-u becomes H level.
The scanning line driving circuit 140 is provided with analog switches 21, 22, 25 to 28 that are transfer gates. Among them, the analog switch 21 is turned on when the transfer direction designation signal Dir-d becomes H level, and the transfer start pulse Dy is sent to the shift signal of the previous stage with respect to the unit circuit 150 of the 0th stage. On the other hand, the analog switch 22 is turned on when the transfer direction designation signal Dir-u becomes H level, and one transfer start pulse Dy is supplied to the unit circuit 150 at the 321st stage. It is configured to supply as a shift signal of the previous stage.
The analog switches 25 and 26 are turned on when the transfer direction designation signal Dir-d becomes H level, and supply the clock signal Φ to the signal trunk line 141 and the inverted clock signal / Φ to the signal trunk line 142, respectively. On the other hand, the analog switches 27 and 28 are connected to the transfer direction designation signal D.
When ir-u becomes H level, each turns on, and the clock signal Φ is sent to the signal trunk line 142,
The inverted clock signal / Φ is supplied to the signal trunk line 141, respectively.

On the other hand, in the unit circuit 150, as shown in FIG.
A selector 170 composed of 174 is separately provided.
Here, a transfer direction designation signal Dir-d is supplied to the gate electrode of the TFT 171, a shift signal Y (i−1) is supplied to its source electrode, and its drain electrode is connected to the TFT 153.
Connected to the gate and source electrodes. A transfer direction designation signal Dir-u is supplied to the gate electrode of the TFT 172, a shift signal Y (i + 1) is supplied to its source electrode, and its drain electrode is connected to the gate / source electrode of the TFT 153. .
On the other hand, the transfer direction designation signal Dir-d is supplied to the gate electrode of the TFT 173, the shift signal Y (i + 1) is supplied to its source electrode, and its drain electrode is connected to the gate electrode of the TFT 154. . Further, the transfer direction designation signal Dir-u is supplied to the gate electrode of the TFT 174, the shift signal Y (i-1) is supplied to the source electrode, and the drain electrode is connected to the gate electrode of the TFT 154. ing.

Therefore, when the transfer direction designation signal Dir-d is at the H level (transfer direction designation signal Dir-u is at the L level) and the downward transfer is designated, the unit circuit 150 in each stage has the TFT 171,
Since 173 is turned on and TFTs 172 and 174 are turned off, an equivalent circuit thereof is the same as that in FIG. After all, when the transfer start pulse Dy is supplied, the shift signal becomes H level in the order of (Y0), Y1, Y2, Y3,..., Y320, (Y321) every time the logic level of the clock signal changes. Become. From the viewpoint of the waveform, the shift signals Y1, Y2, Y3,..., Y320 are based on the clock signal Φ (inverted clock signal) with respect to the waveform shown in FIG. / Φ) is delayed by a half period.
On the other hand, when the transfer direction designation signal Dir-u is at the H level (transfer direction designation signal Dir-d is at the L level) and the upward transfer is designated, the unit circuits 150 of each stage have the TFTs 171 and 173.
Is turned off and the TFTs 172 and 174 are turned on, so that the shift signal Y (i + 1) is applied to the TFT1.
53 is supplied to the source / drain electrodes and the shift signal Y (i-1) is applied to the TFT.
154 is supplied to the gate electrode 154. However, in the case of the upward transfer, for the i-th stage, the previous stage is the (i + 1) -th stage and the next stage is the (i-1) -th stage. The drain signal of the previous stage is supplied to the drain electrode, and T
The relationship in which the next-stage shift signal is supplied to the gate electrode of the FT 154 is the same as the downward transfer.
On the other hand, when the upward transfer is designated, the relationship between the clock signal Φ and the inverted clock signal / Φ supplied to the signal trunk lines 141 and 142 is replaced with the downward transfer. Eventually, transfer start pulse D
Since the transfer path of y does not change at all in the case of the downward transfer and the upward transfer,
When the transfer start pulse Dy is supplied, the shift signal becomes H level in the order of (Y321), Y320, Y319,..., Y1, (Y0) every time the logic level of the clock signal changes.

According to the scanning line driving circuit 140 shown in FIG. 16 and FIG. 17, in addition to being able to transfer in both directions, the elements constituting the unit circuit of each stage are TFT 17 to 154 in addition to TFTs 151 to 154.
1 to 174 is sufficient, and the number can be reduced compared to the 9 elements described in the background art.
In the scanning line driving circuit 140 capable of bidirectional transfer, if the total number of unit circuits 150 is not an even number but an odd number as shown in FIG. 16, the clock signal branch lines 145 and 146 are provided.
The analog switches 25 to 18 are symmetrical when viewed from above and from below.
Is unnecessary.

In the embodiment, since the TFT 116 is an n-channel type, the active level is H level and the non-active level is L level.
When p is a p-channel type, the active level becomes L level and the non-active level becomes H level. When the TFT 116 is of a p-channel type, the L level pulse is sequentially transferred. However, the configuration will not be described separately.

In each of the above-described embodiments, when the pixel capacitor 120 is taken as a unit, the writing polarity is inverted every frame period, because the pixel capacitor 120 is only for AC driving. The inversion may be performed every period of two frames or more.
Furthermore, although the pixel capacitor 120 is in the normally white mode, it may be in a normally black mode in which the pixel capacitor 120 becomes dark when no voltage is applied. R (red), G (green),
Color display may be performed by configuring one dot with three B (blue) pixels, and another one color (for example, cyan (C)) is added, and one dot is formed with these four color pixels. To improve color reproducibility.

In the above description, the reference of the write polarity is the voltage of the common electrode 108.
This is a case where the TFT 116 in the pixel 110 functions as an ideal switch. Actually, the drain electrode (pixel electrode 118) is changed when the state changes from on to off due to the parasitic capacitance between the gate and drain electrodes of the TFT 116. ) Occurs (called push-down, punch-through, field-through, etc.). In order to prevent the deterioration of the liquid crystal, the pixel capacitor 120 must be AC driven. However, when AC driving is performed using the voltage applied to the common electrode 108 as a reference for the writing polarity, negative writing is used for pushdown. The effective voltage value of the pixel capacitor 120 is slightly larger than the effective value by the positive polarity writing (in the case where the TFT 116 is an n-channel). Therefore, in practice, the reference voltage of the write polarity is divided from the voltage of the common electrode 108. Specifically, the reference voltage of the write polarity is changed to the voltage of the common electrode so that the influence of pushdown is offset. Alternatively, the offset may be set to a higher position.
Further, the other end of the storage capacitor 130 is not constant, and may be configured such that it is set to the low-order side during positive polarity writing, then switched to the high-order side, switched to the high-order side during polarity writing, and then switched to the low-order side. .

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 18 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 10 according to the embodiment.
As shown in this figure, a cellular phone 1200 includes the electro-optical device 10 described above together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. Note that components of the electro-optical device 10 other than the portion corresponding to the display region 100 do not appear as appearance.

Electronic devices to which the electro-optical device 10 is applied include a digital still camera, a notebook computer, a liquid crystal television, a viewfinder type (in addition to the mobile phone shown in FIG.
Or a monitor direct view type video recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a videophone, a POS terminal, a device equipped with a touch panel, and the like. And as a display device for these various electronic devices,
Needless to say, the above-described electro-optical device 10 is applicable.

1 is a diagram illustrating an electro-optical device using a shift register according to an embodiment of the present invention. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. It is a figure which shows the structure of the shift register (scanning line drive circuit). It is a figure which shows the structure of the unit circuit in the shift register. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows operation | movement of the shift register. It is an equivalent circuit diagram which shows operation | movement of the unit circuit. It is an equivalent circuit diagram which shows operation | movement of the unit circuit. It is an equivalent circuit diagram which shows operation | movement of the unit circuit. It is an equivalent circuit diagram which shows operation | movement of the unit circuit. It is an equivalent circuit diagram which shows operation | movement of the unit circuit. It is a figure which shows another example of the same unit circuit. It is a figure which shows another example of the same unit circuit. It is a figure which shows another example of the same unit circuit. It is a figure which shows the structure of the shift register which can be transferred bidirectionally. It is a figure which shows the structure of the unit circuit in the shift register. It is a figure which shows the structure of the mobile telephone using the electro-optical apparatus which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 20 ... Control circuit, 100 ... Display area, 108 ... Common electrode, 11
0 ... pixel, 112 ... scan line, 114 ... data line, 116 ... TFT, 120 ... pixel capacity, 1
40: scanning line driving circuit, 145, 146 ... clock signal branch line, 150 ... unit circuit, 151
˜154... TFT, 160... Holding circuit, 161 to 163... TFT, 170.
71 to 174... TFT, 190... Data line drive circuit, 1200.

Claims (7)

A shift register that cascade-connects a plurality of unit circuits and outputs a shift signal that becomes an active level exclusively and sequentially from the output terminal of each stage unit circuit,
Each stage unit circuit includes first and second transistors, a set switch, and a reset switch.
In the unit circuit of each stage,
A source electrode of the first transistor is connected to one of a pair of clock signal branches supplying a pair of complementary clock signals;
A gate electrode of the second transistor is connected to the other of the clock signal branch lines, and a source electrode of the second transistor is connected to a power supply line that supplies one of logic levels;
Drain electrodes of the first and second transistors are connected to the output terminal;
In the case of the unit circuit of the first stage, the set switch is turned on when the transfer start pulse becomes an active level. In the case of a unit circuit other than the first stage, the shift signal from the unit circuit of the previous stage becomes the active level. A voltage that turns on the first transistor is applied to the gate electrode of the first transistor,
The reset switch is turned on when a shift signal by the unit circuit of the next stage becomes an active level, and applies a voltage for turning off the first transistor to the gate electrode of the first transistor,
In the odd-number unit circuit, one of the pair of complementary clock signals is supplied to one of the clock signal branches, and the other of the complementary clock signals is supplied to the other of the complementary clock signals.
In the even-numbered unit circuit, one of the complementary clock signals is supplied to the other of the clock signal branch lines, and the other of the complementary clock signals is supplied to one of the clock signal branch lines. Shift register. The shift register according to claim 1, wherein an auxiliary capacitor is interposed between the gate and drain electrodes of the first transistor. The output terminal of the unit circuit is held at the non-active level for a part or all of the period in which one of the clock signal branch lines is at the active level during the period when the shift signal by the unit circuit is not at the active level. The shift register according to claim 1, further comprising: a holding circuit that performs the following operation. The set switch is
A gate electrode and a source electrode are connected, a shift signal from the unit circuit of the previous stage is supplied to the connection point, and a drain electrode is connected to the gate electrode of the first transistor. Yes,
The reset switch is
A shift signal from the unit circuit of the next stage is supplied to the gate electrode, the source electrode is connected to a power supply line that supplies one of the logic levels, and
The shift register according to claim 1, wherein a drain electrode is a fourth transistor connected to a gate electrode of the first transistor. Depending on the transfer direction of the shift signal,
Supplying a shift signal from the unit circuit of the previous stage to the connection point of the source electrode and the gate electrode of the third transistor;
5. The shift register according to claim 4, further comprising: a selector that supplies a shift signal from the unit circuit of the next stage to the gate electrode of the fourth transistor. Multiple rows of scanning lines;
Multiple columns of data lines;
A plurality of scanning lines are provided corresponding to the intersections of the scanning lines of the plurality of rows and the data lines of the plurality of columns. Each of the scanning lines is supplied to the data line corresponding to itself when the scanning line corresponding to the scanning line becomes active. A pixel having a gradation corresponding to the received data signal,
A data line driving circuit for supplying a data signal corresponding to the gradation of the pixel to the pixel corresponding to the scanning line having an active level via the data line;
With
6. An electro-optical device, wherein the shift signal by the shift register according to claim 1 is used as a scanning line driving circuit that supplies the plurality of rows of scanning lines. An electronic apparatus comprising the electro-optical device according to claim 6.

Images