JP2008091689A - Lateral double-diffused mos transistor, its manufacturing method, and integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lateral double-diffused MOS transistor with high withstand voltage and low on-resistance characteristics. <P>SOLUTION: The lateral double-diffused MOS transistor includes a second conductivity type semiconductor layer 1, a first conductivity type element region 2, a second conductivity type body diffusion region 3, gate insulating films 4a and 4b, a gate electrode 5, a first conductivity type source diffusion region 6, a first conductivity type drain diffusion region 7, and a LOCOS 10 formed in a region along the drain diffusion region 7. In the lateral direction of the element region 2, the impurity concentration of a specific region 2a occupying the area from a first boundary location 15 to a second boundary location 16 is lower than that of a main region 2b occupying the area from the body diffusion region 3 to the first boundary location 15. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a lateral double diffused MOS transistor and a manufacturing method thereof, and more particularly to a lateral double diffused MOS transistor having a high breakdown voltage and a low on-resistance characteristic and a manufacturing method thereof.

  The present invention also relates to an integrated circuit including such a lateral double diffusion field effect transistor.

  In recent years, as electronic devices have become multifunctional, semiconductor devices used for them have been diversified, and high withstand voltage, high power, small size, and low power consumption are required. In order to achieve low power consumption, a transistor with low on-resistance is required.

FIG. 4 shows the structure of a general lateral double-diffused MOS transistor. This horizontal double diffusion type MOS transistor is an N channel type MOS transistor in this example, and includes a low concentration N well diffusion region 102 as a drift region formed on a P type silicon substrate 101. A P body diffusion region 103 for forming a channel is formed on the surface in the low concentration N well diffusion region 102. A gate electrode 105 is provided via a gate oxide film 104 at a position covering from the P body diffusion region 103 to the N well diffusion region 102 outside the diffusion region. An N ⁺ source diffusion region 106 and an N ⁺ drain diffusion region 107 are formed on the surface of the P body diffusion region 103 and the surface of the N well diffusion region 102 corresponding to both sides of the gate electrode 105, respectively. Of the P body diffusion region 103, a region immediately below the gate electrode 5 and sandwiched between the N ⁺ source diffusion region 106 and the N well diffusion region 102 is a channel. The P body diffusion region 103 is short-circuited to the N ⁺ source diffusion region 106 via the P ⁺ back gate diffusion region 108 and a wiring (not shown), thereby preventing the parasitic NPN from operating.

The lateral double diffused MOS transistor is required to have a particularly high breakdown voltage and a low on-resistance. The breakdown voltage is determined by the lateral distance (the length of the drift region) between the P body diffusion region 103 and the N ⁺ drain diffusion region 107 and the concentration of the N well diffusion region 102. That is, the longer the drift region and the lower the concentration of the N-well diffusion region 102, the higher the breakdown voltage. (The reason is that when the depletion layer expands from the body region 103 and reaches the drain diffusion region 107, it does not expand further. This is because breakdown occurs due to electric field concentration there.) However, in order to reduce the on-resistance, which is another necessary performance, it is necessary that the drift region is short and the concentration of the N well diffusion region 102 is high. As a result, the breakdown voltage and the on-resistance are in a trade-off relationship. Also, since downsizing is required, it is unacceptable to make the drift region longer and the breakdown voltage higher.

On the other hand, in order to increase the length of the drift region with the same area, a LOCOS (local oxide film) is formed by local oxidation in a portion along the N ⁺ drain diffusion region 107 in the N well diffusion region 102 as shown in FIG. ) 110 is known. Thereby, in addition to the effect that the depletion layer extending from the body region 103 does not easily reach the drain diffusion region 107, the effect of preventing the gate oxide film from being broken at the end of the gate electrode is obtained. However, in the structure in which the LOCOS 110 is simply provided in this way, the depletion layer spreads unevenly, the electric field concentrates in the vicinity of the LOCOS edge 114, and the breakdown voltage may decrease.

Therefore, conventionally, as shown in FIG. 6, a structure has been proposed in which the impurity concentration of the surface (portion indicated by +) 121 of the gap region (drift region) is made thinner than the substrate region below LOCOS 110 ( For example, see Patent Document 1 (Japanese Patent Laid-Open No. 10-256534). Thereby, the concentration of the electric field in this portion 121 is prevented, and the breakdown voltage is prevented from decreasing.
Japanese Patent Laid-Open No. 10-256534 Japanese Patent Laid-Open No. 3-201484

  However, in the structure shown in FIG. 6, since the N-type impurity concentration in the surface portion is lowered over the entire gap region (drift drain region) between the body diffusion region 103 and the LOCOS 110, the on-resistance is reduced. There is a problem that you can not.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a lateral double diffused MOS transistor having a high breakdown voltage and a low on-resistance characteristic.

  In order to prevent gate oxide film breakdown at the gate electrode end, the gate oxide film thickness at the gate electrode end is increased as described in, for example, Japanese Patent Application Laid-Open No. 3-201484. It is effective.

In order to solve the above problems, the lateral double diffusion MOS transistor of the present invention is
A second conductivity type semiconductor layer;
A first conductivity type element region provided on the second conductivity type semiconductor layer;
A body diffusion region of a second conductivity type formed on the surface in the element region;
A gate electrode formed through a gate insulating film on a region covering from the body diffusion region to the element region outside the diffusion region;
A surface of the body diffusion region corresponding to both sides of the gate electrode, a source diffusion region of a first conductivity type formed on a surface of the element region, a drain diffusion region of a first conductivity type,
Locos formed in a region along the drain diffusion region between the body diffusion region and the drain diffusion region,
Of the element region, a main region that occupies from the body diffusion region to a first boundary position defined between the body diffusion region and the LOCOS in the lateral direction connecting the source diffusion region and the drain diffusion region. Compared to the impurity concentration, the impurity concentration in a specific region occupying from the first boundary position to the second boundary position defined immediately below the LOCOS is low.

  Here, for example, “first conductivity type” refers to N type, and “second conductivity type” refers to P type. Conversely, the “first conductivity type” may be P-type, and the “second conductivity type” may be N-type.

  The “impurity concentration” of a region refers to the concentration of an impurity that determines the conductivity type (N type or P type) of the region.

  In the lateral double-diffused MOS transistor of the present invention, since LOCOS is formed in the region along the drain diffusion region between the body diffusion region and the drain diffusion region, a depletion layer that extends from the body region during operation In addition to the effect of making it difficult to reach the drain diffusion region, an effect of preventing the gate oxide film from being broken at the drain diffusion region side edge of the gate electrode is obtained. Moreover, since the impurity concentration of the specific region is lower than the impurity concentration of the main region in the element region, concentration of the electric field in the specific region is prevented and the breakdown voltage does not decrease. In addition, according to the present invention, the impurity concentration is not lowered over the entire drift drain region between the body diffusion region and LOCOS, but only the impurity concentration in the specific region is lowered. Can be lowered. Therefore, a lateral double diffused MOS transistor having high breakdown voltage and low on-resistance characteristics is realized.

  The semiconductor layer of the second conductivity type may be a semiconductor substrate or another semiconductor layer (for example, an epitaxial layer) formed on the semiconductor substrate.

In the lateral double diffused MOS transistor of one embodiment,
The gate insulating film includes a first gate insulating film that covers a region from the source diffusion region to a third boundary position defined between the body diffusion region and the first boundary position, and the first gate insulating film. And a second gate insulating film covering a region from the third boundary position to the location,
Of the main region of the element region, the impurity concentration in the region from the body diffusion region to the third boundary position is at least uniform.

  According to the lateral double diffusion MOS transistor of this embodiment, the surface portion (channel region) immediately below the gate electrode in the body diffusion region is covered with the thin first gate insulating film. The mutual conductance (Gm) is increased, and the on-resistance can be further reduced.

  The lateral double diffused MOS transistor according to one embodiment is characterized in that the impurity concentration of the main region of the element region is uniform.

  In the lateral double diffused MOS transistor of this embodiment, the on-resistance can be further reduced.

  In one embodiment of the lateral double diffusion MOS transistor, the body diffusion region side edge of the LOCOS is located at the center between the first boundary position and the second boundary position.

  The “body diffusion region side edge” of the LOCOS is the edge closer to the body diffusion region of the two LOCOS edges with respect to the channel direction connecting the source diffusion region and the drain diffusion region, in other words, An edge farther from the drain diffusion region.

  In the lateral double diffusion MOS transistor of this embodiment, the body diffusion region side edge of the LOCOS is surely within the range of the specific region. Therefore, the electric field is prevented from concentrating near the body diffusion region side edge of Locos, and the breakdown voltage is surely prevented from being lowered.

  As a known integrated circuit, a first type field effect transistor having a certain drain breakdown voltage and a second type field effect transistor having a drain breakdown voltage higher than the drain breakdown voltage are mounted on the same semiconductor substrate. There is what I did. In such an integrated circuit, the thickness of the gate insulating film of the second type field effect transistor is realized in order to realize a high drain breakdown voltage with respect to the thickness of the gate insulating film of the first type field effect transistor. Is set thick.

Therefore, the integrated circuit of the present invention is
The lateral double-diffused field effect transistor according to claim 1 and the first and second types having substantially the same film thickness and different drain breakdown voltages on the same semiconductor substrate. And at least a field effect transistor,
The film thickness of the first gate insulating film of the lateral double diffusion field effect transistor is substantially the same as the film thickness of the gate insulating film of the first type field effect transistor having a certain drain breakdown voltage,
The film thickness of the second gate insulating film of the lateral double diffusion field effect transistor is substantially equal to the film thickness of the gate insulating film of the second type field effect transistor having a drain breakdown voltage higher than the drain breakdown voltage. It is characterized by being the same.

  In the integrated circuit of the present invention, the first gate insulating film of the lateral double diffusion field effect transistor of the present invention can be formed simultaneously with the gate insulating film of the first type field effect transistor. The second gate insulating film of the heavy diffusion field effect transistor can be formed simultaneously with the gate insulating film of the second type field effect transistor. Therefore, the manufacturing process can be reduced and the manufacturing cost can be reduced.

  In an integrated circuit according to an embodiment, the integrated circuit is for a switching regulator.

The manufacturing method of the lateral double diffusion MOS transistor of the present invention is as follows:
A manufacturing method of a lateral double diffusion MOS transistor for producing the lateral double diffusion MOS transistor of the invention,
Forming the locos on the surface of the second conductive type semiconductor layer;
Performing photolithography to cover a region corresponding to the specific region of the surface of the semiconductor layer of the second conductivity type with a photoresist;
Using the photoresist as a mask, a first conductivity type impurity is ion-implanted into regions corresponding to both sides of the specific region in the surface of the second conductivity type semiconductor layer, and at least the main region in the element region. Forming a region;
After removing the photoresist, heat treatment is performed, and the specific region of the element region is diffused in a lateral direction so as to merge the impurities of the first conductivity type from regions corresponding to both sides of the specific region. Forming, and
Forming the gate insulating film including the first gate insulating film and the second gate insulating film;
Forming the gate electrode;
Forming a source diffusion region and a drain diffusion region by performing ion implantation of a first conductivity type impurity using the gate electrode and the LOCOS as a mask.

  In the manufacturing method of the lateral double diffusion MOS transistor of the present invention, the structure of the lateral double diffusion MOS transistor of the present invention can be obtained.

In another aspect, a method for manufacturing a lateral double diffusion MOS transistor of the present invention includes:
A manufacturing method of a lateral double diffusion MOS transistor for producing the lateral double diffusion MOS transistor of the invention,
Forming the locos on the surface of the second conductive type semiconductor layer;
In addition to the first gate insulating film and the second gate insulating film, the gate insulating film is formed so as to include a third gate insulating film having the same thickness as the first gate insulating film outside the LOCOS. Process,
Using the LOCOS and the second gate insulating film as a mask, a region of the first conductivity type is formed in a region of the surface of the second conductivity type semiconductor layer corresponding to the region immediately below the first gate insulating film and the third gate insulating film. A step of ion-implanting impurities to form at least the main region of the element region;
By performing a heat treatment and laterally diffusing the impurities of the first conductivity type so as to merge from the region corresponding to the region immediately below the first gate insulating film and the third gate insulating film, the element in the element region Forming a specific region;
Forming the gate electrode;
Forming a source diffusion region and a drain diffusion region by performing ion implantation of a first conductivity type impurity using the gate electrode and the LOCOS as a mask.

  In the manufacturing method of the lateral double diffusion MOS transistor of the present invention, the structure of the lateral double diffusion MOS transistor of the present invention can be obtained. In addition, as compared with the manufacturing method of the previous aspect, the manufacturing process is simplified because there is no step of covering the region corresponding to the specific region with a photoresist. Therefore, man-hours and manufacturing costs can be reduced. In addition, the main region and the specific region can be accurately formed in a self-aligned manner with respect to the second gate oxide film and LOCOS.

In the manufacturing method of the lateral double diffusion type MOS transistor of one embodiment,
When the ion implantation energy for forming the main region is Rp, the ion implantation range is Rp, the dispersion of the range is ΔRp, and the thickness of the second gate oxide film is Tox.
Rp + ΔRp <Tox
It is characterized by setting so as to satisfy the following relationship.

  In the method of manufacturing a lateral double diffusion MOS transistor according to this embodiment, the second gate oxide film reliably masks the first conductivity type impurity during ion implantation for forming the main region. Is done. Therefore, the lateral double diffused MOS transistor is reliably manufactured.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

  In the following embodiment, an example in which the first conductivity type is N type and the second conductivity type is P type will be described.

(First embodiment)
FIG. 1 shows a cross-sectional structure of a lateral double diffused MOS transistor according to the first embodiment of the present invention. The lateral double diffusion MOS transistor is an N-channel MOS transistor in this example, and includes a P-type silicon substrate 1 as a second conductivity type semiconductor layer and an element region formed on the P-type silicon substrate 1. The low concentration N well diffusion region 2 is provided. A P body diffusion region 3 for forming a channel is formed on the surface in the low concentration N well diffusion region 2. A gate electrode 5 is provided through a gate oxide film 4 as an insulating film at a position covering from the P body diffusion region 3 to the N well diffusion region 2 outside the diffusion region. N ⁺ source diffusion region 6 and N ⁺ drain diffusion region 7 are formed on the surface of P body diffusion region 3 and the surface of N well diffusion region 2 corresponding to both sides of gate electrode 5, respectively.

The gate oxide film 4 has a first gate oxide film 4b that covers from the N ⁺ source diffusion region 6 to a region beyond the pattern of the P body diffusion region 3, and a thickness greater than that of the first gate oxide film 4b. And a second gate oxide film 4a covering a region closer to the N ⁺ drain diffusion region 7 than a region covered by the one gate oxide film 4b.

A LOCOS (local oxide film) 10 is formed in a region along the N ⁺ drain diffusion region 7 on the surface of the N well diffusion region 2 so as to continue to the second gate oxide film 4a. The thickness of LOCOS 10 is larger than the thickness of the second gate oxide film 4a.

Further, from the P body diffusion region 3 to the first boundary position 15 defined between the P body diffusion region 3 and the LOCOS 10 in the lateral direction connecting the N ⁺ source diffusion region 6 and the N ⁺ drain diffusion region 7. Compared to the impurity concentration of the occupied main region 2b, the impurity concentration of the specific region 2a occupying from the first boundary position 15 to the second boundary position 16 defined immediately below the LOCOS 10 is lower. The side opposite to the first boundary position 15 with respect to the second boundary position 16 in the N well diffusion region 2, that is, the N ⁺ drain diffusion region 7 side is another main impurity having the same impurity concentration as that of the main region 2 b described above. This is a region 2c. The impurity concentrations in the main regions 2b and 2c are uniform.

  In this example, the body diffusion region side edge 14 of the LOCOS 10 is located at the center between the first boundary position 15 and the second boundary position 16. A third boundary position 13 that divides the first gate oxide film 4b and the second gate oxide film 4a is defined between the P body diffusion region 3 and the first boundary position 15.

Of the P body diffusion region 3, a region sandwiched between the N ⁺ source diffusion region 6 and the N well diffusion region 2 at the surface portion immediately below the gate electrode 5 becomes a channel. Further, the surface portion of the N well diffusion region 2 becomes a drift drain region. The P body diffusion region 3 is short-circuited to the N ⁺ source diffusion region 6 by a wiring (not shown) via the P ⁺ diffusion region 8. As a result, the P body diffusion region 3 and the N ⁺ source diffusion region 6 are set to the same potential to prevent the parasitic NPN from operating. Description of other wirings, field films, and protective films is omitted for simplicity.

  This lateral double-diffused MOS transistor is manufactured as follows.

  First, as shown in FIG. 2A, a silicon oxide film 11 is formed with a thickness of 30 nm on the surface of a P-type silicon substrate 1, and a silicon nitride film 30 is grown (deposited) with a thickness of 160 nm thereon. Then, photolithography and etching are performed to remove a portion corresponding to the region (opening 30w) where the locos is to be formed in the silicon nitride film 30. Thereafter, LOCOS oxidation is performed through the opening 30w to form LOCOS 10 in the opening 30w.

  Next, all the silicon nitride film 30 is removed, and the silicon oxide film 11 other than the LOCOS 10 is also removed once.

  Thereafter, as shown in FIG. 2B, oxidation is performed to form a gate oxide film 4 with a thickness of 80 nm in a region other than LOCOS 10. The lateral double diffusion field effect transistor, the high breakdown voltage gate MOS transistor, and the low breakdown voltage gate MOS transistor are formed on a common P-type silicon substrate 1 as in the case of manufacturing an integrated circuit for a switching regulator. In this case, a gate oxide film of a high voltage gate MOS transistor (not shown) formed in parallel on the P-type silicon substrate 1 is formed simultaneously with the formation of the gate oxide film 4 (that is, a second gate oxide film 4a described later). The same thickness is formed to 80 nm.

Next, as shown in FIG. 2C, photolithography is performed to cover the portion other than the N well diffusion region 2 shown in FIG. 1 and the boundary position between the LOCOS 10 and the gate oxide film 4 (this is (This corresponds to the body diffusion region side edge of LOCOS 10 shown in FIG. 1.) Photoresist 31 is provided so as to cover the region corresponding to the specific region 2a with 14 as the center. Then, using this photoresist 31 as a mask, phosphorus 21 as an N-type impurity is ion-implanted to about 1 × 10 ¹³ atoms / cm ² into the surface portion of the P-type silicon substrate 1 corresponding to the opening of the photoresist 31. . At this time, the region corresponding to the specific region 2a in the P-type silicon substrate 1 is still P-type.

Next, after removing the photoresist 31, as shown in FIG. 2D, a drive-in process is performed as a heat treatment at 1200 ° C. for 600 minutes. As a result, the main regions 2b and 2c of the N well diffusion region 2 are formed, and the specific regions of the N well diffusion region 2 are diffused by laterally diffusing phosphorus from the main regions 2b and 2c. 2a is formed. In this case, the specific region 2a, that is, the region 2a in which phosphorus is not ion-implanted around the LOCOS edge 14 is temporarily N-type, but the main regions 2b and 2c into which phosphorus is directly ion-implanted are formed. impurity concentration ^- than (Figure in 2D N. indicated by), the impurity concentration is lower ^(- shown in in Figure 2D ^N.). In particular, the vicinity of the LOCOS edge 14 is farthest from the main regions 2b and 2c into which phosphorus is directly ion-implanted, so that the impurity concentration is the lowest. On the other hand, the impurity concentrations in the main regions 2b and 2c are substantially uniform.

Next, as shown in FIG. 2E, about 3 × 10 ¹³ atoms / cm ^{2 of} boron is ion-implanted into the main region 2b of the N-well diffusion region 2 by a known method to form a P-type body serving as a channel region. A diffusion region 3 is formed.

  Thereafter, a part of the gate oxide film 4, that is, a portion corresponding to the left side of the third boundary position 13 defined between the P body diffusion region 3 and the first boundary position 15 in FIG. 2E is once etched. Removal and re-oxidation are performed to form a first gate oxide film 4b having a thickness of 25 nm. At this time, a portion of the gate oxide film 4 on the right side of the third boundary position 13 is left as the second gate oxide film 4a. The lateral double diffusion field effect transistor, the high breakdown voltage gate MOS transistor, and the low breakdown voltage gate MOS transistor are formed on a common P-type silicon substrate 1 as in the case of manufacturing an integrated circuit for a switching regulator. In this case, simultaneously with the formation of the first gate oxide film 4b, a gate oxide film of a low breakdown voltage gate MOS transistor (not shown) formed in parallel on the P-type silicon substrate 1 is formed to the same thickness of 25 nm.

  Next, polysilicon is formed on the entire upper surface, and the polysilicon is patterned to form the gate electrode 5 as shown in FIG. 2F. At this time, the gate electrode 5 is formed at a position extending from the P body diffusion region 3 to the LOCOS 10 in the N well diffusion region 2. During operation, a portion of the P-type body diffusion region 3 where the gate electrode 5 overlaps becomes a channel.

Next, as shown in FIG. 1, arsenic is ion-implanted at about 6 × 10 ¹⁵ atoms / cm ^{2 using} the gate electrode 5 and the LOCOS 10 as a mask. Thus, N ⁺ source diffusion region 6 is formed on the surface of P body diffusion region 3 in a self-aligned manner with respect to gate electrode 5, and on the surface of main region 2 c of N well diffusion region 2 with respect to LOCOS 10. Thus, the N ⁺ drain diffusion region 7 is formed in a self-aligning manner.

Finally, in order to take the back gate of the P-type body diffusion region 3, a P ⁺ back gate diffusion region 8 is formed at a position along the source diffusion region 6, and the source diffusion region 6, the P ⁺ back gate diffusion region 8, Is short-circuited by wiring not shown.

  In this way, the lateral double diffusion MOS transistor of FIG. 1 is manufactured.

In the lateral double diffused MOS transistor thus fabricated, the LOCOS 10 is formed in a region along the drain diffusion region 7 between the P body diffusion region 3 and the N ⁺ drain diffusion region 7. In addition to the effect of preventing the depletion layer extending from the P body diffusion region 3 from reaching the drain diffusion region 7 during operation, the gate oxide film can be prevented from being destroyed at the drain diffusion region side edge of the gate electrode 5. . In addition, since the impurity concentration of the specific region 2a is lower than the impurity concentration of the main regions 2b and 2c in the N well diffusion region 2, the concentration of the electric field in the specific region 2a, that is, the LOCOS edge 14 is prevented. Will not drop. In addition, in the present invention, the impurity concentration is not lowered over the entire drift drain region between the P body diffusion region 3 and the LOCOS 10, but only the impurity concentration in the specific region 2a is lowered. Therefore, an increase in on-resistance can be suppressed to a minimum, and the on-resistance can be lowered as compared with the conventional example described in Patent Document 1 (Japanese Patent Laid-Open No. 10-256534).

  Further, since the surface portion (channel region) immediately below the gate electrode 5 in the P body diffusion region 3 is covered with the first gate insulating film 4b having a small film thickness, the mutual conductance (Gm) is increased. Furthermore, the on-resistance can be lowered. If the channel region is covered with the thick second gate insulating film 4a, the mutual conductance (Gm) decreases and the on-resistance increases.

  A third boundary position 13 that divides the first gate insulating film 4 b and the second gate insulating film 4 a is defined between the P body diffusion region 3 and the first boundary position 15. This is because the main region 2b always occupies the region immediately below the first gate oxide film 4b in the drift region (in other words, the specific region 2a protrudes into the region immediately below the first gate oxide film 4b. Means not). This is to make the on-resistance of the lateral double diffusion MOS transistor as low as possible. That is, when the positive voltage applied to the gate electrode 5 is increased, the surface portion (channel region) immediately below the gate electrode 5 in the P body diffusion region 3 is N-type inverted and is originally N-type. The N-type carrier density becomes higher than the N-type carrier density on the surface of the main region 2b. The degree depends on the thickness of the gate oxide film. As the gate oxide film is thinner, N-type inversion occurs at a lower gate voltage, and the N-type carrier density increases. Therefore, the N-type carrier density in the region immediately below the first gate oxide film 4b is higher than the N-type carrier density immediately below the second gate oxide film 4a. Here, in the drift region, the region immediately below the first gate oxide film 4b is always occupied by the main region 2b, so that the N-type carrier density in the region immediately below the first gate oxide film 4b can be further increased. it can. If the specific region 2a protrudes into the region immediately below the first gate oxide film 4b, that is, if the impurity concentration in the region immediately below the first gate oxide film 4b is partially low, the N-type is already turned on. Even if it reverses, it becomes disadvantageous regarding on-resistance.

  Further, since the impurity concentration of the main region 2b is substantially uniform as described above, the on-resistance can be further reduced.

  Thus, according to the present invention, a lateral double diffusion MOS transistor having a high breakdown voltage and a low on-resistance characteristic is realized.

  Further, as in the case of manufacturing an integrated circuit for a switching regulator, this lateral double diffusion field effect transistor, a high breakdown voltage gate MOS transistor as a first type, and a low breakdown voltage gate MOS transistor as a second type Are formed on the P-type silicon substrate 1, an integrated circuit in which these three types of transistors are mixedly mounted on the common P-type silicon substrate 1 can be obtained by the above-described manufacturing method. As described above, the first gate insulating film 4b of the lateral double diffusion field effect transistor can be formed simultaneously with the gate insulating film of the low breakdown voltage field effect transistor. The two-gate insulating film 4a can be formed simultaneously with the gate insulating film of the high breakdown voltage field effect transistor. Therefore, the manufacturing process can be reduced and the manufacturing cost can be reduced.

(Second Embodiment)
The lateral double-diffused MOS transistor is manufactured by another manufacturing method.

  This manufacturing method is different in that ion implantation is performed using a gate insulating film and LOCOS as a mask, as shown in FIG. 3, instead of the mask made of the photoresist 31 shown in FIG. 2C.

  Specifically, after forming the gate oxide film 4 in a region other than the LOCOS 10 as shown in FIG. 2B, it is defined between the P body diffusion region 3 and the first boundary position 15 as shown in FIG. The portion corresponding to the left side of the third boundary position 13 and the portion corresponding to the right side of the LOCOS 10 are temporarily removed by etching, and re-oxidation is performed, so that the first gate oxide film 4b having the film thickness of 25 nm, the first Three gate insulating films 4c are formed. At this time, a portion of the gate oxide film 4 from the third boundary position 13 to the location 10 is left as the second gate oxide film 4a.

  Next, using the LOCOS 10 and the second gate insulating film 4a as a mask, the region of the surface of the P-type silicon substrate 1 corresponding to the region immediately below the first gate insulating film 4b and the third gate insulating film 4c has the first conductivity type. Phosphorus 21 as an impurity is ion-implanted.

Here, when the ion implantation energy is Rp, the range of the ion implantation is ΔRp, and the thickness of the second gate oxide film 4a is Tox.
Rp + ΔRp <Tox (1)
To satisfy the relationship. With this setting, the phosphorus 21 is reliably masked by the second gate oxide film 4a. That is, it means that almost no ion species (phosphorus in this example) are implanted into the silicon semiconductor layer. Therefore, at this stage, the above-described specific region 2a can be reliably left in the P-type, and the lateral double-diffused MOS transistor can be reliably manufactured.

  Thereafter, as described in the first embodiment, a drive-in process is performed as a heat treatment at 1200 ° C. for 600 minutes. As a result, the main regions 2b and 2c of the N well diffusion region 2 are formed, and the specific regions of the N well diffusion region 2 are diffused by laterally diffusing phosphorus from the main regions 2b and 2c. 2a is formed.

  In this manufacturing method, as compared with the previous manufacturing method, there is no step of covering the region corresponding to the specific region 2a with the photoresist, so that the manufacturing process is simplified. Therefore, it is possible to reduce man-hours and manufacturing costs by reducing processes.

  In addition, the main regions 2b and 2c and the specific region 2a can be accurately formed in a self-aligned manner with respect to the second gate oxide film 4a and the LOCOS 10. Therefore, it is possible to reliably reduce the on-resistance of the lateral double diffused MOS transistor.

  In the above example, the second conductivity type semiconductor layer is the P-type silicon substrate 1, but is not limited thereto. The second conductivity type semiconductor layer may be, for example, a P-type epitaxial layer formed on the surface of a semiconductor substrate.

  Even if the conductivity type of each region of the lateral double diffusion MOS transistor is reversed, the effect of high breakdown voltage and low on-resistance can be obtained in the same manner.

  In each of the above embodiments, a silicon substrate is used as a semiconductor substrate and arsenic and phosphorus are used as impurities. However, the present invention is not limited to this, and various materials used in semiconductor manufacturing can be used. The present invention can also be widely applied to a lateral double diffusion MOS transistor using a compound semiconductor.

1 is a cross-sectional view showing a lateral double diffusion MOS transistor according to an embodiment of the present invention. It is process sectional drawing explaining the manufacturing method of the said horizontal double diffused MOS transistor. It is process sectional drawing explaining the manufacturing method of the said horizontal double diffused MOS transistor. It is process sectional drawing explaining the manufacturing method of the said horizontal double diffused MOS transistor. It is process sectional drawing explaining the manufacturing method of the said horizontal double diffused MOS transistor. It is process sectional drawing explaining the manufacturing method of the said horizontal double diffused MOS transistor. It is process sectional drawing explaining the manufacturing method of the said horizontal double diffused MOS transistor. It is process sectional drawing explaining the manufacturing method different from the said manufacturing method. It is sectional drawing which shows the conventional common horizontal type | mold double diffused MOS transistor. It is sectional drawing which shows the horizontal double diffused MOS transistor which has LOCOS along a drain region. It is sectional drawing which shows the conventional horizontal type | mold double diffused MOS transistor by which the N type impurity density | concentration of the surface part is set low over the whole clearance gap area | region between a body diffused layer and LOCOS.

Explanation of symbols

1 P-type silicon substrate 2 N-type well diffusion region 2a Specific region 2b, 2c Main region 3 P body diffusion region 4 Gate oxide film 4a First gate oxide film 4b Second gate oxide film 4c Third gate oxide film 5 Gate electrode 6 N ⁺ source diffusion region 7 N ⁺ drain diffusion region 8 P ⁺ back gate diffusion region

Claims (9)

A second conductivity type semiconductor layer;
A first conductivity type element region provided on the second conductivity type semiconductor layer;
A body diffusion region of a second conductivity type formed on the surface in the element region;
A gate electrode formed through a gate insulating film on a region covering from the body diffusion region to the element region outside the diffusion region;
A surface of the body diffusion region corresponding to both sides of the gate electrode, a source diffusion region of a first conductivity type formed on a surface of the element region, a drain diffusion region of a first conductivity type,
Locos formed in a region along the drain diffusion region between the body diffusion region and the drain diffusion region,
Of the element region, a main region that occupies from the body diffusion region to a first boundary position defined between the body diffusion region and the LOCOS in the lateral direction connecting the source diffusion region and the drain diffusion region. A lateral double diffusion MOS transistor characterized in that the impurity concentration in a specific region occupying from the first boundary position to the second boundary position defined immediately below the location is lower than the impurity concentration. The lateral double-diffused MOS transistor according to claim 1,
The gate insulating film includes a first gate insulating film that covers a region from the source diffusion region to a third boundary position defined between the body diffusion region and the first boundary position, and the first gate insulating film. And a second gate insulating film covering a region from the third boundary position to the location,
A lateral double diffusion MOS transistor, wherein an impurity concentration in a region from the body diffusion region to the third boundary position in the main region of the element region is at least uniform. The lateral double-diffused MOS transistor according to claim 2,
A lateral double-diffused MOS transistor characterized in that the impurity concentration of the main region of the element region is uniform. The lateral double-diffused MOS transistor according to claim 1,
2. The lateral double diffusion type MOS transistor according to claim 1, wherein the body diffusion region side edge of the LOCOS is located at the center between the first boundary position and the second boundary position. The lateral double-diffused field effect transistor according to claim 1 and the first and second types having substantially the same film thickness and different drain breakdown voltages on the same semiconductor substrate. And at least a field effect transistor,
The film thickness of the first gate insulating film of the lateral double diffusion field effect transistor is substantially the same as the film thickness of the gate insulating film of the first type field effect transistor having a certain drain breakdown voltage,
The film thickness of the second gate insulating film of the lateral double diffusion field effect transistor is substantially equal to the film thickness of the gate insulating film of the second type field effect transistor having a drain breakdown voltage higher than the drain breakdown voltage. An integrated circuit characterized by being the same. The integrated circuit of claim 5, wherein
The integrated circuit is used for a switching regulator. A manufacturing method of a lateral double diffusion MOS transistor for manufacturing the lateral double diffusion MOS transistor according to claim 1,
Forming the locos on the surface of the second conductive type semiconductor layer;
Performing photolithography to cover a region corresponding to the specific region of the surface of the semiconductor layer of the second conductivity type with a photoresist;
Using the photoresist as a mask, a first conductivity type impurity is ion-implanted into regions corresponding to both sides of the specific region in the surface of the second conductivity type semiconductor layer, and at least the main region in the element region. Forming a region;
After removing the photoresist, heat treatment is performed, and the specific region of the element region is diffused in a lateral direction so as to merge the impurities of the first conductivity type from regions corresponding to both sides of the specific region. Forming, and
Forming the gate insulating film including the first gate insulating film and the second gate insulating film;
Forming the gate electrode;
A step of forming a source diffusion region and a drain diffusion region by performing ion implantation of a first conductivity type impurity using the gate electrode and the LOCOS as a mask. Production method. A manufacturing method of a lateral double diffusion MOS transistor for manufacturing the lateral double diffusion MOS transistor according to claim 1,
Forming the locos on the surface of the second conductive type semiconductor layer;
In addition to the first gate insulating film and the second gate insulating film, the gate insulating film is formed so as to include a third gate insulating film having the same thickness as the first gate insulating film outside the LOCOS. Process,
Using the LOCOS and the second gate insulating film as a mask, a region of the first conductivity type is formed in a region of the surface of the second conductivity type semiconductor layer corresponding to the region immediately below the first gate insulating film and the third gate insulating film. A step of ion-implanting impurities to form at least the main region of the element region;
By performing a heat treatment and laterally diffusing the impurities of the first conductivity type so as to merge from the region corresponding to the region immediately below the first gate insulating film and the third gate insulating film, the element in the element region Forming a specific region;
Forming the gate electrode;
A step of forming a source diffusion region and a drain diffusion region by performing ion implantation of a first conductivity type impurity using the gate electrode and the LOCOS as a mask. Production method. In the manufacturing method of the horizontal double diffused MOS transistor according to claim 8,
When the ion implantation energy for forming the main region is Rp, the ion implantation range is Rp, the dispersion of the range is ΔRp, and the thickness of the second gate oxide film is Tox.
Rp + ΔRp <Tox
A method of manufacturing a lateral double-diffused MOS transistor, characterized in that it is set so as to satisfy the following relationship:

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