JP2008083888A - Memory controller, memory device and image forming apparatus using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect abnormality occurring between a memory module and a memory controller, and to decide a place where any abnormality occurs. <P>SOLUTION: A memory I/F controller 19 is provided with: a switch control part 41 for alternately applying a Vcc voltage or a GND voltage to any of control lines CL1, CL2 through CLn connected to a memory module 11 with respect to a Vcc power source and a GND power source; an I/O control part 21 for detecting the Vcc voltage and GND voltage applied to the control lines CL1, CL2, through CLn by the switch control part 41; a comparison/decision part 43 for comparing the detection values of the Vcc voltage and the GND voltage with the application values of the Vcc voltage and the GND voltage, and for deciding the abnormality factors of the control lines CL1, CL2, through CLn, based on the comparison result; and an input/output part 24 for outputting information relating to the abnormality factor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory control device, a memory device, and an image forming apparatus using them.

  Conventionally, in a circuit board for information equipment incorporating a semiconductor memory module, the semiconductor memory module is inserted into a socket soldered to the circuit board to form a connection with the memory controller. When an abnormality of the memory module is to be detected between the semiconductor memory module and the memory controller connected in this way, after writing predetermined data into the memory, the written data is read and written. By determining whether the previous data and the read data match, an abnormality between the two is detected. As an apparatus for performing such processing, there is an apparatus described in Patent Document 1.

Japanese Patent Laid-Open No. 5-128139

  However, when such a technique is used, it is possible to detect the presence or absence of abnormality by determining whether the data before writing and the read data match, but if both data do not match, There was a problem that the cause could not be determined.

  Therefore, the present invention is an invention made in view of such a situation, and a memory capable of detecting an abnormality occurring between the memory module and the memory controller and determining a location where the abnormality has occurred. It is an object of the present invention to provide a control device, a memory device, and an image forming apparatus using them.

  In order to solve the above problems, a memory control device according to the present invention includes a first voltage applying unit that applies a first voltage, and a second voltage that applies a second voltage different from the first voltage. An application control unit that alternately applies the first voltage or the second voltage to any one of the plurality of control lines connected to the memory device with respect to the voltage application unit, and the application control unit A voltage detection unit for detecting the first voltage and the second voltage applied to the plurality of control lines; the first voltage detected by the voltage detection unit; and the second voltage A comparison unit that compares a detection value of the voltage with an application value of the first voltage and the second voltage, and a determination that determines a cause of abnormality of the plurality of control lines based on a comparison result by the comparison unit And the cause of the abnormality determined by the determination unit It is characterized by comprising the cause output unit for outputting information.

  According to this configuration, the determination result output from the determination result output unit is based on a comparison result in which the comparison unit compares the application value of the first voltage and the second voltage with the detection value. When there is no abnormality in the control line, the application values of the first voltage and the second voltage applied to the plurality of control lines under the control of the application control unit and the first value detected by the voltage detection unit. The detected values of the voltage 1 and the second voltage match. However, if any of the control lines has a ground short or mixed line, and some physical abnormality occurs with the memory device, these detected values The applied value does not match. Therefore, the determination unit refers to the comparison result of such a comparison unit, determines a control line in which an abnormality has occurred among the plurality of control lines, and the cause output unit determines the cause of the abnormality determined by the determination unit. Can be output.

  In this manner, the memory control device according to the present invention can detect an abnormality that has occurred between the memory module and the memory controller, and can determine the location where the abnormality has occurred.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  The memory control device according to the embodiment is a memory control device provided in an image forming apparatus such as a color printer, for example, and controls a memory including a semiconductor storage device attached to the image forming apparatus.

  As shown in FIG. 1, the image forming apparatus 1 according to the first embodiment includes a CPU (Central Processing Unit) 3 that controls the operation of each unit constituting the image forming apparatus 1 and the image forming apparatus 1. A data control unit 5 that controls the exchange of data of each unit, a printing mechanism unit 7 that prints image data that has been transmitted from an external device such as an information processing apparatus and that has undergone predetermined image processing, and a predetermined value for the user The display unit 9 for displaying the information and the memory module 11 are provided. In such an image forming apparatus 1, the CPU 3 converts image information input from the outside into image data in a bitmap format. The image forming apparatus 1 supplies the converted image data to the mechanism control unit 13 that controls the printing mechanism unit 7 using the data control unit 5. The image forming apparatus 1 controls the printing mechanism unit 7 using the mechanism control unit 13 to print an image based on the image data on a recording medium such as paper.

  The image forming apparatus 1 also includes a CPU I / F controller 15 that establishes a connection between the CPU 3 and the data control unit 5 when data is exchanged between the CPU 3 and the data control unit 5. The CPU I / F controller 15 is an interface for establishing a connection between the CPU 3 when supplying data to the data control unit 5 or when supplying data from the data control unit 5 to the CPU 3.

  The display unit 9 displays information related to the cause of abnormality determined by a method described later to the user. Such a display unit 9 is configured by, for example, an operation panel formed in the image forming apparatus 1. In the image forming apparatus 1, the display unit 9 constitutes an inspection result output unit that outputs the inspection result to the user.

  The memory module 11 is a main memory used as a temporary storage area when the CPU 3 performs processing for converting image information transmitted from an external device into image data. Such a memory module 11 is configured by arranging a plurality of memory devices on a predetermined circuit board, and is detachably formed on the circuit board of the image forming apparatus 1.

  The image forming apparatus 1 also includes an external I / F controller 17 that establishes a connection between the image forming apparatus 1 and an external apparatus when data is transmitted and received. The external I / F controller 17 is an interface such as a Centronics, LAN (Local Area Network), or USB (Universal Serial Bus) provided on the outer surface of the image forming apparatus 1. When receiving transmitted image information, or when supplying data from the image forming apparatus 1 to an external apparatus, it is used to establish a connection between the two.

  The image forming apparatus 1 also includes a memory I / F controller 19 as a memory control device that establishes a connection between the data control unit 5 and the memory module 11 when data is exchanged between the data control unit 5 and the memory module 11. As shown in FIG. 2, the memory I / F controller 19 includes an I / O (In / Out) control unit 21 that controls the operation of the memory I / F controller 19 to exchange information with the outside, and the memory I / F. A procedure management unit 23 that manages a procedure of a predetermined operation to be performed by the controller 19 and an input / output unit 24 that inputs and outputs various types of information are provided. Although details will be described later, the memory I / F controller 19 executes a series of processes for detecting an abnormality in the physical connection between the image forming apparatus 1 and the memory module 11.

  The I / O control unit 21 is connected to a socket 25 into which the memory module 11 is inserted via a buffer group 27 and a plurality of control lines CL1, CL2,..., CLn (n: integer). Each of the control lines CL1, CL2,..., CLn is connected to the I / O control unit 21 via a buffer group 27 as a voltage detection unit configured by an input buffer and an output buffer.

  The buffer group 27 includes input buffer elements and output buffer elements corresponding to the control lines CL1, CL2,..., CLn. The voltage output from the I / O control unit 21 and the voltage input to the I / O control unit 21 are input / output via the buffer group 27. Here, the memory I / F controller 19 inputs / outputs a predetermined signal via the buffer elements constituting the buffer group 27 and reads / writes data from / to the memory module 11, but the I / O control unit 21 Buffer elements are provided not only for bidirectional data input / output from / to the memory module 11 from the memory I / F controller 19 and strobe signals, but also for control lines dedicated to output, for example, clock signals.

Each control line CL1, CL2,..., CLn is connected to the socket 25, respectively. The memory module 11 and the memory I / F controller 19 connected in this way transmit and receive various types of information via the control lines CL1, CL2,..., CLn. In the present invention, an abnormality occurs in the control lines CL1, CL2,..., CLn, and the memory device including the memory module 11 and the memory I / F controller 19 can normally transmit and receive data. If not, this is detected, and it is determined which control line CL1, CL2,. In this embodiment, for convenience of explanation, the signal lines to be detected are sent to the CLKP signal, the CLKN signal, the CKE signal, the CS signal, and the RAS signal that are transmitted and received by the memory module 11 and the memory I / F controller 19. , WE signal, A0, A1, A2, ..., A13 signal, BA0, BA1 signal, DQS0, DQS1, ..., DQS7 signal, DM0, DM1, ..., DM7 signal and DQ0, DQ1,. .. Will be described in detail as a control line for transmitting and receiving 103 signals of the DQ63 signal. And, for convenience of explanation, with these respective signals, the control line CL1 that transmission and receiving are performed, CL2, ..., _{S 1} signal so as to correspond to CLn, _{S 2} signal, ..., a symbol to _{S n} signal Detailed explanation will be given. In addition, each control line CL1, CL2,..., CLn has a power supply for applying a termination voltage, which will be described later, to prevent distortion of the waveform of the voltage flowing in the control lines CL1, CL2,. It is an interface in SSTL (Stub Series Terminated Logic) format that conforms to DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory).

  The image forming apparatus 1 further includes a Vcc power supply 29 that applies a voltage Vcc as a first voltage to the control lines CL1, CL2,..., CLn. Specifically, the voltage applied to the control lines CL1, CL2,..., CLn by the voltage Vcc is a plurality of pull-up resistors provided corresponding to the control lines CL1, CL2,. It is applied through a pull-up resistor group 31 constituted by In the memory I / F controller 19, the Vcc power supply 29 and the pull-up resistor group 31 constitute a first voltage application unit.

  Further, the image forming apparatus 1 includes a GND power supply 33 that applies a voltage GND as a second voltage to the control lines CL1, CL2,..., CLn. Specifically, the GND power supply 33 is connected to the control lines CL1, CL2,..., CLn via a pull-down resistor group 35 including a plurality of pull-down resistors provided corresponding to the control lines CL1, CL2,. ..., connected to CLn. In the memory I / F controller 19, the GND power supply 33 and the pull-down resistor group 35 constitute a second voltage application unit.

  In addition, the image forming apparatus 1 includes a pull-up switch group 37 configured by a plurality of pull-up switch elements that switch a conduction state between the Vcc power supply 29 and the pull-up resistor group 31 in the middle portion. The pull-up switch group 37 includes pull-up switch elements corresponding to the control lines CL1, CL2,. Then, the memory I / F controller 19 selects the control lines CL1, CL2,..., CLn to which the Vcc voltage is applied by switching each pull-up switch element on and off.

  In addition, the image forming apparatus 1 includes a pull-down switch group 39 configured by a plurality of pull-down switch elements that switch a conduction state between the GND power source 33 and the pull-down resistor group 35 in the middle portion. The pull-down switch group 39 includes pull-down switch elements corresponding to the control lines CL1, CL2,. Then, the memory I / F controller 19 selects the control lines CL1, CL2,..., CLn to which the GND voltage is applied by switching each pull-down switch element on and off.

  The image forming apparatus 1 also includes a switch control unit 41 serving as an application control unit that controls each pull-up switch element constituting the pull-up switch group 37 and each pull-down switch element constituting the pull-down switch group 39. The switch control unit 41 is connected to each pull-up switch element constituting the pull-up switch group 37 and each pull-down switch element constituting the pull-down switch group 39, and each switch element is controlled under the control of the procedure management unit 23. Are individually controlled to select the control lines CL1, CL2,..., CLn to which the Vcc voltage or the GND voltage is applied. The switch control unit 41 drives the pull-up switch element connected to each control line CL1, CL2,..., CLn, thereby conducting the control line connected to the pull-down switch element and the Vcc power supply 29. Put it in a state. The switch control unit 41 drives the pull-down switch element connected to each of the control lines CL1, CL2,..., CLn, thereby conducting the control power line connected to the pull-down switch element and the GND power source 33. Put it in a state.

  Further, the memory I / F controller 19 detects the application value of the voltage applied to the control lines CL1, CL2,..., CLn and the detection input by the I / O control unit 21 through the buffer group 27. A comparison / determination unit 43 is provided as a voltage comparison unit that compares the values. Specifically, the comparison / determination unit 43 uses the detected voltage value detected by the I / O control unit 21 under the control of the procedure management unit 23 and the Vcc power supply or the GND power supply stored in the procedure management unit 23. The expected value of the voltage value to be applied to the control lines CL1, CL2,..., CLn is compared. Further, the comparison / determination unit 43 extracts control lines CL1, CL2,..., CLn in which an abnormality has occurred based on its comparison result, and stores the extraction result. Then, after comparing the detection value with the expected value for all the control lines, the cause of the abnormality is comprehensively determined. For example, if the detected voltage value and the expected value do not match, the comparison / determination unit 43 has some abnormality between the memory module 11 and the control line to which the buffer element in which the detected value is detected is connected. Judge that there is. Then, after the comparison between the detection values of all the control lines and the expected values is completed, the comparison / determination unit 43 refers to the entire comparison result and comprehensively determines the cause of the abnormality.

  The image forming apparatus 1 further includes a Vtt power source 45 that generates an intermediate potential between the Vcc power source 29 and the GND power source 33. The Vtt power supply 45 applies a termination voltage to the control lines CL1, CL2,..., CLn via the termination resistor group 47. The relationship among the voltages generated by the Vcc power supply 29, the GND power supply 33, and the Vtt power supply 45 is such that the inequality of voltage Vcc> upper threshold> voltage Vtt = voltage Vcc / 2> lower threshold> voltage GND is satisfied.

  The image forming apparatus 1 having such a configuration inspects the physical connection between the memory I / F controller 19 and the memory module 11 according to the flowchart shown in FIG. For example, the image forming apparatus 1 inspects connection when the image forming apparatus 1 is powered on.

  When a series of processes starts, the procedure management unit 23 confirms the number of control lines to be inspected in step S1. In the following, detailed description will be given assuming that the number of control lines to be inspected is n.

  Next, in step S2, the procedure management unit 23 substitutes the value 0 for the number x of the control line to be inspected in order to reset the control line to be inspected. As a result, the control line to be inspected first is selected. The procedure management unit 23 thereafter changes the control line to be inspected by incrementing the number x.

Then, the switch control unit 41 in step S3, under the control of the procedure management section 23, in order to apply a voltage to the control line S _x to be inspected, which is connected to the control line S _x to be inspected pull The up switch element is turned on, and the power supply Vcc and the control line _Sx are brought into conduction. At this time, all pull-up switch elements connected to control lines other than the control line to be inspected are turned off, while pull-down switch elements connected to the control line _Sx to be inspected are turned off. All pull-down switch elements connected to control lines other than the control line to be inspected are turned on. That is, since the control line to be inspected in these first operations is the control line S ₀ , the signal flowing through the control line S ₀ becomes a high level signal as shown in FIG. 4, and the other control lines S ₁ , S ₂ ,..., S ₁₀₂ are low level signals. Then, the I / O control unit 21 _confirms that the signals flowing through the control lines S ₁ , S ₂ ,..., S ₁₀₂ are low level signals, and the signals flowing through the other control lines are high level signals. To detect.

Next, in step S4, the comparison / determination unit 43 compares the value detected by the I / O control unit 21 with the expected value that would be detected if there was no abnormality in the control line _Sx . Specifically, the expected value in this step means that a high level signal is detected only from the control line to be inspected and a low level signal is detected from the other control lines. When no physical abnormality has occurred with respect to the control line _Sx to be inspected, the detected value matches the expected value. If the comparison / determination unit 43 determines that the detected value matches the expected value, the memory I / F controller 19 performs the process of step S5 to perform further inspection. On the other hand, if the comparison / determination unit 43 determines that the detected value does not match the expected value, since some abnormality has occurred in the control line _Sx , the process of step S6 is performed to extract such abnormality. Execute.

In step S6, the comparison / determination unit 43 extracts a location where an abnormality has occurred, that is, the control line _Sx , from the comparison result in step S4, and stores this. Thereafter, the memory I / F controller 19 executes the process of step S5 to perform further inspection.

In step S5, the switch control unit 41 is connected to a control line other than the control line to be inspected to apply a voltage to a control line other than the control line to be inspected under the control of the procedure management unit 23. The pull-up switch element is turned on, and the power supply Vcc and the control lines other than the control line to be inspected are made conductive. At this time, the pull-up switch element connected to the control line _Sx to be inspected is turned off, while the pull-down switch element connected to the control line _Sx to be inspected is turned on. All pull-down switch elements connected to control lines other than the control line are turned off. Then, the I / O control unit 21 detects that a signal flowing through the control line _Sx to be inspected becomes a low level signal, and a signal flowing through a control line other than the control line to be inspected becomes a high level signal. To do. That is, the memory I / F controller 19 reverses the signal states of the control lines CL1, CL2,..., CLn to the signal states of the control lines CL1, CL2,. To the state.

Next, in step S7, the comparison / determination unit 43 compares the value detected by the I / O control unit 21 with the expected value to be detected if the control line _Sx is not abnormal. Specifically, the expected value in this step means that a low level signal is detected only from the control line to be inspected and a high level signal is detected from the other control lines. When no physical abnormality has occurred in the control line _Sx that is the inspection target, the detected value matches the expected value. Thereafter, the memory I / F controller 19 executes the process of step S8 in order to confirm the inspection result. On the other hand, if the comparison / determination unit 43 determines that the detected value does not match the expected value, since some abnormality has occurred in the control line _Sx , the process of step S9 is performed to extract the abnormality. Execute.

In step S9, the comparison / determination unit 43 extracts a location where an abnormality has occurred, that is, the control line _Sx , from the comparison result in step S7, and stores this. Thereafter, the memory I / F controller 19 executes the process of step S8 in order to confirm the inspection result.

In step S8, the comparison / determination unit 43 confirms the inspection result. Specifically, the comparison / determination unit 43 comprehensively determines the cause of the abnormality by receiving the extraction results stored in step S6 and step S9. For example, when the comparison / determination unit 43 detects an abnormality from only one control line in step S6, the comparison / determination unit 43 causes the signal flowing through the control line _Sx where the abnormality is detected to transition from the low level signal. If not, it is determined that the control line _Sx is shorted to the ground. Further, when the comparison / determination unit 43 detects an abnormality in, for example, step S6 and step S9, the comparison / determination unit 43 determines that the control line S _x is normal for the control line S _{x ± 1} that is not checked. In this state, it is assumed that an undefined level signal is detected because the control line _Sx is detected in synchronization with another control line _Sx even though a high level signal or a low level signal should flow. It is determined that the other control line _{Sx ± 1} or the like is mixed. Then, the determination result by the comparison / determination unit 43 is output from the memory I / F controller 19 via the input / output unit 24 as information regarding the cause of the abnormality, and is supplied to the display unit 9. The display unit 9 displays the supplied information and notifies the user.

Next, in step S10, the procedure management unit 23 ends the inspection of the control line _Sx that is currently inspected, and selects the next control line _Sx . Specifically, the procedure management unit 23 increments the value x by adding the value 1 to the value x and assigning the addition result to the value x. Thereby, the procedure management unit 23 selects the control line _Sx to be inspected next.

Next, the procedure management module 23 in step S11, in order to determine whether there remains a control line to be tested, the value x is determined whether greater than the number n of the control line S _x. If there are remaining control lines to be inspected, that is, if the value x is smaller than the number n of control lines, the process of step S3 is executed to inspect even the control lines that have not been inspected. On the other hand, if the value x is greater than the number n of control lines, that is, if it is determined that the inspection for n control lines has been completed, the image forming apparatus 1 ends the series of processes.

  In this way, the image forming apparatus 1 alternately applies the voltage supplied from the Vtt power supply and the voltage of the ground GND to the control lines CL1, CL2,. The physical connection between 19 and the memory module 11 is inspected. Then, the image forming apparatus 1 actually sets the expected values to be detected by applying voltages to the control lines CL1, CL2,..., CLn for the control lines CL1, CL2,. By performing an inspection comparing the detected values, it is possible to detect an abnormality in physical connection such as a short circuit of the control lines CL1, CL2,..., CLn.

  Then, after inspecting the physical connection of the control lines CL1, CL2,..., CLn, the image forming apparatus 1 initializes the memory module 11 under the control of the CPU 3, and further performs write / read. Perform an inspection. Specifically, when initializing the memory module 11, the CPU 3 supplies a command for initializing the memory module 11 to the procedure management unit 23. Receiving this, the procedure management unit 23 supplies a memory initialization command to the I / O control unit 21. Then, the I / O control unit 21 initializes the memory module 11 by outputting a signal that transitions in a predetermined pattern to the memory module 11 via the output buffer elements that constitute the buffer group 27. In the write / read test, data written by a predetermined algorithm is written to the memory module 11 and then the data written to the memory module 11 is read. Then, the CPU 3 compares the data written to the memory module 11 with the data read from the memory module 11, and determines whether or not both are equivalent data. If any abnormality occurs at this stage, it is not an abnormality in the physical connection between the memory I / F controller 19 and the memory module 11, but there is an abnormality in the memory device itself mounted on the memory module 11. Can be judged.

  After performing such physical connection inspection and write / read inspection of the control lines CL1, CL2,..., CLn, the CPU 3 uses the memory module 11 to transmit the image transmitted from the information processing apparatus. Convert information to image data. The converted image data is supplied to the data control unit 5. Thereafter, the data control unit 5 drives the printing mechanism unit 7 and the mechanism control unit 13 based on the image data, prints an image based on the image information on a recording medium such as paper, and provides it to the user.

  As described above, according to the image forming apparatus 1 according to the first embodiment, all the control lines CL1, CL2,..., CLn connecting the memory module 11 and the memory I / F controller 19 are physically Whether or not a normal connection is normally made can be checked. Then, the image forming apparatus 1 has, for example, an abnormality such as an insertion error of the memory module 11, a connection failure between terminals due to key wear of the socket 25, a failure of the memory module 11 itself, a connection failure due to part peeling, or the like. Can determine the control line in which an abnormality has occurred and the element causing the abnormality.

  Next, a second embodiment to which the present invention is applied will be described in detail. Since the image forming apparatus according to the second embodiment has a portion having the same configuration as that of the image forming apparatus 1, detailed description of the portion is omitted, and only detailed portions are described in detail. I do.

  As shown in FIG. 5, the memory I / F controller 51 mounted on the image forming apparatus according to the second embodiment includes an I / O control unit 21, a procedure management unit 23, a buffer group 27, a switch A control unit 41 and a comparison / determination unit 43 are provided. Such a memory I / F controller 51 is connected to the memory module 55 via control lines CL1, CL2,..., CLn and a socket 53.

  The memory module 55 includes a plurality of memory devices D1, D2,..., Dn arranged on a predetermined substrate. The memory devices D1, D2,..., Dn are connected to control lines CL1, CL2,. Of such control lines CL1, CL2,..., CLn, for example, clock signals CLKP, CLKN, etc., the same kind of signals are simultaneously supplied to the memory devices D1, D2,. Is connected to each of the memory devices D1, D2,..., Dn through a common wiring CML formed on the substrate of the memory module 55. On the other hand, control lines to which signals individually supplied for the memory devices D1, D2,..., Dn are individually supplied from the socket 53 to the memory devices D1, D2,. Connected. The memory module 55 is connected to the switch control unit 41 via the wiring 57.

  The memory devices D1, D2,..., Dn each have a configuration as shown in FIG. Since the memory devices D1, D2,..., Dn all have the same configuration, in the following description, “the configuration of the memory devices D1, D2,. A detailed description will be given.

  The control lines CL1, CL2,..., CLn included in the memory device D are substantially a control line group CL-IN in which the flow is bidirectional due to the nature of the signal, and a control in which the signal flow is unidirectional. It is divided into line groups CL-OW and connected to the memory device core 59. As the control lines constituting the control line group CL-IN, there are control lines to which DQS0, DQS1,..., DQS7 signals are supplied, and control lines to which DQ0, DQ1,. . On the other hand, the control lines constituting the control line group CL-OW include CLKP signal, CLKN signal, CKE signal, CS signal, RAS signal, WE signal, A0, A1, A2,..., A13 signal, BA0, There are control lines to which the BA1 signal and DM0, DM1,. The memory device D includes a plurality of switch circuits SW1, SW2,..., SWn corresponding to the control lines CL1, CL2,. The switch circuits SW1, SW2,..., SWn are provided corresponding to the control lines CL1, CL2,. The switch circuits SW1, SW2,..., SWn are independent of the other switch circuits SW1, SW2,..., SWn, respectively, a terminal Vcc connected to the Vcc power supply, a terminal Vtt connected to the Vtt power supply, and It is formed so as to be connectable to a terminal GND connected to the ground GND. Then, the switch control circuit 63 drives the switch elements 61 of the switch circuits SW1, SW2,..., SWn based on the instruction supplied from the switch control unit 41, and controls the control lines CL1, CL2,. Switching is performed so that CLn is connected to any one of the terminal Vcc, the terminal Vtt, and the terminal GND. When the switch element 61 is driven and the switch element 61 and the terminal Vcc are connected, the control lines CL1, CL2,..., CLn corresponding to the switch element 61 are connected to the Vcc power supply via the resistor R. Connected. When the switch element 61 is driven and the switch element 61 and the terminal Vtt are connected, the control lines CL1, CL2,..., CLn corresponding to the switch element 61 are connected to the Vtt power source via the resistor R. Connected. When the switch element 61 is driven and the switch element 61 is connected to the terminal GND, the control lines CL1, CL2,..., CLn corresponding to the switch element 61 are connected to the ground GND via the resistor R. Connected. In the memory device D, the control line group CL-IN in which the signal flow is bidirectional and the control line group CL-OW in which the signal flow is unidirectional are substantially divided into the memory device. By connecting to the core 59, a delay in signal processing caused by the switching operation of the switch circuits SW1, SW2,..., SWn can be prevented.

  Such a memory module 55 has a configuration capable of selectively switching voltages applied to the control lines CL1, CL2,..., CLn inside the memory device D.

  Hereinafter, a series of operations when the image forming apparatus inspects the connection with respect to such a memory module 55 will be described in detail with reference to FIG.

  When a series of processes starts, in step S12, the procedure management unit 23 checks the number of control lines to be inspected.

  Next, in step S13, the procedure management unit 23 substitutes the value 0 for the number x of the control line to be inspected. At the same time, the procedure management unit 23 instructs the switch control unit 41 to shift to the connection check mode. Specifically, the connection check mode refers to a state in which all the switch elements 61 are connected to the terminal GND. In order to perform such a transition process, the switch control unit 41 supplies an instruction to the switch control circuit 63 to connect all the switch elements 61 to the terminal Vtt based on an instruction from the procedure management unit 23. . In response to the instruction from the switch control unit 41, the switch control circuit 63 drives the switch elements 61 so that all the switch elements 61 are connected to the terminal Vtt.

Next, in step S14, the switch control unit 41 is connected to the control line _Sx to be inspected in order to apply a voltage to the control line _Sx to be inspected under the control of the procedure management unit 23. Only the switch element 61 is connected to the Vcc power source. On the other hand, the switch control unit 41 connects the switch element 61 connected to a control line other than the control line to be inspected to the terminal GND. Thereby, the signal flowing through the control line _Sx to be inspected becomes a high level signal. On the other hand, since the switch element 61 connected to the control line other than the control line to be inspected is connected to the ground GND, the signal flowing through the control line other than the control line to be inspected is in the low level signal state. It becomes.

Next, in step S15, the comparison / determination unit 43 compares the value detected by the I / O control unit 21 with the expected value that would be detected if there was no abnormality in the control line _Sx . The expected value in this step means that a high level signal is detected only from the control line _Sx to be inspected and a low level signal is detected from the other control lines. If the comparison / determination unit 43 determines that the detected value matches the expected value, the memory I / F controller 51 executes the process of step S16 to perform further inspection. On the other hand, if the comparison / determination unit 43 determines that the detected value does not match the expected value, since some abnormality has occurred in the control line _Sx , the process of step S17 is performed to extract the abnormality. Execute.

In step S17, the comparison / determination unit 43 extracts a location where an abnormality has occurred, that is, the control line _Sx , from the comparison result in step S15, and stores this. Thereafter, the memory I / F controller 19 executes the process of step S16 in order to perform further inspection.

  In step S <b> 16, the switch control unit 41 is connected to a control line other than the control line to be inspected to apply a voltage to a control line other than the control line to be inspected under the control of the procedure management unit 23. The switch element 61 is connected to the terminal Vcc. On the other hand, the switch element 61 connected to the control line to be inspected is connected to the terminal GND. Thereby, a signal flowing through a control line other than the control line to be inspected becomes a high level signal, and a signal flowing through a control line other than the control line to be inspected becomes a low level signal.

Next, in step S18, the comparison / determination unit 43 compares the value detected by the I / O control unit 21 with the expected value that would be detected if there was no abnormality in the control line _Sx . The expected value in this step means that a high level signal is detected from a control line other than the control line to be inspected, and a low level signal is detected from the control line to be inspected. If the comparison / determination unit 43 determines that the detected value matches the expected value, the memory I / F controller 51 executes the process of step S19 to confirm the inspection result. On the other hand, if the comparison / determination unit 43 determines that the detected value does not match the expected value, some abnormality has occurred in the control line _Sx, and therefore the process of step S20 is performed to extract the abnormality. Execute.

In step S20, the comparison / determination unit 43 extracts a part where an abnormality has occurred, that is, the control line _Sx , from the comparison result in step S18, and stores this. Thereafter, the memory I / F controller 51 executes the process of step S19 in order to confirm the inspection result.

In step S19, the comparison / determination unit 43 confirms the inspection result. Specifically, the comparison / determination unit 43 comprehensively determines the cause of occurrence of the abnormality based on the extraction results stored in Step S17 and Step S20. For example, when the comparison / determination unit 43 detects an abnormality from only one control line in step S17, the comparison / determination unit 43 causes the signal flowing through the control line _Sx in which an abnormality is detected to transition from the low level signal. If not, it is determined that the control line _Sx is shorted to the ground. Further, when the comparison / determination unit 43 detects an abnormality in, for example, step S17 and step S20, the comparison / determination unit 43 determines that the control line S _x is normal for the control line S _{x ± 1} that is not the check target. despite the high level signal or a low level signal should have flowed if a state, will be synchronized with the other control line S _x, as indeterminate signal is detected, the control line S _x Are mixed with other control lines S _{x ± 1 and the} like. Then, the determination result by the comparison / determination unit 43 is supplied to the display unit 9 as information regarding the cause of the abnormality. The display unit 9 displays the supplied information and notifies the user.

Next, in step S21, the procedure management unit 23 ends the inspection of the control line _Sx that is currently inspected, and selects the next control line _Sx . Specifically, the procedure management unit 23 increments the value x by adding the value 1 to the value x and assigning the addition result to the value x. Thereby, the procedure management unit 23 selects the control line _Sx to be inspected next.

  Next, in step S22, the procedure management unit 23 determines whether or not the value x is larger than the number n of control lines in order to determine whether or not there are remaining control lines to be inspected. Then, when there are remaining control lines to be inspected, that is, when the value x is smaller than the number n of control lines, the process of step S14 is executed to inspect the control lines that have not been inspected. On the other hand, if the value x is larger than the number n of control lines, that is, if it is determined that the inspection for n control lines has been completed, the image forming apparatus ends a series of processes.

  Then, after inspecting the physical connection of the control lines, the image forming apparatus initializes the memory module 55 under the control of the CPU 3, and further performs a write / read inspection.

  As described above, according to the image forming apparatus of the second embodiment, the connection state of the pin to pin between the memory I / F controller 51 and the memory module 55 can be inspected, and the image forming apparatus 1 It is possible to obtain higher accuracy than the inspection by the above. In addition, since the memory module 55 incorporates a pull-down resistor, a pull-up resistor, and a termination resistor, it is possible to prevent the wiring on the substrate from being congested and perform smart wiring.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit of the present invention.

  For example, in the above-described embodiment, the detailed description is given using the memory modules 11 and 55 and the memory I / F controllers 15 and 51 provided in the color printer as an example of the image forming apparatus. Needless to say, the present invention is also applicable to an image forming apparatus having a memory control device such as an MFP, a facsimile, or a copying apparatus.

  In the above-described embodiment, after checking the connection state for all the control lines and confirming the inspection result, determining the cause and displaying the cause on the display unit 9 However, when the image forming apparatus determines that the expected value does not match the detected value in steps S4, S7, S15, and S18 of the above-described processing, for example, the control line that is the inspection target is abnormal. May be displayed on the display unit 9.

  In the above-described embodiment, the inspection method has been described in detail with the memory modules 11 and 55 connected to the image forming apparatus through the socket 25 as an example. The present invention is not applied only to such memory modules 11 and 55. The above-described connection test is performed on various memory control devices such as a memory element arranged on a circuit board and connected to the same bus as a socket, or a memory having only a configuration in which memory elements are directly arranged on a circuit board. Applicable.

  Further, in the above-described embodiment, the connection inspection is performed by transitioning the signal flowing for each control line. However, the inspection may be performed by collectively transitioning signals for a plurality of control lines. .

1 is a block diagram of an image forming apparatus shown as a first embodiment, and is a diagram for explaining a configuration of the image forming apparatus. FIG. 2 is a block diagram of a memory I / F controller provided in the image forming apparatus, and is a diagram for explaining a configuration of the memory I / F controller. FIG. FIG. 3 is a flowchart when the image forming apparatus inspects a physical connection between a memory I / F controller and a memory module. It is a figure which shows the waveform of the signal which flows into the control line which connects the memory I / F controller and a memory module. FIG. 4 is a block diagram of a memory I / F controller provided in an image forming apparatus shown as a second embodiment, and is a diagram for explaining a configuration of the memory I / F controller. It is a block diagram of the memory device of the memory module connected with the memory I / F controller, and is a diagram for explaining the configuration of the memory device. FIG. 3 is a flowchart when the image forming apparatus inspects a physical connection between a memory I / F controller and a memory module.

Explanation of symbols

1 Image forming apparatus 3 CPU
5 Data control unit 7 Printing mechanism unit 9 Display unit 11, 55 Memory module 13 Mechanism control unit 15 CPU I / F controller 17 External I / F controller 19, 51 Memory I / F controller 21 I / O control unit 23 Procedure management unit 25, 53 Socket 27 Buffer group 29 Vcc power supply 31 Pull-up resistor group 33 GND power supply 35 Pull-down resistor group 37 Pull-up switch group 39 Pull-down switch group 41 Switch control unit 43 Comparison / determination unit 61 Switch element 63 Switch control circuit

Claims (5)

A plurality of controls connected to a memory device for a first voltage applying unit that applies a first voltage and a second voltage applying unit that applies a second voltage different from the first voltage An application control unit that alternately applies the first voltage or the second voltage to any one of the control lines;
A voltage detection unit for detecting the first voltage and the second voltage applied to the plurality of control lines by the application control unit;
A comparison unit for comparing the detected values of the first voltage and the second voltage detected by the voltage detection unit with the application values of the first voltage and the second voltage;
A determination unit that determines an abnormality cause of the plurality of control lines based on a comparison result by the comparison unit;
A cause output unit that outputs information on the cause of abnormality determined by the determination unit;
A memory control device. The application control unit includes:
A first terminal connected to the first voltage application unit, or a second terminal connected to the second voltage application unit, formed in the memory device, corresponding to the plurality of control lines; By driving a switch unit that connects any one of the terminals and the control line, the first voltage application unit or the second voltage application unit to any one of the plurality of control lines. Alternately applying a voltage or the second voltage;
The memory control device according to claim 1. A first terminal connected to a first voltage application unit that is provided corresponding to a plurality of control lines and applies a first voltage to the control lines, or the first control terminals connected to the plurality of control lines. A switch unit for connecting any one of the second terminals connected to the second voltage application unit for applying a second voltage different from the voltage to the control line;
A memory device having a memory device core for storing signals input via the plurality of control lines;
By driving the switch unit, the first voltage or the second voltage is alternately applied to any of the plurality of control lines from the first voltage application unit or the second voltage application unit. An application control unit to apply,
A voltage detection unit for detecting the first voltage and the second voltage applied to the plurality of control lines by the application control unit;
A comparison unit for comparing the detected values of the first voltage and the second voltage detected by the voltage detection unit with the application values of the first voltage and the second voltage;
A determination unit that determines an abnormality cause of the plurality of control lines based on a comparison result by the comparison unit;
A memory control device having a cause output unit that outputs information on the cause of abnormality determined by the determination unit;
A memory device. The plurality of control lines are substantially divided into a control line through which a unidirectional signal flows and a control line through which a bidirectional signal flows, and is connected to the memory device;
The memory device according to claim 3. An image conversion unit that converts input image information into printable image data;
A memory device for storing information when the image conversion unit converts the image information into the image data;
A memory control device that inspects the connection state of the memory device and determines the cause of abnormality based on the inspection result;
A plurality of control lines connecting the memory device and the memory control device;
A first voltage applying unit for applying a predetermined first voltage to the control line;
A second voltage applying unit that applies a second voltage different from the first voltage to the control line;
An inspection result output unit that outputs a determination result of the memory control device;
The memory control device
The first voltage applied by the first voltage application unit or the second voltage applied by the second voltage application unit to any one of the plurality of control lines. An application control unit that alternately applies any one of the voltages of
A voltage detection unit for detecting the first voltage and the second voltage applied to the plurality of control lines by the application control unit;
A comparison unit for comparing the detected values of the first voltage and the second voltage detected by the voltage detection unit with the applied values of the first voltage and the second voltage;
A determination unit that determines an abnormality cause of the plurality of control lines based on a comparison result by the comparison unit;
A comparison result output unit that outputs a determination result by the determination unit to the inspection result output unit;
An image forming apparatus.