JP2008067494A - Power supply device and image forming device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply device that further reduces power consumption during standby, in a power supply configuration composed of one ACDC converter and a DCDC converter provided at the post stage of the ACDC converter. <P>SOLUTION: The power supply device is provided with the ACDC converter, which converts an AC current into a DC current while being inputted with the AC current so as to supply the DC current to a first load and the DCDC converter; a first control means for controlling the output voltage of the ACDC converter; the DCDC converter for reducing a voltage of the ACDC converter so as to supply it to a second load; a switch means for opening/closing between an output terminal of the ACDC converter and an output terminal of the DCDC converter; and a second control means for controlling each operation of the ACDC converter, the DCDC converter, and the switch means. The first control means controls the output voltage of the ACDC converter so as to make it as a reference voltage. The second control means controls so as to reduce the reference voltage (S84), to close the switch means (S86), and to stop the operation of the DCDC converter (S87) during sleep mode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power supply device suitable for an image forming apparatus, and more particularly to reduction of power consumption in a sleep state where load current is low.

  As a method for reducing power consumption as an energy saving method of a conventional power supply device, as described in Patent Document 1 and Patent Document 2, a technique for intermittently oscillating an ACDC converter to reduce an oscillation frequency and reduce a switching loss is known. It has been. Furthermore, in a power supply configuration in which the output voltage of the ACDC converter is stepped down by the DCDC converter, a method for increasing the efficiency of the DCDC converter by reducing the ACDC voltage during sleep that does not require a driving voltage is generally known. ing.

The conventional example described above will be described below.
FIG. 3 is a diagram illustrating a circuit configuration of a power supply device in a conventional image forming apparatus, and illustrates an operation using a partial resonance type flyback power supply and a DCDC converter as an example.
Reference numeral 1 denotes a commercial AC power source. Reference numeral 6 denotes a diode bridge that rectifies the voltage of the AC power supply 1, and reference numeral 7 denotes a primary smoothing capacitor that smoothes the voltage rectified by the diode bridge 6. Reference numeral 8 denotes an FET for switching the primary winding 10 of the power transformer 9 for converting the primary voltage into the secondary voltage, and the on / off timing of switching is controlled by the power controller 11 for controlling the power. Here, a package including the FET 8 and the power supply control unit 11 is referred to as a power supply IC 25.

  The current flowing through the FET 8 is primary smoothed from the primary winding 10 via the drain terminal 3 of the FET 8 and the GND terminal / source terminal 4 of the power supply control unit 11 and the current detection resistor 23 for detecting overcurrent. It flows to the negative terminal of the capacitor 7. The GND terminal / source terminal 4 of the power supply IC 25 is based on the GND reference of the power supply control unit 11, and each terminal of the power supply control unit 11 operates based on the GND terminal / source terminal 4 of the power supply IC 25.

  Subsequently, a voltage is generated at both ends of the current detection resistor 23 due to the current flowing through the current detection resistor 23, and the voltage is applied to the bottom detection / OCP terminal 20 that detects the overcurrent of the power supply control unit 11 and the noise removal resistor 24. Is transmitted via. Reference numeral 41 denotes a noise removing capacitor for constituting the noise removing resistor 24 and the primary low-pass filter. The bottom detection / OCP terminal 20 also serves as a function of detecting the timing at which the minimum voltage of the resonance voltage waveform generated between the drain and source of the FET 8 is generated at the turn-off timing of the FET 8.

  Immediately after the power supply is turned on, the power supply control unit 11 is activated by the activation resistor 12 that supplies the initial power of the power supply control unit 11, and the FET 8 is driven to generate a voltage at the secondary output. At the same time, power is continuously supplied to the power supply control unit 11 by the auxiliary winding 13 that supplies power to the power supply terminal 42 of the power supply control unit 11. The voltage output from the auxiliary winding 13 is rectified and smoothed by the control unit rectifier diode 15 and the control unit smoothing capacitor 16, and then stepped down by the control unit regulator 63 and input to the power source terminal 42 for the control unit.

  When the power supply terminal 42 reaches a set voltage or higher, the power supply terminal 42 enters a shutdown state in which oscillation of the power supply IC 25 stops. In order to use the shutdown function for protection of abnormal voltage on the secondary side, a short-circuit overvoltage operation transistor 64 is provided between the input and output to turn on and shut down when the voltage on the secondary side rises in some abnormal state. Is to operate. Reference numeral 98 denotes a base resistance of the overvoltage operation transistor 64.

  Next, the operation of the overvoltage operation transistor 64 will be described. Reference numeral 65 denotes an abnormal voltage protection operational amplifier for supplying a current to the abnormal voltage protection photocoupler 67 when the voltage on the secondary side becomes equal to or higher than the set voltage 66. Reference numeral 68 denotes an abnormal voltage protection photocoupler current setting resistor for setting a current to the abnormal voltage protection photocoupler 67. When the secondary voltage rises and exceeds the set voltage, the abnormal voltage protection operational amplifier 65 causes a current to flow through the abnormal voltage protection photocoupler 67, the overvoltage operation transistor 64 is turned on, and the voltage at the power supply terminal 42 increases. The power supply IC 25 is shut down.

  Subsequently, the pseudo-resonant operation of the flyback operation will be described. From the timing when the FET 8 is turned off, the drain-source voltage of the FET 8 resonates with the inductance of the primary winding 10 and the capacitance of the resonant capacitor 19. In order to shape only the positive voltage signal from the resonance waveform, it is rectified by the bottom detection signal rectifier diode 17. Then, the minimum value of the resonance voltage waveform of the power supply control unit 11 is detected via the bottom detection signal protection resistor 21 and the OCP signal protection diode 22 that reduce the voltage so that an excessive voltage is not applied to the power supply control unit 11. Output to the bottom detection / OCP terminal 20. The power supply control unit 11 detects the timing when the positive voltage of the signal input to the bottom detection / OCP terminal 20 becomes 0 V, and turns on the FET 8 after a predetermined time has elapsed from the timing. Reference numeral 26 denotes a bottom point adjustment capacitor for setting a minute delay time of the resonance voltage waveform, and is adjusted so that the FET 8 is turned on at the timing when the voltage generated between the drain and source of the FET 8 becomes the smallest. Is.

  The secondary current output from the secondary winding 18 is rectified by the secondary rectifier diode 27 for rectifying the secondary current and smoothed by the secondary smoothing capacitor 28.

  Next, the operation of the power control unit 11 will be described. Reference numeral 29 denotes a voltage control operational amplifier for negatively feeding back the error amount of the output voltage on the secondary side. The secondary side voltage is divided by the secondary side voltage dividing resistor 30 and compared with the voltage of the reference voltage Zener diode 31 that generates the reference voltage of the secondary side voltage. The reference voltage Zener diode 31 is supplied with a bias current by a bias resistor 32 and generates a constant voltage. Reference numerals 33 and 34 denote phase compensation resistors and capacitors, and reference numeral 35 denotes a gain adjustment resistor for adjusting the gain of the voltage control operational amplifier. Reference numeral 36 denotes a photocoupler for transmitting the voltage error amount on the secondary side to the primary side. A current inversely proportional to the output voltage of the voltage control operational amplifier 29 flows to the light emitting diode of the photocoupler 36, and the phototransistor receives the light from the light emitting diode and transmits an error amount to the primary side. The current output from the phototransistor passes through the photocoupler current limiting resistor 37 for limiting the amount of current to the power supply control unit 11, and the error amount is transmitted to the FB terminal 38 of the power supply control unit 11. Reference numerals 39 and 40 denote primary-side phase compensation resistors and capacitors.

  The circuit described above is an ACDC converter unit, and is mainly used as a power source for a drive unit of the image forming apparatus.

  Subsequently, a DCDC converter that generates a control voltage based on the output voltage of the ACDC converter will be described. Reference numeral 69 denotes a DCDC converter control IC that controls the DCDC converter. The output voltage of the DCDC converter is divided by the DCDC converter output detection resistor 70 and negatively fed back to the DCDC converter control IC 69. The DCDC converter control IC 69 compares the negatively fed back voltage with the internally set voltage, and determines the ON width of the DCDC converter transistor 71 which is the main switch of the DCDC converter. When the DCDC converter transistor 71 is turned on, a current flows into the choke coil 72 that temporarily stores energy. When the DCDC converter transistor 71 is turned off, a regenerative current flows through the regenerative diode 73 by the back electromotive force of the choke coil 72. . Reference numeral 99 denotes a smoothing capacitor for smoothing the current flowing out of the choke coil 72. Here, the output voltage of the ACDC converter is referred to as a driving voltage 74, and the output voltage of the DCDC converter is referred to as a control voltage 75.

Next, the operation during sleep will be described. In the image forming apparatus, the driving voltage 74 is necessary for high-power driving such as a motor during printing operation, and does not require the voltage generated by the ACDC converter during non-printing. In this specification, the non-printing state is referred to as a sleep state. Therefore, in the sleep state, the voltage of the reference voltage Zener diode 31 is decreased in order to lower the control voltage of the voltage control operational amplifier 29 from the ASIC 76 that controls the image forming apparatus. Here, the power supply efficiency of the DCDC converter is improved because the voltage difference between the input and output is reduced, and the power consumption of the entire apparatus is reduced. Further, by intermittently turning off the current flowing from the ASIC 76 to the photocoupler 36, the ACDC converter is forcibly turned on / off at regular intervals, and the switching loss generated in the DCDC converter transistor 71 is reduced. The power consumption during sleep is reduced by the method described above.
Japanese Patent Laid-Open No. 11-215819 JP 2000-228873 A

However, the conventional example described above has the following problems.
In the conventional example, the voltage of the ACDC converter can be lowered in the sleep state to increase the efficiency of the DCDC converter and the power consumption can be reduced. However, since the DCDC converter is not stopped, power for controlling the DCDC converter is generated.

  In particular, in an image forming apparatus, the proportion of waiting time is much larger than that during printing when the power is turned on, so it is a proposition to reduce the power consumption by providing a sleep mode during the waiting time. It has become. As a method for greatly reducing power consumption during standby, a method is known in which driving voltage and control voltage are generated from separate ACDC converters, and driving ACDC converter is stopped during standby to reduce power consumption. Yes. However, since two ACDC converters are required, the configuration is expensive.

  The present invention has been made under such circumstances, and in a power supply configuration in which one ACDC converter and a DCDC converter are provided in a subsequent stage, a power supply apparatus and an image that can further reduce power consumption during standby It is an object of the present invention to provide a forming apparatus.

  In order to solve the above problems, in the present invention, the power supply device is configured as described in the following (1), and the image forming apparatus is configured as described in the following (2).

(1) An ACDC converter that inputs AC power, converts it to DC power, and supplies it to the first load and the DCDC converter;
First control means for controlling the output voltage of the ACDC converter;
The DCDC converter that receives the output of the ACDC converter, reduces the voltage, and supplies the reduced voltage to the second load;
Switch means for opening and closing between the output terminal of the ACDC converter and the output terminal of the DCDC converter via a diode that secures a minimum voltage at which the DCDC converter operates;
A second control unit that controls operations of the ACDC converter, the DCDC converter, and the switch unit;
The first control means controls the output voltage of the ACDC converter to be a reference voltage,
The second control means controls to reduce the reference voltage, close the switch means, and stop the operation of the DCDC converter in the sleep mode.
Power supply.

(2) An image forming apparatus including the power supply device according to (1),
Supplying power from the ACDC converter to the drive unit of the image forming apparatus as the first load;
An image forming apparatus that supplies power from the DCDC converter to a control unit of the image forming apparatus that is the second load.

  According to the present invention, standby power consumption can be further reduced in a power supply configuration in which one ACDC converter and a subsequent DCDC converter are provided.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to an embodiment of a power supply device in an image forming apparatus.

FIG. 1 is a diagram illustrating a circuit configuration of a “power supply device in an image forming apparatus” according to a first embodiment.
In the circuit configuration of this power supply device, a circuit to be described later is added to the circuit configuration of the conventional example shown in FIG. Here, the added circuit will be mainly described. The description of the conventional example in FIG. 3 is used for the configuration and operation of circuits other than the added circuit.

  In FIG. 1, reference numeral 77 denotes a controller that receives image data from a host computer (not shown) and converts it into raster data. When the ASIC 76 receives a print signal from the controller 77, the ASIC 76 starts a series of print operations. Further, after a time set from the host computer has elapsed or when the sleep state is entered at the set time, a sleep signal is transmitted to the ASIC 76. Further, when the controller 77 receives a print signal in the sleep state, the controller 77 transmits a sleep release to the ASIC 76, and the ASIC 76 releases the sleep of the image forming apparatus.

  When the controller 77 receives the sleep release completion signal, it transmits a print signal to the ASIC 76 and starts a series of printing operations. Reference numeral 78 denotes a sleep transistor that connects the drive voltage and the control voltage, and is turned on / off by a signal from the ASIC 76. 79 is a gate bias resistor that generates the gate voltage of the sleep transistor 78, and 80 is a bias transistor that supplies current to the gate bias resistor 79. Reference numeral 100 denotes a base resistance of the bias transistor 80. Reference numeral 81 denotes a voltage securing diode array for assuring the minimum voltage at which the DCDC converter operates with respect to the control voltage. Reference numeral 82 denotes a voltage monitoring voltage dividing resistor for detecting the driving voltage 74 and outputs the divided value to the A / D terminal of the ASIC 76.

  Reference numeral 96 denotes an ACDC converter intermittent transmission transistor for intermittent transmission (intermittent operation) of the ACDC converter. When the transistor is turned on by the ASIC 76, a current is supplied to the photocoupler 36 to forcibly turn off the FET 8. In the intermittent operation, the ACDC converter can reduce the oscillation frequency by repeatedly forcibly turning on / off intermittently, so that the power consumption generated in the FET 8 can be reduced. Reference numeral 97 denotes a base resistance of the ACDC converter intermittent transmission transistor 96.

FIG. 2 is a flowchart showing the circuit operation during sleep according to this embodiment.
When the ASIC 76 receives the sleep signal from the controller 77 (see step 83 (referred to as S83 in the figure, the same applies hereinafter)), the ASIC 76 decreases the reference voltage of the reference voltage Zener diode 31 (S84). Eventually, when the drive voltage decreases and the ASIC 76 detects that the drive voltage has become equal to or lower than the set value (S85), the DCDC converter transistor 71 is turned on, and then the sleep transistor 78 is turned on (S86). The DCDC converter transistor 71 is turned on by applying an excessive voltage to the control voltage line 75 when the drive voltage line 74 and the control voltage line 75 are connected by turning on the sleep transistor 78. Is to prevent. Further, the voltage value to be set needs to be set to a level at which an element connected to the control voltage 75 line is not destroyed.

  Subsequently, since the drive voltage 74 line and the control voltage 75 line are connected, power can be supplied from the ACDC converter to the components connected to the control voltage 75 line. There is no need to supply. Therefore, the ASIC 76 outputs a signal for stopping the driving of the DCDC converter to the DCDC converter control IC 69 via the signal line 110 to stop the function of the DCDC converter (S87). Subsequently, the ASIC 76 causes the ACDC converter to oscillate intermittently to reduce the power consumption of the ACDC converter (S88). The above state is a sleep state, and power consumption in this embodiment is minimized.

  Thereafter, when a print signal is transmitted from the host computer to the controller 77, the controller 77 transmits a sleep release signal to the ASIC 76 (S89). When the ASIC 76 receives the sleep release signal, the ASIC 76 stops the intermittent oscillation of the ACDC converter (S90) and drives the DCDC converter again (S91). Subsequently, the sleep transistor 78 is turned off (S92), the drive voltage 74 line and the control voltage 75 line are disconnected, and the ASIC 76 increases the reference voltage of the reference voltage Zener diode 31 and increases the drive power supply voltage (S93). ). When the ASIC 76 detects that the drive voltage 74 line has reached the voltage before the transition to the sleep state (S94), the ASIC 76 transmits a sleep release signal to the controller 77 and the preparation for accepting the print operation is completed (S95).

  As described above, according to the present embodiment, in the sleep state, since the voltage can be directly supplied from the ACDC converter to the control unit, the driving of the DCDC converter can be stopped and the power consumption of the apparatus can be reduced. Can do. In addition, since the ACDC converter can be intermittently driven with a pulse width optimized for the minimum power consumption, the power consumption of the ACDC converter can be kept small.

  Further, it detects that the voltage of the driving voltage line has become a set value, and connects and disconnects the driving voltage line and the control voltage line. Therefore, problems such as an excessive voltage being applied to the elements connected to the control voltage line and resetting of the elements connected to the drive voltage line with a low voltage do not occur.

Circuit diagram of Example 1 Flowchart showing the operation of the first embodiment. Circuit diagram of conventional example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Commercial AC power supply 9 Power supply transformer 10 Primary winding 11 Power supply control part 69 DCDC converter control IC
71 DC / DC Converter Transistor 76 ASIC
78 Transistor for Sleep

Claims (4)

An ACDC converter that inputs AC power, converts it to DC power, and supplies the DC power to the first load and the DCDC converter;
First control means for controlling the output voltage of the ACDC converter;
The DCDC converter that receives the output of the ACDC converter, reduces the voltage, and supplies the reduced voltage to the second load;
Switch means for opening and closing between the output terminal of the ACDC converter and the output terminal of the DCDC converter via a diode that secures a minimum voltage at which the DCDC converter operates;
A second control unit that controls operations of the ACDC converter, the DCDC converter, and the switch unit;
The first control means controls the output voltage of the ACDC converter to be a reference voltage,
The second control means controls to reduce the reference voltage, close the switch means, and stop the operation of the DCDC converter in the sleep mode.
A power supply device characterized by that. The power supply device according to claim 1,
The power supply apparatus according to claim 2, wherein the second control unit controls the ACDC converter to intermittently operate in a sleep mode. The power supply device according to claim 1 or 2,
The power supply apparatus according to claim 2, wherein the second control means opens and closes the switch means when the output voltage of the ACDC converter is a predetermined value. An image forming apparatus comprising the power supply device according to claim 1,
Supplying power from the ACDC converter to the drive unit of the image forming apparatus as the first load;
An image forming apparatus, wherein power is supplied from the DCDC converter to a control unit of the image forming apparatus which is the second load.

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