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JP2008066440A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2008066440A
JP2008066440A JP2006241292A JP2006241292A JP2008066440A JP 2008066440 A JP2008066440 A JP 2008066440A JP 2006241292 A JP2006241292 A JP 2006241292A JP 2006241292 A JP2006241292 A JP 2006241292A JP 2008066440 A JP2008066440 A JP 2008066440A
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insulating film
pad
metal pattern
connection hole
wiring
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Shinji Nishiura
信二 西浦
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/05089—Disposition of the additional element
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent a pad from being peeled off upon wire bonding by preventing cracking in an insulating film on a lower layer of the pad during probing for inspection or during wire bonding, and also to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device includes one insulating film 112 formed on a semiconductor substrate 101, one metallic pattern 116 formed on the insulating film 112, another insulating film 117 formed on the insulating film 112 and the metallic pattern 116, another metallic pattern 119 formed on the insulating film 117 to be opposed to the metallic pattern 116, and connection holes 120b made in the insulating film 117 to be arranged in the periphery of the metallic pattern 119. The metallic patterns 116 and 119 are directly contacted with each other via the connection holes 120b to be electrically connected to each other. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置およびその製造方法に関し、特に、多層配線を有する半導体集積回路上のボンディングパッド構造およびその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a bonding pad structure on a semiconductor integrated circuit having a multilayer wiring and a manufacturing method thereof.

近年、半導体装置の多機能化や、大容量化、システム化によってチップサイズが増大傾向にあり、チップコストを下げるためにチップサイズの縮小化が急務となってきている。チップサイズを縮小するためには、プロセスルールの縮小、回路の簡素化等様々な方法があるが、レイアウト的な手法の１つとして、半導体素子が形成された領域の上にボンディングパッドを形成するいわゆるＰＯＥ（Pad on element）技術が考えられる。ところが、従来のボンディングパッド構成では、ウェハテスト工程におけるテスタのプローバの衝撃、または後工程でチップをパッケージに組立する際のボンディング工程におけるワイヤーボンダのボンディングヘッドの衝撃によって、ボンディングパッド下の層間絶縁膜にクラックが発生し、さらにクラックが基板上の半導体素子まで達し、ショートが起こる可能性があったため、これを抑制しない限りＰＯＥ技術は採用し難いものであった。   In recent years, the chip size has been increasing due to the multi-function, large capacity, and systematization of semiconductor devices, and it has become urgent to reduce the chip size in order to reduce the chip cost. In order to reduce the chip size, there are various methods such as reduction of process rules and simplification of circuits. As one of layout methods, a bonding pad is formed on a region where a semiconductor element is formed. So-called POE (Pad on element) technology can be considered. However, in the conventional bonding pad configuration, the interlayer insulating film under the bonding pad is affected by the impact of the tester prober in the wafer test process or the impact of the bonding head of the wire bonder in the bonding process when assembling the chip into the package in the subsequent process. Since cracks occurred and the cracks reached the semiconductor elements on the substrate and could cause a short circuit, it was difficult to adopt the POE technique unless this was suppressed.

以下、クラックが基板に達するのを防止したＰＯＥ型ボンディングパッド構造の従来例を、図９、図１０を用いて説明する。   Hereinafter, a conventional example of a POE type bonding pad structure that prevents cracks from reaching the substrate will be described with reference to FIGS.

図９は、半導体素子が形成された領域の上に、特許文献１に記載されている構成のボンディングパッドが形成されたＰＯＥ型パッドの断面構造図であり、４層配線構造の半導体装置に適用された例である。   FIG. 9 is a cross-sectional structure diagram of a POE type pad in which a bonding pad having a configuration described in Patent Document 1 is formed on a region where a semiconductor element is formed, and is applied to a semiconductor device having a four-layer wiring structure. This is an example.

図９に示すように、シリコン基板２０１の表面には素子分離絶縁膜２０２と前記素子分離絶縁膜２０２によって区画された半導体素子２０３が形成されている。シリコン基板２０１上には、素子分離絶縁膜２０２、半導体素子２０３を覆うように、第１の層間絶縁膜２０４が形成されている。第１の層間絶縁膜２０４には、拡散層２０３ａと後述する第１の配線２０７とを電気的に接続する第１の接続孔２０５が形成され、接続孔２０５には第１のプラグ２０６が埋め込まれている。   As shown in FIG. 9, an element isolation insulating film 202 and a semiconductor element 203 partitioned by the element isolation insulating film 202 are formed on the surface of the silicon substrate 201. A first interlayer insulating film 204 is formed on the silicon substrate 201 so as to cover the element isolation insulating film 202 and the semiconductor element 203. A first connection hole 205 is formed in the first interlayer insulating film 204 to electrically connect the diffusion layer 203a and a first wiring 207 described later. A first plug 206 is embedded in the connection hole 205. It is.

また、第１の層間絶縁膜２０４の上には、第１の配線２０７が形成されており、さらに、第１の配線２０７を覆うように第２の層間絶縁膜２０８が形成されている。第２の層間絶縁膜２０８には、第１の配線２０７と後述する第２の配線２１１とを電気的に接続する第２の接続孔２０９が形成され、接続孔２０９には第２のプラグ２１０が埋め込まれている。   A first wiring 207 is formed on the first interlayer insulating film 204, and a second interlayer insulating film 208 is formed so as to cover the first wiring 207. A second connection hole 209 is formed in the second interlayer insulating film 208 to electrically connect the first wiring 207 and a second wiring 211 described later, and the second plug 210 is formed in the connection hole 209. Is embedded.

また、第２の層間絶縁膜２０８の上には、第２の配線２１１と金属パターン２１２が形成されており、さらに、第２の配線２１１と金属パターン２１２を覆うように第３の層間絶縁膜２１３が形成されている。第３の層間絶縁膜２１３には、第２の配線２１１と後述する第３の配線２１６とを電気的に接続する第３の接続孔１１４が形成され、接続孔１１４には第３のプラグ１１５が埋め込まれている。   A second wiring 211 and a metal pattern 212 are formed on the second interlayer insulating film 208, and a third interlayer insulating film is formed so as to cover the second wiring 211 and the metal pattern 212. 213 is formed. In the third interlayer insulating film 213, a third connection hole 114 that electrically connects the second wiring 211 and a third wiring 216 described later is formed, and a third plug 115 is formed in the connection hole 114. Is embedded.

また、第３の層間絶縁膜２１３の上には、第３の配線２１６が形成されており、さらに、第３の配線２１６を覆うように第４の層間絶縁膜２１７が形成されている。第４の層間絶縁膜２１７には、第３の配線２１６と後述する第４の配線２２０およびパッド２２１を電気的に接続する第４の接続孔２１８が形成され、接続孔２１８には第４のプラグ２１９が埋め込まれている。   A third wiring 216 is formed on the third interlayer insulating film 213, and a fourth interlayer insulating film 217 is formed so as to cover the third wiring 216. The fourth interlayer insulating film 217 is provided with a fourth connection hole 218 that electrically connects the third wiring 216 to a later-described fourth wiring 220 and the pad 221, and the connection hole 218 includes a fourth connection hole 218. A plug 219 is embedded.

また、第４の層間絶縁膜２１７の上には、第４の配線２２０と、パッド２２１が形成されている。第４の層間絶縁膜２１７の上には、第４の配線２２０およびパッド２２１を覆うように保護膜２２２が形成されており、保護膜２２２には、パッド２２１を露出させるパッド開口部２２３が形成されている。   A fourth wiring 220 and a pad 221 are formed on the fourth interlayer insulating film 217. A protective film 222 is formed on the fourth interlayer insulating film 217 so as to cover the fourth wiring 220 and the pad 221, and a pad opening 223 that exposes the pad 221 is formed in the protective film 222. Has been.

ここで、パッド２２１は、第３の層間絶縁膜２１３および第４の層間絶縁膜２１７を介して金属パターン２１２と対向しており、金属パターン２１２はフローティング状態にある。   Here, the pad 221 is opposed to the metal pattern 212 through the third interlayer insulating film 213 and the fourth interlayer insulating film 217, and the metal pattern 212 is in a floating state.

このように構成されたボンディングパッド部分では、プロービングやワイヤボンディングによって第４の層間絶縁膜２１７および第３の層間絶縁膜２１３にクラックが発生した場合でも、クラックは金属パターン２１２で止められる。また、金属パターン２１２はフローティング状態にあるため、パッド２２１にかかった応力の影響を極小にでき、第２の層間絶縁膜２０８、第１の層間絶縁膜２０４にクラックが発生するのを防止できる。したがって、クラックがシリコン基板２０１に達するのを防止できる。   In the bonding pad portion configured as described above, even when a crack occurs in the fourth interlayer insulating film 217 and the third interlayer insulating film 213 by probing or wire bonding, the crack is stopped by the metal pattern 212. Further, since the metal pattern 212 is in a floating state, the influence of the stress applied to the pad 221 can be minimized, and the occurrence of cracks in the second interlayer insulating film 208 and the first interlayer insulating film 204 can be prevented. Therefore, the crack can be prevented from reaching the silicon substrate 201.

図１０は、メタルパターンによってボンディングパッド下層の絶縁膜に発生したクラックが半導体基板に達するのを防止したＰＯＥ型パッドの他の一例である。   FIG. 10 shows another example of the POE type pad in which the crack generated in the insulating film under the bonding pad due to the metal pattern is prevented from reaching the semiconductor substrate.

図１０に示すように、シリコン基板３０１の表面には素子分離絶縁膜３０２と前記素子分離絶縁膜３０２によって区画された半導体素子３０３が形成されている。シリコン基板３０１上には、素子分離絶縁膜３０２、半導体素子３０３を覆うように、第１の層間絶縁膜３０４が形成されている。第１の層間絶縁膜３０４には、拡散層３０３ａと後述する第１の配線３０７とを電気的に接続する第１の接続孔３０５が形成され、接続孔３０５には第１のプラグ３０６が埋め込まれている。   As shown in FIG. 10, an element isolation insulating film 302 and a semiconductor element 303 partitioned by the element isolation insulating film 302 are formed on the surface of the silicon substrate 301. A first interlayer insulating film 304 is formed on the silicon substrate 301 so as to cover the element isolation insulating film 302 and the semiconductor element 303. In the first interlayer insulating film 304, a first connection hole 305 that electrically connects the diffusion layer 303a and a first wiring 307 described later is formed, and the first plug 306 is embedded in the connection hole 305. It is.

また、第１の層間絶縁膜３０４の上には、第１の配線３０７が形成されており、さらに、第１の配線３０７を覆うように第２の層間絶縁膜３０８が形成されている。第２の層間絶縁膜３０８には、第１の配線３０７と後述する第２の配線３１１とを電気的に接続する第２の接続孔３０９が形成され、接続孔３０９には第２のプラグ３１０が埋め込まれている。   A first wiring 307 is formed on the first interlayer insulating film 304, and a second interlayer insulating film 308 is formed so as to cover the first wiring 307. The second interlayer insulating film 308 is provided with a second connection hole 309 that electrically connects the first wiring 307 and a second wiring 311 described later, and the second plug 310 is formed in the connection hole 309. Is embedded.

また、第２の層間絶縁膜３０８の上には、第２の配線３１１と第１のパッド３１２が形成されており、さらに、第２の配線３１１と第１のパッド３１２を覆うように第３の層間絶縁膜３１３が形成されている。第３の層間絶縁膜３１３には、第２の配線３１１と後述する第３の配線３１６とを電気的に接続する第３の接続孔３１４ａが、また第１のパッド３１２と後述する第２のパッド３１７とを電気的に接続する第３の接続孔３１４ｂが形成され、接続孔３１４ａ，３１４ｂには第３のプラグ３１５が埋め込まれている。   In addition, a second wiring 311 and a first pad 312 are formed on the second interlayer insulating film 308, and the third wiring 311 and the first pad 312 are covered so as to cover the third wiring 311 and the first pad 312. An interlayer insulating film 313 is formed. The third interlayer insulating film 313 includes a third connection hole 314a that electrically connects the second wiring 311 and a third wiring 316 described later, and a second pad 312 described later. A third connection hole 314b that electrically connects to the pad 317 is formed, and a third plug 315 is embedded in the connection holes 314a and 314b.

また、第３の層間絶縁膜３１３の上には、第３の配線３１６と第２のパッド３１７が形成されており、さらに、第３の配線３１６を覆うように第４の層間絶縁膜３１８が形成されている。第４の層間絶縁膜３１８には、第３の配線３１６と後述する第４の配線３２１とを電気的に接続する第４の接続孔３１９ａが、また第２のパッド３１７と後述する第３のパッド３２２を電気的に接続する第４の接続孔３１９ｂが形成され、接続孔３１９a，３１９ｂには第４のプラグ３２０が埋め込まれている。   A third wiring 316 and a second pad 317 are formed on the third interlayer insulating film 313, and a fourth interlayer insulating film 318 is formed so as to cover the third wiring 316. Is formed. The fourth interlayer insulating film 318 includes a fourth connection hole 319a that electrically connects the third wiring 316 and a fourth wiring 321 described later, and a second pad 317 and a third wiring described later. A fourth connection hole 319b for electrically connecting the pad 322 is formed, and a fourth plug 320 is embedded in the connection holes 319a and 319b.

また、第４の層間絶縁膜３１８の上には、第４の配線３２１と、第３のパッド３２２が形成されている。第４の層間絶縁膜３１８の上には、第４の配線３２１および第３のパッド３２２を覆うように保護膜３２３が形成されており、保護膜３２３には、第３のパッド３２２を露出させるパッド開口部３２４が形成されている。   A fourth wiring 321 and a third pad 322 are formed on the fourth interlayer insulating film 318. A protective film 323 is formed on the fourth interlayer insulating film 318 so as to cover the fourth wiring 321 and the third pad 322, and the third pad 322 is exposed to the protective film 323. A pad opening 324 is formed.

ここで、第２のパッド３１７はパッド開口部３２４の下層を除いた領域に形成され、第３のパッド３２２と第１のパッド３１２は、第３の層間絶縁膜３１３および第４の層間絶縁膜３１８を介して対向している。また、第３のパッド３２２と第１のパッド３１２は、周囲部に形成された第４のプラグ３２０と第２のパッド３１７と第３のプラグ３１５と通じて電気的に接続されている。   Here, the second pad 317 is formed in a region excluding the lower layer of the pad opening 324, and the third pad 322 and the first pad 312 are the third interlayer insulating film 313 and the fourth interlayer insulating film. Opposite via 318. In addition, the third pad 322 and the first pad 312 are electrically connected through the fourth plug 320, the second pad 317, and the third plug 315 formed in the peripheral portion.

このように構成されたパッドにおいても、プロービングやワイヤボンディングによって第４の層間絶縁膜３１８および第３の層間絶縁膜３１３に発生したクラックは、第１のパッド３１２で止められる。また、第３のパッド３２２と第１のパッド３１２はパッド開口３２４の周囲部のみで接続されているため、プロービングまたはボンディングの際に第３のパッド３２２にかかる負荷がそのまま第１のパッド３１２まで及ぶことはなく、第２の層間絶縁膜３０８にクラックが発生するのを防止できる。したがって、クラックが半導体基板３０１に達するのを防止できる。
特開２００１−７１１３号公報 特開平１１−１８６３２０号公報 Even in the pad configured as described above, cracks generated in the fourth interlayer insulating film 318 and the third interlayer insulating film 313 by probing or wire bonding are stopped by the first pad 312. Further, since the third pad 322 and the first pad 312 are connected only at the periphery of the pad opening 324, the load applied to the third pad 322 during probing or bonding is directly applied to the first pad 312. Therefore, the second interlayer insulating film 308 can be prevented from cracking. Therefore, the crack can be prevented from reaching the semiconductor substrate 301.
Japanese Patent Laid-Open No. 2001-7113 Japanese Patent Laid-Open No. 11-186320

しかしながら、図９、図１０に示したように従来のボンディングパッドの構成では、金属パターン２１２とパッド２２１（図９）、第１のパッド３１２と第３のパッド３２２（図１０）は少なくとも２層以上の層間絶縁膜を介して形成する必要があった。１層の層間絶縁膜しか介さない場合、パッド２２１（図９）、第３のパッド３２２（図１０）がはがれ易く、ワイヤボンディング不良や半導体パッケージのアセンブリ特性低下などの問題が発生することがあった。これは、クラックの発生によってボンディングパッド部の強度が低下していることに加え、パッド２２１（図９）、第３のパッド３２２（図１０）と第４のプラグ（タングステンプラグ）２１９，３２０との接続強度が弱いためである。   However, as shown in FIGS. 9 and 10, in the conventional bonding pad configuration, the metal pattern 212 and the pad 221 (FIG. 9), the first pad 312 and the third pad 322 (FIG. 10) are at least two layers. It was necessary to form through the above interlayer insulating film. If only one interlayer insulating film is interposed, the pad 221 (FIG. 9) and the third pad 322 (FIG. 10) are easy to peel off, which may cause problems such as defective wire bonding and degradation of assembly characteristics of the semiconductor package. It was. This is because, in addition to the strength of the bonding pad portion being reduced due to the occurrence of cracks, the pad 221 (FIG. 9), the third pad 322 (FIG. 10), and the fourth plugs (tungsten plugs) 219 and 320 This is because the connection strength is weak.

この場合、ボンディングパッド下に形成される集積回路において、使用可能な配線数が減少するため集積度が低下し、ＰＯＥ化してもチップサイズを十分に縮小できない問題があった。すなわち、図９の例では、金属パターン２１２とパッド２２１との間に２層の層間絶縁膜２１３，２１７が介装されており、金属パターン２１２の下には２層の層間絶縁膜２０４，２０８しかないことから、使用可能な配線は第１の配線２０７のみとなり、集積度が低下する。また、図１０の例では、第１のパッド３１２と第３のパッド３２２との間に２層の層間絶縁膜３１３，３１８が介装されており、第１のパッド３１２の下には２層の層間絶縁膜３０４，３０８しかないことから、使用可能な配線は第１の配線３０７のみとなり、集積度が低下する。   In this case, in the integrated circuit formed under the bonding pad, the number of usable wires is reduced, so that the degree of integration is lowered, and there is a problem that the chip size cannot be sufficiently reduced even if POE is used. That is, in the example of FIG. 9, two layers of interlayer insulating films 213 and 217 are interposed between the metal pattern 212 and the pad 221, and two layers of interlayer insulating films 204 and 208 are disposed under the metal pattern 212. Therefore, only the first wiring 207 can be used, and the degree of integration decreases. In the example of FIG. 10, two layers of interlayer insulating films 313 and 318 are interposed between the first pad 312 and the third pad 322, and two layers are provided below the first pad 312. Therefore, only the first wiring 307 can be used, and the degree of integration is reduced.

本発明の請求項１に記載の半導体装置は、半導体基板上に形成された一の絶縁膜と、前記一の絶縁膜の上に形成された一の金属パターンと、前記一の絶縁膜および前記一の金属パターンの上に形成された他の絶縁膜と、前記他の絶縁膜の上に前記一の金属パターンと対向して形成された他の金属パターンと、前記他の金属パターンの周囲に配置して、前記他の絶縁膜中に形成された接続孔とを備え、前記接続孔を通じて前記一の金属パターンと前記他の金属パターンを直接接触させて電気的に接続することを特徴とする。   According to a first aspect of the present invention, there is provided a semiconductor device comprising: one insulating film formed on a semiconductor substrate; one metal pattern formed on the one insulating film; the one insulating film; Another insulating film formed on one metal pattern, another metal pattern formed on the other insulating film so as to face the one metal pattern, and around the other metal pattern And a connection hole formed in the other insulating film, wherein the one metal pattern and the other metal pattern are in direct contact with each other and electrically connected through the connection hole. .

本発明の請求項２に記載の半導体装置は、請求項１記載の半導体装置において、前記接続孔のアスペクト比が１以下であることを特徴とする。   A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, characterized in that an aspect ratio of the connection hole is 1 or less.

本発明の請求項３に記載の半導体装置は、請求項１記載の半導体装置において、前記接続孔が前記他の金属パターンの周囲を取り巻く溝からなることを特徴とする。   A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, characterized in that the connection hole comprises a groove surrounding the other metal pattern.

本発明の請求項４に記載の半導体装置は、請求項１記載の半導体装置において、前記接続孔の底部に露出した、前記一の金属パターンの表面が凹凸形状になっていることを特徴とする。   According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the surface of the one metal pattern exposed at the bottom of the connection hole has an uneven shape. .

本発明の請求項５に記載の半導体装置の製造方法は、半導体基板上に一の絶縁膜を形成する工程と、前記一の絶縁膜の上に一の金属パターンを形成する工程と、前記一の絶縁膜と前記一の金属パターンの上に他の絶縁膜を形成する工程と、前記他の絶縁膜中に接続孔を形成する工程と、前記他の絶縁膜の上と前記接続孔の内に他の金属パターンを形成する工程とを含み、前記接続孔は前記他の金属パターンの周囲に配置され、前記接続孔を通じて前記一の金属パターンと前記他の金属パターンを直接接触させて電気的に接続することを特徴とする。   According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a single insulating film on a semiconductor substrate; forming a single metal pattern on the single insulating film; Forming another insulating film on the insulating film and the one metal pattern; forming a connection hole in the other insulating film; and on the other insulating film and in the connection hole And forming the other metal pattern on the periphery of the other metal pattern, and electrically connecting the one metal pattern and the other metal pattern directly through the connection hole. It is characterized by connecting to.

本発明の請求項６に記載の半導体装置の製造方法は、半導体基板上に一の絶縁膜を形成する工程と、前記一の絶縁膜の上に一の金属パターンを形成する工程と、前記一の絶縁膜と前記一の金属パターンの上に他の絶縁膜を形成する工程と、前記他の絶縁膜中に接続孔を形成する工程と、前記接続孔の底部に露出した前記一の金属パターン表面を凹凸形状にする工程と、前記他の絶縁膜の上と前記接続孔の内に他の金属パターンを形成する工程とを含み、前記接続孔は前記他の金属パターンの周囲に配置され、前記接続孔を通じて前記一の金属パターンと前記他の金属パターンを直接接触させて電気的に接続することを特徴とする。   According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a single insulating film on a semiconductor substrate; forming a single metal pattern on the single insulating film; Forming another insulating film on the insulating film and the one metal pattern, forming a connection hole in the other insulating film, and the one metal pattern exposed at the bottom of the connection hole A step of forming an uneven surface, and a step of forming another metal pattern on the other insulating film and in the connection hole, the connection hole being disposed around the other metal pattern, The one metal pattern and the other metal pattern are in direct contact with each other and electrically connected through the connection hole.

本発明の半導体装置およびその製造方法によると、他の金属パターンの下層に他の絶縁膜を介して一の金属パターンが形成されているので、プロービングまたはワイヤボンディングの際に他の絶縁膜にクラックが発生しても、一の金属パターンで止められる。また、一の金属パターンと他の金属パターンは、他の金属パターン周囲部に設けられた接続孔を通じてのみ接続されているので、プロービングまたはワイヤボンディングの際に他の金属パターンにかかる負荷がそのまま一の金属パターンまで及ぶことはない。これにより、一の絶縁膜にクラックが発生するのを防止できる。   According to the semiconductor device and the manufacturing method thereof of the present invention, since one metal pattern is formed below another metal pattern via another insulating film, the other insulating film is cracked during probing or wire bonding. Even if this occurs, it can be stopped with a single metal pattern. In addition, since one metal pattern and another metal pattern are connected only through connection holes provided around the other metal pattern, the load applied to the other metal pattern during probing or wire bonding is kept as it is. The metal pattern does not extend to. Thereby, it is possible to prevent cracks from occurring in one insulating film.

また、他の金属パターンは、接続孔に埋め込まれて他の絶縁膜を覆い囲むように形成されているため、従来の平坦な下地の上に形成された金属パターンに比べてはがれに対する強度が向上する。また、一の金属パターンと他の金属パターンを直接接続することにより、そして接続部分における一の金属パターンの表面を凹凸形状にすることにより、一の金属パターンと他の金属パターンが密接に接続され、他の金属パターンのはがれに対する強度がより一層向上する。   In addition, the other metal pattern is embedded in the connection hole so as to cover the other insulating film, so the strength against peeling is improved compared to the conventional metal pattern formed on a flat base. To do. In addition, by directly connecting one metal pattern and another metal pattern, and by making the surface of the one metal pattern at the connection part uneven, the one metal pattern and the other metal pattern are closely connected. Further, the strength against peeling of other metal patterns is further improved.

本発明の半導体装置およびその製造方法によると、検査時のプロービング又はワイヤボンディングの際に、パッド下層の層間絶縁膜にクラックが達するのを防止でき、さらにワイヤボンディングでのパッドはがれを防止でき、パッド下層の領域を有効に活用してチップ面積を縮小でき、チップコストを低減できる。   According to the semiconductor device and the manufacturing method thereof of the present invention, it is possible to prevent cracks from reaching the interlayer insulating film under the pad during probing or wire bonding at the time of inspection, and further to prevent pad peeling during wire bonding. The chip area can be reduced by effectively utilizing the lower layer area, and the chip cost can be reduced.

以下、本発明の実施形態を、図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

（第１の実施形態）
図１は、本発明の第１の実施形態に係るボンディングパッド構造を示す断面図である。 (First embodiment)
FIG. 1 is a cross-sectional view showing a bonding pad structure according to a first embodiment of the present invention.

図１に示すように、シリコン基板１０１の表面には素子分離絶縁膜１０２と前記素子分離絶縁膜１０２によって区画された半導体素子１０３が形成されている。半導体素子１０３には、拡散層１０３ａ、ゲート絶縁膜１０３ｂ、ゲート電極１０３ｃ、サイドウォール１０３ｄが形成されている。シリコン基板１０１上には、素子分離絶縁膜１０２、半導体素子１０３を覆うように、第１の層間絶縁膜１０４が形成されている。第１の層間絶縁膜１０４には、拡散層１０３ａと後述する第１の配線１０７とを電気的に接続する第１の接続孔１０５が形成され、接続孔１０５には第１のプラグ１０６が埋め込まれている。   As shown in FIG. 1, an element isolation insulating film 102 and a semiconductor element 103 partitioned by the element isolation insulating film 102 are formed on the surface of a silicon substrate 101. In the semiconductor element 103, a diffusion layer 103a, a gate insulating film 103b, a gate electrode 103c, and a sidewall 103d are formed. A first interlayer insulating film 104 is formed on the silicon substrate 101 so as to cover the element isolation insulating film 102 and the semiconductor element 103. A first connection hole 105 is formed in the first interlayer insulating film 104 to electrically connect the diffusion layer 103a and a first wiring 107 described later. A first plug 106 is embedded in the connection hole 105. It is.

また、第１の層間絶縁膜１０４の上には、第１の配線１０７が形成されており、さらに、第１の配線１０７を覆うように第２の層間絶縁膜１０８が形成されている。第２の層間絶縁膜１０８には、第１の配線１０７と後述する第２の配線１１１とを電気的に接続する第２の接続孔１０９が形成され、接続孔１０９には第２のプラグ１１０が埋め込まれている。   A first wiring 107 is formed on the first interlayer insulating film 104, and a second interlayer insulating film 108 is formed so as to cover the first wiring 107. A second connection hole 109 that electrically connects the first wiring 107 and a second wiring 111 to be described later is formed in the second interlayer insulating film 108, and the second plug 110 is formed in the connection hole 109. Is embedded.

また、第２の層間絶縁膜１０８の上には、第２の配線１１１が形成されており、さらに、第２の配線１１１を覆うように第３の層間絶縁膜１１２が形成されている。第３の層間絶縁膜１１２には、第２の配線１１１と後述する第３の配線１１５と第１のパッド１１６を電気的に接続する第３の接続孔１１３が形成され、接続孔１１３には第３のプラグ１１４が埋め込まれている。   A second wiring 111 is formed on the second interlayer insulating film 108, and a third interlayer insulating film 112 is formed so as to cover the second wiring 111. The third interlayer insulating film 112 is formed with a third connection hole 113 that electrically connects the second wiring 111, a third wiring 115 described later, and the first pad 116. A third plug 114 is embedded.

また、第３の層間絶縁膜１１２の上には、第３の配線１１５および第１のパッド１１６が形成されており、さらに、第３の配線１１５および第１のパッド１１６を覆うように第４の層間絶縁膜１１７が形成されている。第４の層間絶縁膜１１７には、第３の配線１１５および第１のパッド１１６と、後述する第４の配線１１８および第２のパッド１１９を電気的に接続する第４の接続孔１２０ａ，１２０ｂが形成されている。   In addition, a third wiring 115 and a first pad 116 are formed on the third interlayer insulating film 112, and a fourth wiring is formed so as to cover the third wiring 115 and the first pad 116. An interlayer insulating film 117 is formed. The fourth interlayer insulating film 117 includes fourth connection holes 120a and 120b that electrically connect the third wiring 115 and the first pad 116 to a fourth wiring 118 and a second pad 119 described later. Is formed.

また、第４の層間絶縁膜１１７の上には、第３の配線１１５と第４の接続孔１２０ａを通して直接接続する第４の配線１１８が形成されていると共に、第１のパッド１１６と第４の層間絶縁膜１１７を介して対抗し、さらに第１のパッド１１６と接続孔１２０ｂを通して直接接続する第２のパッド１１９が形成されている。第４の層間絶縁膜１１７の上には、第４の配線１１８および第２のパッド１１９を覆うように保護膜１２１が形成されており、保護膜１２１には、第２のパッド１１９を露出させるパッド開口部１２２が形成されている。   On the fourth interlayer insulating film 117, a fourth wiring 118 that is directly connected to the third wiring 115 through the fourth connection hole 120a is formed, and the first pad 116 and the fourth wiring are connected. A second pad 119 is formed which is opposed to the first interlayer insulating film 117 and is directly connected to the first pad 116 through the connection hole 120b. A protective film 121 is formed on the fourth interlayer insulating film 117 so as to cover the fourth wiring 118 and the second pad 119, and the second pad 119 is exposed to the protective film 121. A pad opening 122 is formed.

なお、請求項１と本実施形態の関係は、半導体基板がシリコン基板１０１、一の絶縁膜が第３の層間絶縁膜１１２、一の金属パターンが第１のパッド１１６、他の絶縁膜が第４の層間絶縁膜１１７、他の金属パターンが第２のパッド１１９、接続孔が第４の接続孔１２０ｂにそれぞれ対応している。   The relationship between claim 1 and this embodiment is that the semiconductor substrate is the silicon substrate 101, one insulating film is the third interlayer insulating film 112, one metal pattern is the first pad 116, and the other insulating film is the first. The fourth interlayer insulating film 117, the other metal patterns correspond to the second pads 119, and the connection holes correspond to the fourth connection holes 120b, respectively.

また、本実施形態において、第１のパッド１１６は、第３のプラグ１１４を通して第２の配線１１１と接続し、下層の半導体素子１０３と電気的に導通しているが、第１のパッド１１６と第３の配線１１５を直接に接続させてもよいし、第２のパッド１１９と第４の配線１１８を直接に接続させてもよい。   In this embodiment, the first pad 116 is connected to the second wiring 111 through the third plug 114 and is electrically connected to the lower semiconductor element 103. The third wiring 115 may be directly connected, or the second pad 119 and the fourth wiring 118 may be directly connected.

ここで、第１のプラグ１０６、第２のプラグ１１０、第３のプラグ１１４はタングステンよりなる。また、第１の配線１０７、第２の配線１１１、第３の配線１１５、第４の配線１１８、第１のパッド１１６、第２のパッド１１９は、アルミニウムを主層とし下層からチタン、窒化チタン、アルミニウム、窒化チタンの積層メタルからなる。   Here, the first plug 106, the second plug 110, and the third plug 114 are made of tungsten. The first wiring 107, the second wiring 111, the third wiring 115, the fourth wiring 118, the first pad 116, and the second pad 119 have aluminum as a main layer and titanium and titanium nitride from the lower layer. Made of laminated metal of aluminum, titanium nitride.

図２は、第１の実施形態のパッドの平面図である。   FIG. 2 is a plan view of the pad according to the first embodiment.

図２に示すように、第１のパッド１１６は第２のパッド１１９より大きくなるように形成されている。また、接続孔１２０ｂはパッド開口部１２２の周囲に形成されている。   As shown in FIG. 2, the first pad 116 is formed to be larger than the second pad 119. Further, the connection hole 120 b is formed around the pad opening 122.

本実施形態のパッド構造では、第１のパッド１１６と第２のパッド１１９がパッド開口部１２２の周囲部のみで接続されているため、プロービングまたはボンディングの際に第２のパッド１１９にかかる負荷がそのまま第１のパッド１１６まで及ぶことはなく、第３の層間絶縁膜１１２にクラックが発生するのを防止できる。詳細に説明すると、プロービングまたはボンディングの際に第２のパッド１１９にかかる応力は、パッド開口部１２２の中心付近を主にして、図１に示した矢印１２３の方向に加えられる。加えられた負荷が大きい場合には、第４の層間絶縁膜１１７にクラックが発生し、これによって応力が分散され、第１のパッド１１６には大きな負荷が及ばない。第４の層間絶縁膜１１７にクラックが発生した場合、クラックは第１のパッド１１６で止められる。つまり、本実施形態の第１のパッド１１６は、前記従来例で、図９中に示した金属パターン２１２や、図１０中に示した第１のパッド３１２と同様の機能を有し、第３の層間絶縁膜１１２以下にクラックが発生するのを防止できる。   In the pad structure of the present embodiment, since the first pad 116 and the second pad 119 are connected only at the periphery of the pad opening 122, the load applied to the second pad 119 during probing or bonding is reduced. It does not reach the first pad 116 as it is, and it is possible to prevent the third interlayer insulating film 112 from cracking. More specifically, the stress applied to the second pad 119 during probing or bonding is applied mainly in the vicinity of the center of the pad opening 122 in the direction of the arrow 123 shown in FIG. When the applied load is large, cracks are generated in the fourth interlayer insulating film 117, whereby stress is dispersed and the first pad 116 does not receive a large load. When a crack occurs in the fourth interlayer insulating film 117, the crack is stopped by the first pad 116. That is, the first pad 116 of this embodiment has the same function as the metal pattern 212 shown in FIG. 9 and the first pad 312 shown in FIG. The generation of cracks in the interlayer insulating film 112 and below can be prevented.

一方、第２のパッド１１９は接続孔１２０ｂに埋め込まれて第４の層間絶縁膜１１７を覆い囲むように形成されているため、従来の平坦な下地の上に形成されたパッドよりはがれに対する強度が向上している。さらに、第２のパッド１１９と第１のパッド１１６とは、第２のパッド１１９を構成するチタン膜と第１のパッド１１６のアルミニウム膜とで密接に接続されているため、前記第２の従来例（図１０）に示されるように第２のパッドのチタン膜とタングステンプラグで接続されたパッドよりはがれに対する強度が向上している。   On the other hand, since the second pad 119 is formed so as to be embedded in the connection hole 120b so as to cover the fourth interlayer insulating film 117, the second pad 119 has higher strength against peeling than the pad formed on the conventional flat base. It has improved. Further, since the second pad 119 and the first pad 116 are closely connected to each other by the titanium film constituting the second pad 119 and the aluminum film of the first pad 116, the second conventional art. As shown in the example (FIG. 10), the strength against peeling is improved compared to the pad of the second pad connected by the titanium film and the tungsten plug.

このように、本実施形態のボンディングパッド構造によれば、多層配線の上から２層の配線でパッドを構成でき、パッド下層の層間絶縁膜にクラックが達するのを防止でき、さらにパッドはがれに対する強度を向上でき、パッド下層の領域を有効活用できるためチップ面積を縮小でき、チップコストを低減できる。すなわち、第１のパッド１１６上に第２のパッド１１９が直接接続されており、第１のパッド１１６下には３層の層間絶縁膜１０４，１０８，１１２が存在し、第１の配線１０７と第２の配線１１１が使用可能であるため、集積度が低下せず、ＰＯＥ化してチップサイズを十分に縮小できる。   As described above, according to the bonding pad structure of the present embodiment, the pad can be constituted by two layers of wiring from the top of the multilayer wiring, cracks can be prevented from reaching the interlayer insulating film below the pad, and the strength against the pad peeling can be prevented. And the area under the pad can be effectively utilized, so that the chip area can be reduced and the chip cost can be reduced. That is, the second pad 119 is directly connected to the first pad 116, and the three layers of the interlayer insulating films 104, 108, and 112 exist below the first pad 116. Since the second wiring 111 can be used, the degree of integration does not decrease, and the chip size can be sufficiently reduced by POE.

なお、接続孔１２０ｂの径が小さいと、孔の側壁部において第２のパッド１１９の膜厚が極端に薄くなり、パッドはがれに対する強度が低下する。このため接続孔１２０ｂは深さと径寸法の比（アスペクト比）を１以下にすることが望ましい。本実施形態では、接続孔１２０ｂの深さは約１μｍなので、孔の径を１μｍ以上に設定している。   When the diameter of the connection hole 120b is small, the film thickness of the second pad 119 is extremely thin at the side wall portion of the hole, and the strength against the pad peeling is reduced. Therefore, it is desirable that the connection hole 120b has a depth / diameter dimension ratio (aspect ratio) of 1 or less. In this embodiment, since the depth of the connection hole 120b is about 1 μm, the diameter of the hole is set to 1 μm or more.

（第２の実施形態）
図３に示す平面図を用いて、本発明の第２の実施形態を説明する。この実施形態で示されるパッドの断面構造は、第１の実施形態と同様であるので、ここでは第１の実施形態と異なる点のみを図３に示すパッド平面図を用いて説明する。 (Second Embodiment)
A second embodiment of the present invention will be described with reference to the plan view shown in FIG. Since the cross-sectional structure of the pad shown in this embodiment is the same as that of the first embodiment, only the differences from the first embodiment will be described with reference to the pad plan view shown in FIG.

図３に示すように、本実施形態では第１の実施形態の接続孔１２０ｂを、パッド開口部１２２を取り巻く接続溝１２０ｃとしている。接続溝１２０ｃによって、パッドはがれに対する強度が第１の実施形態より向上する。また、第４の層間絶縁膜１１７に発生したクラックが横方向に広がった場合でも、接続溝１２０ｃに埋め込まれた第２のパッド１１９によって止めることができる。   As shown in FIG. 3, in the present embodiment, the connection hole 120 b of the first embodiment is a connection groove 120 c surrounding the pad opening 122. Due to the connection groove 120c, the strength against pad peeling is improved as compared with the first embodiment. Further, even when a crack generated in the fourth interlayer insulating film 117 spreads in the lateral direction, it can be stopped by the second pad 119 embedded in the connection groove 120c.

このように、本実施形態のボンディングパッド構造によれば、多層配線の上から２層の配線でパッドを構成でき、パッド下層の層間絶縁膜とさらにパッド領域以外の層間絶縁膜にクラックが達するのを防止でき、さらにパッドはがれに対する強度を第１の実施形態より向上でき、パッド下層の領域を有効活用できるためチップ面積を縮小でき、チップコストを低減できる。   As described above, according to the bonding pad structure of the present embodiment, a pad can be configured with two layers of wiring from the top of the multilayer wiring, and cracks reach the interlayer insulating film under the pad and the interlayer insulating film other than the pad region. Further, the strength against pad peeling can be improved as compared with the first embodiment, and the area under the pad can be effectively used, so that the chip area can be reduced and the chip cost can be reduced.

（第３の実施形態）
図４に示す第１のパッドと第２のパッドの接続部を拡大した断面図を用いて、本発明の第３の実施形態を説明する。この実施形態で示されるパッド部全体の断面構造および平面構造は、第１の実施形態および第２の実施形態と同様であるから、ここでは第１の実施形態および第２の実施形態と異なる点のみを図４に示す断面図を用いて説明する。 (Third embodiment)
A third embodiment of the present invention will be described with reference to an enlarged cross-sectional view of the connection portion between the first pad and the second pad shown in FIG. The cross-sectional structure and planar structure of the entire pad portion shown in this embodiment are the same as those in the first embodiment and the second embodiment, and are different here from the first embodiment and the second embodiment. Only will be described with reference to the cross-sectional view shown in FIG.

図４には、接続孔１２０ｂまたは接続溝１２０ｃ部分を通して第１のパッド１１６と第２のパッド１１９が接続されている構造が拡大して示されている。図４において、１１６ａは第１のパッド１１６を構成するアルミニウム膜、１１６ｂはアルミニウム粒境界、１１６ｃは窒化チタン膜であり、１１９ａ，１１９ｂ，１１９ｃはそれぞれ第２のパッド１１９を構成するチタン膜、窒化チタン膜、アルミニウム膜である。   FIG. 4 shows an enlarged structure in which the first pad 116 and the second pad 119 are connected through the connection hole 120b or the connection groove 120c. In FIG. 4, 116a is an aluminum film constituting the first pad 116, 116b is an aluminum grain boundary, 116c is a titanium nitride film, 119a, 119b, and 119c are a titanium film and nitride that constitute the second pad 119, respectively. Titanium film and aluminum film.

図４に示すように、本実施形態ではアルミニウム膜１１６ａの表面部分が、凹凸形状に加工されている。凹凸は、他の接続孔底部のアルミニウム膜より大きく、特にアルミニウム粒の境界部１１６ｂで約２０ｎｍ以上の凹みが形成されている。この凹凸形状にすることによって、アルミニウム膜１１６ａとチタン膜１１９ａはより密接に接続される。   As shown in FIG. 4, in the present embodiment, the surface portion of the aluminum film 116a is processed into an uneven shape. The unevenness is larger than the aluminum film at the bottom of the other connection hole, and in particular, a recess of about 20 nm or more is formed at the boundary portion 116b of the aluminum grain. By making this uneven shape, the aluminum film 116a and the titanium film 119a are more closely connected.

このように、本実施形態のボンディングパッド構造によれば、第１の実施形態および第２の実施形態と同様の効果を有しながら、さらにパッドはがれに対する強度を向上できる。したがって、パッド下層の領域を有効活用できるためチップ面積を縮小でき、チップコストを低減できる。   Thus, according to the bonding pad structure of this embodiment, the strength against pad peeling can be further improved while having the same effects as those of the first embodiment and the second embodiment. Therefore, the area under the pad can be used effectively, so that the chip area can be reduced and the chip cost can be reduced.

（第４の実施形態）
図５〜図８は、第４の実施形態のボンディングパッドの製造方法を示す工程順の断面図である。本実施形態は、第３の実施形態のボンディングパッドの製造方法に関するものである。 (Fourth embodiment)
5 to 8 are cross-sectional views in order of steps showing the method for manufacturing the bonding pad of the fourth embodiment. The present embodiment relates to a bonding pad manufacturing method according to the third embodiment.

まず、図５に示す工程で、シリコン基板１０１の表面に素子分離絶縁膜１０２と前記素子分離絶縁膜１０２によって区画された半導体素子１０３を形成する。半導体素子１０３には、拡散層１０３ａ、ゲート絶縁膜１０３ｂ、ゲート電極１０３ｃ、サイドウォール１０３ｄが形成されている。次に、シリコン基板１０１上に、素子分離絶縁膜１０２、半導体素子１０３を覆うように、第１の層間絶縁膜１０４を形成する。次に、第１の層間絶縁膜１０４に、拡散層１０３ａと後述する第１の配線１０７とを電気的に接続する第１の接続孔１０５を形成し、続いて接続孔１０５に第１のプラグ１０６を埋め込む。   First, in the step shown in FIG. 5, the element isolation insulating film 102 and the semiconductor element 103 partitioned by the element isolation insulating film 102 are formed on the surface of the silicon substrate 101. In the semiconductor element 103, a diffusion layer 103a, a gate insulating film 103b, a gate electrode 103c, and a sidewall 103d are formed. Next, a first interlayer insulating film 104 is formed on the silicon substrate 101 so as to cover the element isolation insulating film 102 and the semiconductor element 103. Next, a first connection hole 105 for electrically connecting the diffusion layer 103a and a first wiring 107 described later is formed in the first interlayer insulating film 104, and then a first plug is formed in the connection hole 105. 106 is embedded.

次に、第１の層間絶縁膜１０４の上に、第１の配線１０７を形成し、さらに、第１の配線１０７を覆うように第２の層間絶縁膜１０８を形成する。次に、第２の層間絶縁膜１０８に、第１の配線１０７と後述する第２の配線１１１とを電気的に接続する第２の接続孔１０９を形成し、続いて接続孔１０９に第２のプラグ１１０を埋め込む。   Next, a first wiring 107 is formed on the first interlayer insulating film 104, and a second interlayer insulating film 108 is formed so as to cover the first wiring 107. Next, a second connection hole 109 that electrically connects the first wiring 107 and a second wiring 111 to be described later is formed in the second interlayer insulating film 108, and then the second connection hole 109 is formed with a second connection hole 109. The plug 110 is embedded.

次に、第２の層間絶縁膜１０８の上に、第２の配線１１１を形成し、さらに、第２の配線１１１を覆うように第３の層間絶縁膜１１２を形成する。次に、第３の層間絶縁膜１１２に、第２の配線１１１と後述する第３の配線１１５および第１のパッド１１６を電気的に接続する第３の接続孔１１３を形成し、接続孔１１３には第３のプラグ１１４を埋め込む。   Next, a second wiring 111 is formed on the second interlayer insulating film 108, and a third interlayer insulating film 112 is formed so as to cover the second wiring 111. Next, a third connection hole 113 is formed in the third interlayer insulating film 112 to electrically connect the second wiring 111 to a third wiring 115 and a first pad 116 described later. Is embedded with a third plug 114.

次に、図６に示す工程で、第３の層間絶縁膜１１２の上に、金属層を形成しフォトリソグラフィによるレジスト（図示せず）をマスクにして前記金属層をパターニングして、第３の配線１１５および第１のパッド１１６を形成する。さらに、第３の配線１１５および第１のパッド１１６を覆うように第４の層間絶縁膜１１７を形成する。次いで、フォトリソグラフィによるレジスト（図示せず）をマスクにして、第４の層間絶縁膜１１７をドライエッチングして、第３の配線１１５と後述する第４の配線１１８とを、第１のパッド１１６と後述する第２のパッド１１９とを、それぞれ電気的に接続する第４の接続孔１２０ａ，１２０ｂを形成する。ここで、接続孔１２０ｂの直径は、前記第１の接続孔１０５、第２の接続孔１０９、第３の接続孔１１３の直径にくらべて大きく、孔のアスペクト比が１以下程度の大きなサイズに開口する。   Next, in the step shown in FIG. 6, a metal layer is formed on the third interlayer insulating film 112, and the metal layer is patterned using a resist (not shown) by photolithography as a mask to form a third layer. A wiring 115 and a first pad 116 are formed. Further, a fourth interlayer insulating film 117 is formed so as to cover the third wiring 115 and the first pad 116. Next, using the resist (not shown) by photolithography as a mask, the fourth interlayer insulating film 117 is dry-etched so that the third wiring 115 and a fourth wiring 118 described later are connected to the first pad 116. And a second pad 119 described later are formed as fourth connection holes 120a and 120b. Here, the diameter of the connection hole 120b is larger than the diameters of the first connection hole 105, the second connection hole 109, and the third connection hole 113, and the hole has an aspect ratio of about 1 or less. Open.

次に、図７に示す工程で、アルゴンイオンミリング法により接続孔１２０ｂ底部に露出した第１のパッド１１６のアルミニウム表面をエッチングして、表面を凹凸形状にする。本工程において、アルミニウム粒の境界部１１６ｂが特にエッチングが速く進行するため深い凹部が形成される。   Next, in the step shown in FIG. 7, the aluminum surface of the first pad 116 exposed at the bottom of the connection hole 120b is etched by an argon ion milling method to make the surface uneven. In this step, since the etching proceeds particularly fast in the boundary portion 116b of the aluminum grain, a deep recess is formed.

次に、図８に示す工程で、第４の層間絶縁膜１１７および第４の接続孔１２０ａ，１２０ｂの上に、第４の配線１１８および第２のパッド１１９となる金属層を形成する。続いて、フォトリソグラフィによるレジスト（図示せず）をマスクにして、前記金属層をパターニングして、第４の配線１１８および第２のパッド１１９を形成する。最後に、第４の層間絶縁膜１１７と、第４の配線１１８と、第２のパッド１１９とを覆うように保護膜１２１を形成した後、保護膜１２１に第２のパッド１１９を露出させるパッド開口部１２２を形成する。   Next, in the step shown in FIG. 8, a metal layer to be the fourth wiring 118 and the second pad 119 is formed on the fourth interlayer insulating film 117 and the fourth connection holes 120a and 120b. Subsequently, the metal layer is patterned using a photolithography resist (not shown) as a mask to form the fourth wiring 118 and the second pad 119. Finally, a protective film 121 is formed so as to cover the fourth interlayer insulating film 117, the fourth wiring 118, and the second pad 119, and then the pad that exposes the second pad 119 to the protective film 121. Opening 122 is formed.

このように、本発明の第４の実施形態のボンディングパッドの製造方法によれば、第３の実施形態のパッドを形成でき、第１の実施形態および第２の実施形態と同様の効果を有しながら、さらにパッドはがれに対する強度を向上できる。したがって、パッド下層の領域を有効活用できるためチップ面積を縮小でき、チップコストを低減できる。   Thus, according to the bonding pad manufacturing method of the fourth embodiment of the present invention, the pad of the third embodiment can be formed, and the same effects as those of the first and second embodiments are obtained. However, the strength against pad peeling can be further improved. Therefore, the area under the pad can be used effectively, so that the chip area can be reduced and the chip cost can be reduced.

なお、接続孔１２０ａ底部に露出した第３の配線１１５も、第１のパッド１１６と同様、アルゴンイオンミリング法により第３の配線１１５のアルミニウム表面をエッチングして、表面を凹凸形状にすることができる。   Note that the surface of the third wiring 115 exposed at the bottom of the connection hole 120a can also be made uneven by etching the aluminum surface of the third wiring 115 by an argon ion milling method, like the first pad 116. it can.

また、第１，２の実施形態のパッドの製造方法に関しても、図５，６，８に示す工程と同様にして製造することができる。   Further, the pad manufacturing methods of the first and second embodiments can be manufactured in the same manner as the steps shown in FIGS.

本発明は、半導体素子上にボンディングパッドを形成するＰＯＥ型プローブパッドを有する半導体装置における電極パッドと配線層との接続構造に有用である。   The present invention is useful for a connection structure between an electrode pad and a wiring layer in a semiconductor device having a POE type probe pad for forming a bonding pad on a semiconductor element.

本発明の第１の実施形態に係る半導体装置の断面図Sectional drawing of the semiconductor device which concerns on the 1st Embodiment of this invention 本発明の第１の実施形態に係る半導体装置のパッド部の平面図The top view of the pad part of the semiconductor device which concerns on the 1st Embodiment of this invention 本発明の第２の実施形態に係る半導体装置のパッド部の平面図The top view of the pad part of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の第１のパッドと第２のパッドの接続部を拡大した部分断面図The fragmentary sectional view which expanded the connection part of the 1st pad and the 2nd pad of the semiconductor device concerning a 3rd embodiment of the present invention. 本発明の第４の実施形態に係る半導体装置の製造方法を示す工程順の断面図Sectional drawing of order of a process which shows the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention 本発明の第４の実施形態に係る半導体装置の製造方法を示す工程順の断面図Sectional drawing of order of a process which shows the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention 本発明の第４の実施形態に係る半導体装置の製造方法を示す工程順の断面図Sectional drawing of order of a process which shows the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention 本発明の第４の実施形態に係る半導体装置の製造方法を示す工程順の断面図Sectional drawing of order of a process which shows the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention 従来に係るボンディングパッド部を有する半導体装置の断面図Sectional drawing of the semiconductor device which has the bonding pad part which concerns on the past 従来に係るボンディングパッド部を有する半導体装置の断面図Sectional drawing of the semiconductor device which has the bonding pad part which concerns on the past

符号の説明Explanation of symbols

１０１ シリコン基板（半導体基板）
１０２ 素子分離絶縁膜
１０３ 半導体素子
１０３ａ 拡散層
１０３ｂ ゲート酸化膜
１０３ｃ ゲート電極
１０３ｄ サイドウォール
１０４ 第１の層間絶縁膜
１０５ 第１の接続孔
１０６ 第１のプラグ
１０７ 第１の配線
１０８ 第２の層間絶縁膜
１０９ 第２の接続孔
１１０ 第２のプラグ
１１１ 第２の配線
１１２ 第３の層間絶縁膜（一の絶縁膜）
１１３ 第３の接続孔
１１４ 第３のプラグ
１１５ 第３の配線
１１６ 第１のパッド（一の金属パターン）
１１６ａ アルミニウム膜
１１６ｂ アルミニウム粒境界
１１６ｃ 窒化チタン膜
１１７ 第４の層間絶縁膜（他の絶縁膜）
１１８ 第４の配線
１１９ 第２のパッド（他の金属パターン）
１１９ａ チタン膜
１１９ｂ 窒化チタン膜
１１９ｃ アルミニウム膜
１２０ａ 第４の接続孔
１２０ｂ 第４の接続孔
１２０ｃ 接続溝
１２１ 保護膜
１２２ パッド開口
１２３ 応力のかかる方向 101 Silicon substrate (semiconductor substrate)
102 Element isolation insulating film 103 Semiconductor element 103a Diffusion layer 103b Gate oxide film 103c Gate electrode 103d Side wall 104 First interlayer insulating film 105 First connection hole 106 First plug 107 First wiring 108 Second interlayer insulation Film 109 Second connection hole 110 Second plug 111 Second wiring 112 Third interlayer insulating film (one insulating film)
113 3rd connection hole 114 3rd plug 115 3rd wiring 116 1st pad (one metal pattern)
116a Aluminum film 116b Aluminum grain boundary 116c Titanium nitride film 117 Fourth interlayer insulating film (other insulating film)
118 4th wiring 119 2nd pad (other metal pattern)
119a Titanium film 119b Titanium nitride film 119c Aluminum film 120a Fourth connection hole 120b Fourth connection hole 120c Connection groove 121 Protective film 122 Pad opening 123 Stress application direction

Claims (6)

半導体基板上に形成された一の絶縁膜と、
前記一の絶縁膜の上に形成された一の金属パターンと、
前記一の絶縁膜および前記一の金属パターンの上に形成された他の絶縁膜と、
前記他の絶縁膜の上に前記一の金属パターンと対向して形成された他の金属パターンと、
前記他の金属パターンの周囲に配置して、前記他の絶縁膜中に形成された接続孔とを備え、
前記接続孔を通じて前記一の金属パターンと前記他の金属パターンを直接接触させて電気的に接続することを特徴とする半導体装置。 One insulating film formed on the semiconductor substrate;
One metal pattern formed on the one insulating film;
The one insulating film and another insulating film formed on the one metal pattern;
Another metal pattern formed on the other insulating film so as to face the one metal pattern;
Arranged around the other metal pattern, and provided with a connection hole formed in the other insulating film,
A semiconductor device, wherein the one metal pattern and the other metal pattern are in direct contact with each other and electrically connected through the connection hole. 前記接続孔のアスペクト比が１以下であることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein an aspect ratio of the connection hole is 1 or less. 前記接続孔が前記他の金属パターンの周囲を取り巻く溝からなることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the connection hole includes a groove surrounding the periphery of the other metal pattern. 前記接続孔の底部に露出した、前記一の金属パターンの表面が凹凸形状になっていることを特徴とする請求項１の半導体装置。   2. The semiconductor device according to claim 1, wherein the surface of the one metal pattern exposed at the bottom of the connection hole has an uneven shape. 半導体基板上に一の絶縁膜を形成する工程と、
前記一の絶縁膜の上に一の金属パターンを形成する工程と、
前記一の絶縁膜と前記一の金属パターンの上に他の絶縁膜を形成する工程と、
前記他の絶縁膜中に接続孔を形成する工程と、
前記他の絶縁膜の上と前記接続孔の内に他の金属パターンを形成する工程とを含み、
前記接続孔は前記他の金属パターンの周囲に配置され、前記接続孔を通じて前記一の金属パターンと前記他の金属パターンを直接接触させて電気的に接続することを特徴とする半導体装置の製造方法。 Forming an insulating film on the semiconductor substrate;
Forming a metal pattern on the insulating film;
Forming another insulating film on the one insulating film and the one metal pattern;
Forming a connection hole in the other insulating film;
Forming another metal pattern on the other insulating film and in the connection hole,
The connection hole is disposed around the other metal pattern, and the one metal pattern and the other metal pattern are in direct contact with each other through the connection hole to be electrically connected to each other. . 半導体基板上に一の絶縁膜を形成する工程と、
前記一の絶縁膜の上に一の金属パターンを形成する工程と、
前記一の絶縁膜と前記一の金属パターンの上に他の絶縁膜を形成する工程と、
前記他の絶縁膜中に接続孔を形成する工程と、
前記接続孔の底部に露出した前記一の金属パターン表面を凹凸形状にする工程と、
前記他の絶縁膜の上と前記接続孔の内に他の金属パターンを形成する工程とを含み、
前記接続孔は前記他の金属パターンの周囲に配置され、前記接続孔を通じて前記一の金属パターンと前記他の金属パターンを直接接触させて電気的に接続することを特徴とする半導体装置の製造方法。 Forming an insulating film on the semiconductor substrate;
Forming a metal pattern on the insulating film;
Forming another insulating film on the one insulating film and the one metal pattern;
Forming a connection hole in the other insulating film;
Making the surface of the one metal pattern exposed at the bottom of the connection hole an uneven shape;
Forming another metal pattern on the other insulating film and in the connection hole,
The connection hole is disposed around the other metal pattern, and the one metal pattern and the other metal pattern are in direct contact with each other through the connection hole to be electrically connected to each other. .
JP2006241292A 2006-09-06 2006-09-06 Semiconductor device and its manufacturing method Pending JP2008066440A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102790058A (en) * 2011-05-20 2012-11-21 台湾积体电路制造股份有限公司 Semiconductor device having a bonding pad and method of manufacturing the same
KR101259724B1 (en) * 2011-07-07 2013-04-30 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Backside illumination sensor having a bonding pad structure and method of making the same
CN113990994A (en) * 2021-09-08 2022-01-28 华灿光电（浙江）有限公司 High-stability light emitting diode chip and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102790058A (en) * 2011-05-20 2012-11-21 台湾积体电路制造股份有限公司 Semiconductor device having a bonding pad and method of manufacturing the same
KR101259724B1 (en) * 2011-07-07 2013-04-30 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Backside illumination sensor having a bonding pad structure and method of making the same
US8435824B2 (en) 2011-07-07 2013-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside illumination sensor having a bonding pad structure and method of making the same
DE102011056178B4 (en) * 2011-07-07 2016-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. A back surface exposure sensor having a bonding surface structure and manufacturing method thereof
CN113990994A (en) * 2021-09-08 2022-01-28 华灿光电（浙江）有限公司 High-stability light emitting diode chip and manufacturing method thereof
CN113990994B (en) * 2021-09-08 2023-11-14 华灿光电（浙江）有限公司 High-stability light-emitting diode chip and manufacturing method thereof

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