JP2008053634A - Manufacturing methods of semiconductor film, and of semiconductor element, and electro-optical apparatus and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To crystalize a semiconductor film, while further enhancing uniformity more than a conventional technique by further improving a thermal plasma jet crystallization technique. <P>SOLUTION: The manufacturing method of a semiconductor film includes a first step of forming a semiconductor film (104) on a substrate (106), and a second step of allowing a thermal plasma (103) to abut on the semiconductor film, while relatively moving the plasma along a first axis parallel to the surface of the semiconductor film. The second step is executed under the conditions that value Φ/v, obtained by dividing a distance Φ in a first axial direction of a jetting hole (107) of the thermal plasma by a relative moving speed v between the thermal plasma and the substrate, be 5-40 mm/sec, and that distance D be 2-15 mm between an electrode (102) for generating the thermal plasma and the substrate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor thin film formed on a single crystal semiconductor substrate or an insulator, a thin film transistor, and a logic circuit, a memory circuit, a liquid crystal display device, and a display pixel or display device of an organic electroluminescence (EL) display device formed thereby. The present invention relates to a method for manufacturing a thin film transistor used as a constituent element of a drive circuit and a method for manufacturing a solar cell formed on an insulator.

  Conventionally, semiconductor thin films such as polycrystalline silicon (poly-Si) have been widely used for thin film transistors (TFTs) and solar cells. In particular, poly-Si TFTs have high carrier mobility and can be manufactured on a transparent insulating substrate such as a glass substrate. For example, pixel circuits such as liquid crystal display devices, liquid crystal projectors, and organic EL display devices can be formed. It is widely used as a switching element or a circuit element of a driver for driving a liquid crystal.

  As a method of manufacturing a high-performance TFT on a glass substrate, there is a manufacturing method generally called a high temperature process. Among TFT manufacturing processes, a process using a high temperature of about 1000 ° C. is generally called a high temperature process. Features of the high-temperature process are that a relatively good quality polycrystalline silicon can be formed by solid phase growth of silicon, a good quality gate insulating layer can be obtained by thermal oxidation of silicon, and a clean polycrystalline. This is the point that an interface between silicon and the gate insulating layer can be formed. Due to these characteristics, a high-performance TFT having high mobility and high reliability can be stably manufactured in a high-temperature process. However, in the high temperature process, in order to crystallize the silicon film by solid phase growth, a long time heat treatment of about 48 hours at a temperature of about 600 ° C. is required. This is a very long process, and in order to increase the process throughput, a large number of heat treatment furnaces are inevitably required, and it is difficult to reduce the cost. In addition, quartz glass has to be used as an insulating substrate with high heat resistance, so the cost of the substrate is high and it is said that it is not suitable for large area.

  On the other hand, a technique for lowering the maximum temperature in the process and manufacturing a poly-Si TFT on an inexpensive large-area glass substrate is a technique called a low-temperature process. Among TFT manufacturing processes, a process for manufacturing poly-Si TFTs on a heat-resistant glass substrate that is relatively inexpensive in a temperature environment where the maximum temperature is approximately 600 ° C. or lower is generally called a low-temperature process. In a low temperature process, a laser crystallization technique for crystallizing a silicon film by using a pulse laser having an extremely short oscillation time is widely used. Laser crystallization is a technique that utilizes the property of crystallizing in the process of solidifying instantaneously by irradiating a silicon thin film on a substrate with high-power pulsed laser light.

  However, this laser crystallization technique has some major problems. One is a large amount of trap levels localized inside the polysilicon film formed by the laser crystallization technique. Due to the presence of the trap level, carriers that should originally move in the active layer by the application of a voltage are trapped and cannot contribute to electrical conduction, which has adverse effects such as a decrease in TFT mobility and an increase in threshold voltage. Further, there is a problem that the size of the glass substrate is limited due to the limitation of the laser output. In order to improve the throughput of the laser crystallization process, it is necessary to increase the area that can be crystallized at one time. However, since the current laser output is limited, when this crystallization technique is adopted for a large substrate such as the seventh generation (1800 mm × 2100 mm), it takes a long time to crystallize one substrate. Laser crystallization technology generally uses a laser shaped in a line, and crystallization is performed by scanning this laser. This line beam is shorter than the width of the substrate because of limited laser output, and it is necessary to scan the laser several times in order to crystallize the entire surface of the substrate. As a result, a line beam seam area is generated in the substrate, and an area that is scanned twice is formed. This region is significantly different in crystallinity from the region crystallized by one scan. For this reason, the element characteristics of the two are greatly different, which causes a large variation in devices. Finally, since the laser crystallization apparatus has a complicated apparatus configuration and a high cost of consumable parts, there are problems that the apparatus cost and running cost are high. As a result, a TFT using a polysilicon film crystallized by a laser crystallization apparatus becomes an element with a high manufacturing cost.

  In order to overcome the problems such as the limitation of the substrate size and the high apparatus cost, a crystallization technique called a thermal plasma jet crystallization method has been studied (for example, see Non-Patent Document 1). The technology is briefly described below. When a tungsten (W) cathode and a water-cooled copper (Cu) anode are opposed to each other and a DC voltage is applied, an arc discharge occurs between the two electrodes. By flowing argon gas between these electrodes under atmospheric pressure, thermal plasma is ejected from the ejection holes vacated in the copper anode. Thermal plasma is thermal equilibrium plasma, which is an ultra-high temperature heat source having substantially the same temperature of ions, electrons, neutral atoms, etc., and the temperature of which is about 10,000K. Therefore, the thermal plasma can easily heat the object to be heated to a high temperature, and the substrate on which the a-Si film is deposited scans the front surface of the ultra-high temperature thermal plasma at a high speed, thereby crystallizing the a-Si film. Can be Thus, since the apparatus configuration is very simple and the crystallization process is performed under atmospheric pressure, it is not necessary to cover the apparatus with an expensive member such as a chamber, and the apparatus cost can be expected to be extremely low. The utilities required for crystallization are argon gas, electric power, and cooling water, which is a crystallization technique with low running costs.

S. Higashi, AM-LCD '05, pp. 75-78 (2005)

  An object of the present invention is to further improve the above-described thermal plasma jet crystallization technique and provide a technique for further improving the crystallinity of a semiconductor film as compared with the conventional technique.

A method of manufacturing a semiconductor film according to the first aspect of the present invention includes:
A first step of forming a semiconductor film on a substrate;
A second step in which thermal plasma is applied to the semiconductor film while relatively moving along a first axis parallel to the surface of the semiconductor film;
Including
In the second step, Φ / v, which is a value obtained by dividing a distance Φ in the first axial direction of the ejection hole of the thermal plasma by a relative moving speed v of the thermal plasma and the substrate, is 5 milliseconds or more 40 It is performed under the conditions that the distance D between the electrode part for generating the thermal plasma and the substrate is 2 mm or more and 15 mm or less and not longer than milliseconds. Here, “relatively moving” refers to relatively moving the semiconductor film and the thermal plasma, and more specifically, in the case of moving only the semiconductor film (and the substrate associated therewith). Both the case of moving only the thermal plasma and the case of moving both together are included.

  According to such a method, the thermal plasma jet crystallization technique can be further improved, and the crystallinity of the semiconductor film can be further improved as compared with the conventional method. More specifically, a semiconductor film having high electrical conductivity and a small trap level density can be obtained.

  More preferably, the second step is performed under the condition that the Φ / v is 10 milliseconds or more and 20 milliseconds or less, and the distance D is 5 mm or more and 12 mm or less.

  Under such conditions, the crystallinity of the semiconductor film can be further improved.

A method of manufacturing a semiconductor element according to the second aspect of the present invention includes:
A first step of forming a heat-treated semiconductor film using the manufacturing method described above;
A second step of forming a semiconductor element using the semiconductor film;
including. Here, the “semiconductor element” refers to, for example, a transistor, a diode, a resistance element, a capacitor element, or the like.

  According to such a method, a semiconductor element composed of a semiconductor film with good crystallinity can be obtained.

  The third aspect of the present invention is an electro-optical device including a thin film transistor manufactured by using the method for manufacturing a semiconductor element. Here, “electro-optical device” means a general device including an electro-optical element that emits light by electric action or changes the state of light from the outside. The device that emits light by itself and the passage of light from the outside. Includes both things to control. Examples of the electro-optical element include a liquid crystal element, an electrophoretic element, an EL (electroluminescence) element, and an electron-emitting element that emits light by applying electrons generated by applying an electric field to a light-emitting plate.

  The fourth aspect of the present invention is an electronic apparatus including the electro-optical device as a display unit. Here, “electronic device” refers to a general device that exhibits a certain function by a combination of a plurality of elements or circuits. Examples of such electronic devices include an IC card, a mobile phone, a video camera, a personal computer, a head-mounted display, a fax machine with a display function, a digital camera finder, a portable TV, a PDA, and an electronic notebook. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic view for explaining a semiconductor film crystallization method using thermal plasma. The thermal plasma generating apparatus 1 includes a cathode 101 and an anode 102 that is disposed to face the cathode 101 with a predetermined distance therebetween. The cathode 101 is made of a conductor such as tungsten. The anode 102 is made of a conductor such as copper. Moreover, the anode 102 is formed in a hollow shape, and is configured so that water can be cooled through the hollow portion. The anode 102 is provided with an ejection hole (nozzle) 107. When a direct current (DC) voltage is applied between the cathode 101 and the anode 102, an arc discharge is generated between the two electrodes. In this state, the thermal plasma 103 can be ejected from the ejection hole 107 by flowing a gas such as argon gas between the cathode 101 and the anode 102 under atmospheric pressure. Here, the “thermal plasma” is a thermal equilibrium plasma, which is an ultra-high temperature heat source having substantially the same temperature of ions, electrons, neutral atoms, etc., and having a temperature of about 10,000K. An example of conditions for generating the thermal plasma 103 will be described. The cathode 101 is made of tungsten, and the anode 102 is made of copper. The distance between the cathode 101 and the anode 102 (interelectrode distance) is 1 mm. The gas flowing between both electrodes is argon (Ar) gas, and the flow rate is set to about 9.8 to 10 liters / minute. The DC voltage applied between the electrodes is set so that the current flowing between the electrodes is constant at 150A. The diameter of the ejection hole 107 from which the thermal plasma 103 is ejected is 4 mm.

  Such thermal plasma can be used for heat treatment for crystallization of a semiconductor film. Specifically, a semiconductor film 104 (for example, an amorphous silicon film) is formed over the substrate 106, and thermal plasma (thermal plasma jet) 103 is applied to the semiconductor film 104. At this time, the thermal plasma 103 is applied to the semiconductor film 104 while relatively moving along a first axis (left and right direction in the illustrated example) parallel to the surface of the semiconductor film 104. That is, the thermal plasma 103 is applied to the semiconductor film 104 while scanning in the first axis direction. Here, “relatively moving” refers to relatively moving the semiconductor film 104 (and the substrate 106 supporting the semiconductor film 104) and the thermal plasma 103, and moving only one or both of them. Any of the cases are included. By such scanning of the thermal plasma 104, the semiconductor film 104 is heated by the high temperature of the thermal plasma 103, and a crystallized semiconductor film 105 (polysilicon film in this example) is obtained. At this time, the thermal plasma scanning method differs depending on whether the thermal plasma is in the form of dots or lines. This will be described next.

  FIG. 2 is a schematic plan view for explaining a scanning method in the case where the thermal plasma has a dot shape. More specifically, the case where the thermal plasma 103 is dot-like means, for example, that the thermal plasma generator 1 described above has one ejection hole 107 and uses the thermal plasma 103 discharged from the ejection hole 107. Is the case. In this case, the thermal plasma 103 is applied to the semiconductor film 104 on the substrate 106 while moving in the direction of the first axis (X axis in the drawing) parallel to the surface of the semiconductor film 104. The scanning speed at this time is appropriately set within a range of about 80 to 1000 mm / second, for example. Next, the position of the thermal plasma 103 is shifted by a distance d (hereinafter referred to as “shift width d”) to a second axis (Y-axis in the drawing) parallel to the surface of the semiconductor film 104 and perpendicular to the first axis. Thereafter, the thermal plasma 103 is again scanned in the first axis direction. By sequentially repeating this series of processes on the substrate 106, heat treatment is applied to the semiconductor film 104 formed on the substrate 106. Thereby, a crystallized semiconductor film 105 is obtained. When such crystallization is performed, the shift width d in the Y-axis direction affects the crystallinity of the semiconductor film 105 and its in-plane uniformity. The displacement width d of the thermal plasma 103 in the Y-axis direction is 10% or less, more preferably 5% or less with respect to the diameter Φ of the anode 102. Thereby, the uniformity of crystallization is ensured.

  In the example shown in FIG. 2, the thermal plasma 103 is folded and scanned. However, as in the example shown in FIG. 3, the thermal plasma 103 is scanned in one direction along the first axis without being folded. Good. That is, in the example of FIG. 2, the direction in which the thermal plasma 103 is moved is opposite (opposite direction) before and after shifting in the second axis (Y axis) direction, but in the example of FIG. ) The direction in which the thermal plasma 103 is moved is the same before and after shifting in the direction. In the case of the reciprocal scanning shown in FIG. 2, the time required for scanning the thermal plasma 103 can be further shortened by folding back at the end of the substrate 106. On the other hand, in the case of the unidirectional scanning shown in FIG. 3, the temporal profile of the amount of heat given to the semiconductor film can be made more uniform.

  Next, a case where a plurality of plasma sources are provided in order to improve the throughput per substrate when the semiconductor film is crystallized using thermal plasma will be described. In this case, in the thermal plasma generator 1 described above, a plurality of ejection holes 107 may be provided, and a plurality of cathodes 101 may be provided corresponding to each of the plurality of ejection holes 107.

  FIG. 4 is a diagram for explaining a thermal plasma scanning method when a plurality of plasma sources are provided. As shown in FIG. 4, the plurality of thermal plasmas 103 are arranged with a predetermined interval therebetween along the Y-axis (second axis) direction. The plurality of thermal plasmas 103 arranged in this manner are applied to the semiconductor film 104 while moving in the X-axis (first axis) direction. Next, the position of each thermal plasma 103 is shifted by the above-described shift width d in the Y-axis direction. Thereafter, each thermal plasma 103 is again scanned in the first axis direction. By sequentially repeating this series of processes on the substrate 106, heat treatment is applied to the semiconductor film 104 formed on the substrate 106. At this time, the distance between the individual thermal plasmas 103 is preferably an integer multiple (for example, 2 to 3 times) the shift width d in the Y-axis direction. As a result, crystallization can be achieved without shifting the joint between adjacent thermal plasmas 103, and uniformity can be maintained. Further, the throughput can be greatly improved. In addition to the case where each thermal plasma 103 is reciprocally scanned as shown in FIG. 4, each thermal plasma 103 may be scanned in one direction as shown in FIG.

  FIG. 6 is a graph showing the relationship between the electrode and substrate distance with respect to the annealing time. Here, in this embodiment, the “annealing time” refers to the distance Φ in the first axial direction of the thermal plasma ejection hole 107 (in this example, the diameter Φ of the ejection hole 107), and the moving speed v of the substrate 106 (that is, heat It is defined as “Φ / v” which is a value divided by the relative movement speed of the plasma 103 and the substrate 106. In addition, when the ejection hole of the thermal plasma 103 is in a line shape, the above Φ is the distance in the first axial direction (short axis direction) of the ejection port. A broken line on the left side shown in FIG. 6 indicates a threshold condition for determining whether or not the semiconductor film 104 (in this example, an amorphous silicon film) is crystallized. This indicates that the amorphous silicon film cannot be crystallized under the crystallization condition in the region on the left side of the broken line. The broken line on the right is the threshold condition for crystallization and ablation. In other words, the crystallization conditions in the region on the right side of the broken line indicate that the amorphous silicon film is heated too much to cause ablation and the film itself disappears. From these, a region between two broken lines is a region indicating a condition for crystallization.

  FIG. 7 is a graph showing the results of half-value widths obtained by Raman scattering spectroscopic analysis under a plurality of crystallization conditions A, B, C, D, E, and F that are almost immediately above the broken line shown in FIG. In FIG. 6, the crystallization conditions A, B, C or D, E, and F on the same broken line show almost the same half width. Therefore, it can be seen that they have almost the same crystallinity. In particular, the crystallization conditions D, E, and F are conditions immediately before ablation occurs, and are the conditions in which the substrate temperature is the highest, so that it is understood that the crystallinity is higher than the crystallization conditions A, B, and C.

FIG. 8 shows crystallization of an amorphous silicon film doped with 1 × 10 ¹⁸ cm ^{−3 of} phosphorus under the above crystallization conditions A, B, C, D, E, F, G, H, and I. 5 is a graph showing the results of measuring the electrical conductivity σ (S / cm) of the polysilicon film obtained in this manner. The electrical conductivity σ is expressed by charge q × carrier mobility μ × carrier density n. As shown in FIG. 8, the electrical conductivity σ varies greatly depending on the crystallization conditions, and this is because the carrier density n varies greatly. As described above, a large amount of trap levels exist in the polysilicon film. This trap level captures carriers that should contribute to the electrical conductivity, thereby reducing the substantial carrier density. That is, high electrical conductivity means that the carrier density is high, and that the trap level density is low. As can be seen from FIG. 8, the polysilicon film crystallized by the method of this embodiment has a higher electrical conductivity and a high-quality polysilicon film having a small trap level density compared to laser crystallization (ELA). It turns out that it has formed. Further, the condition of the highest electrical conductivity among the above eight crystallization conditions is in the case of the condition I having the longest annealing time. Although the crystallization conditions D, E, and F are the same in crystallinity (see FIG. 7), it can be seen that the trap level density existing in the film is significantly different. From the above results, it is clear that even if the crystallinity of the polysilicon film is the same, the trap level density varies greatly depending on the annealing time, and a high-quality polysilicon film can be formed by increasing the annealing time. I understood. However, if the annealing time is too long, it takes time to crystallize, which causes a reduction in throughput. In view of these circumstances, the annealing time Φ / v is desirably 5 milliseconds or more and 40 milliseconds or less. Further, in order to perform crystallization with such an annealing time Φ / v, the distance D between the electrode portion (the end portion of the anode 102) for generating the thermal plasma 103 and the substrate 106 is set to 2 mm or more and 15 mm or less. There is a need to. Further preferable conditions are that the annealing time Φ / v is 10 to 20 milliseconds and the distance D is 5 to 12 mm.

  In the above description, the method of performing crystallization using thermal plasma on the semiconductor film 104 made of an amorphous silicon film has been described. For example, the above-described thermal plasma jet is further applied to a polysilicon film that has been laser-crystallized in advance. Crystallization may be performed. By performing such treatment, non-uniform crystallinity formed by laser crystallization can be relaxed. The crystallization method of the present embodiment can be applied not only to an amorphous silicon film or a laser-crystallized polysilicon film but also to various thin film materials such as amorphous, polycrystalline, and microcrystal. The semiconductor film itself is not limited to the silicon film (details will be described later).

  Next, a method for crystallizing a semiconductor film by the above-described method and manufacturing a semiconductor element using the crystallized semiconductor film will be described.

  FIG. 9 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor element. In the following description, a top gate type thin film transistor (TFT) is taken as an example of a semiconductor element, but the semiconductor element is not limited to this.

(1. Base protective film and semiconductor thin film formation process)
First, a base protective film 701 is formed over a substrate 700, and a semiconductor thin film 702 is formed thereover (FIG. 9A). Here, the substrate 700 is made of a conductive material such as a metal, a ceramic material such as silicon carbide (SiC), alumina (Al ₂ O ₃ ), or aluminum nitride (AlN), or transparent or non-transparent such as fused quartz or glass. Insulating materials, semiconductor materials such as silicon and germanium wafers, and LSI substrates on which such materials are processed are possible. Examples of the base protective film 701 include an insulating material such as a silicon oxide film (SiO _x : 0 <x ≦ 2) and a silicon nitride film (Si ₃ N _x : 0 <x ≦ 4). In general, when a thin film semiconductor element such as a TFT is formed on a glass substrate, it is important to suppress contamination of the semiconductor thin film with impurities. Specifically, the semiconductor film is deposited after forming a base protective film on the substrate so that mobile ions such as sodium (Na) and potassium (K) contained in the glass substrate do not enter the semiconductor thin film. It is preferable. In addition, when a conductive material such as a metal material is used as a substrate and the semiconductor thin film must be electrically insulated from the metal substrate, a base protective film is indispensable to ensure insulation. Further, when a semiconductor film is formed on a semiconductor substrate or LSI element, an interlayer insulating film between transistors and wirings simultaneously functions as a base protective film.

The base protective film 701 is formed by first cleaning the substrate 700 with an organic solvent such as pure water or alcohol, and then performing an atmospheric pressure chemical vapor deposition method (APCVD method) or a low pressure chemical vapor deposition method (LPCVD method) on the substrate 700. The film is formed using a CVD method such as a plasma chemical vapor deposition method (PECVD method) or a film forming method such as a sputtering method. In the case where a silicon oxide film is used as the base protective film 701, the atmospheric pressure chemical vapor deposition method can be performed using monosilane (SiH ₄ ) or oxygen as a raw material at a substrate temperature of about 250 ° C. to 450 ° C. In the plasma chemical vapor deposition method or the sputtering method, the substrate temperature is about room temperature to 400 ° C. The base protective film 701 needs to be thick enough to prevent diffusion and mixing of impurity elements from the substrate 700. The thickness of the base protective film 701 is about 100 nm at the minimum, and is preferably about 200 nm or more in consideration of the variation between lots and substrates, and if it is about 300 nm, it can sufficiently function as a protective film. In the case where the base protective film 701 also serves as an interlayer insulating film such as an IC element or a wiring connecting these elements, the film thickness is usually about 400 nm to 600 nm. If the base protective film 701 is too thick, cracks due to film stress occur. Therefore, the maximum film thickness is preferably about 2 μm. When it is necessary to consider productivity, the upper limit of the insulating film thickness is about 1 μm.

Next, the semiconductor thin film 702 will be described. As the semiconductor thin film 702 of the present embodiment, silicon / germanium (Si _x Ge ₁ -x: 0 <x <1), silicon, etc., in addition to a single group IV semiconductor film such as silicon (Si) or germanium (Ge). A semiconductor film of a group IV element complex such as carbide (Si _X C _1-X : 0 <x <1) or germanium carbide (Ge _X C _1-X : 0 <x <1), gallium arsenide (GaAs ) And indium antimony (InSb), etc., a compound compound semiconductor film of a group 3 element and a group 5 element, or a compound compound semiconductor film of a group 2 element, such as cadmium selenium (CdSe), and a group 6 element, etc. Can be mentioned. Alternatively, the semiconductor thin film 702 may be formed of a further compound compound semiconductor film such as silicon, germanium, gallium, and arsenic (Si _x Ge _y Ga _z As _z : x + y + z = 1), phosphorus (P), arsenic (As ), An N-type semiconductor film to which a donor element such as antimony (Sb) is added, or a P-type semiconductor film to which an acceptor element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) is added. There may be. These semiconductor thin films are formed using a CVD method such as an APCVD method, an LPCVD method, or a PECVD method, or a physical vapor deposition method (PVD method) such as a sputtering method or an evaporation method. When a silicon film is used as the semiconductor thin film 702, disilane (Si ₂ H ₆ ) or the like can be deposited using LPCVD as a raw material with a substrate temperature of about 400 ° C. to 700 ° C. In the PECVD method, deposition can be performed at a substrate temperature of about 100 ° C. to 500 ° C. using monosilane (SiH ₄ ) or the like as a raw material. When using the sputtering method, the substrate temperature is about room temperature to 400 ° C. The initial state (as-deposited state) of the semiconductor thin film 702 thus deposited includes various states such as amorphous, mixed crystal, microcrystalline, and polycrystalline. In this embodiment, the initial state May be in any state. In the present specification, not only amorphous crystallization but also polycrystalline or microcrystalline recrystallization is referred to as “crystallization”. The film thickness of the semiconductor thin film 702 is suitably about 20 nm to 100 nm when it is used for a TFT.

(2. Thermal plasma jet crystallization)
After the semiconductor thin film 702 is formed, the semiconductor thin film 702 is crystallized by using the thermal plasma 703 by the method described in detail above (FIG. 9B). Thereby, a crystallized semiconductor thin film 704 is obtained on the substrate 700.

(3. Element isolation process)
Next, an element isolation step is performed to electrically insulate the TFT elements from each other. Specifically, after forming an etching mask on the semiconductor thin film 704 by photolithography, wet etching or dry etching is performed to pattern the semiconductor thin film 704 into an island shape (FIG. 9C).

(4. Formation process of gate insulating film)
After the island-shaped semiconductor thin film 704 is formed, a gate insulating film 705 that covers the semiconductor thin film 704 is formed over the entire surface of the substrate 700 (FIG. 9C). Examples of the method for forming the gate insulating film include an ECR plasma CVD method and a parallel plate RF discharge plasma CVD method.

(5. Formation process of gate electrode)
Subsequently, a conductive thin film to be the gate electrode 706 is deposited by the PVD method or the CVD method. This conductive thin film is desired to have low electrical resistance and be stable with respect to a heat process of about 350 ° C., and for example, a high melting point metal such as tantalum, tungsten, or chromium is preferably used. Further, when the source and drain are formed by ion doping, the thickness of the gate electrode is required to be about 700 nm in order to prevent hydrogen channeling. Tantalum is preferable in that it is a material that is not easily cracked by film stress even if it is formed with a film thickness of 700 nm among refractory metals. After the conductor thin film is formed, the gate electrode 706 is formed by patterning the conductor thin film (FIG. 9C).

(6. Source / drain formation process)
Subsequently, impurity ions are implanted into the semiconductor thin film 704 to form source / drain regions 707 (FIG. 9D). At this time, since the gate electrode 706 serves as a mask for ion implantation, the channel is formed only under the gate electrode (a so-called self-aligned structure). Impurity ion implantation is performed by ion doping using a mass non-separable ion implanter to implant hydride and hydrogen of an implanted impurity element, or by ion implantation using a mass separated ion implanter to implant only a desired impurity element. Laws can be adopted. As a source gas for the ion doping method, a hydride of an implanted impurity element such as phosphine (PH ₃ ) or diborane (B ₂ H ₆ ) having a concentration of about 0.1% to 10% diluted in hydrogen is used. In the ion implantation method, only a desired impurity element is implanted, and then hydrogen ions (protons and hydrogen molecular ions) are implanted. In the case of manufacturing a CMOS circuit, first, an NMOS transistor or a PMOS transistor is alternately covered with a mask using an appropriate mask material such as polyimide resin, and each ion implantation is performed by the above-described method. Further, there is laser activation that irradiates an excimer laser or the like as an efficient method for activating impurities. This is a method of activating impurities by melting and solidifying the source and drain by laser irradiation through an insulating film.

(7. Electrode formation process)
Next, an interlayer insulating film 708 which covers the gate insulating film 705 and the gate electrode 706 is formed (FIG. 9E). The formation method is the same as that of each insulating film described above. Thereafter, contact holes are formed on the source / drain 707, and source / drain extraction electrodes 709 and other wirings (not shown) are formed (FIG. 9E). More specifically, a source / drain extraction electrode 709 is formed by forming a conductive thin film by a film forming method such as a PVD method or a CVD method, and patterning it. Through the above steps, the thin film transistor is completed.

  Next, an organic EL device will be described as a configuration example of the electro-optical device using the above-described thin film transistor, and further, a configuration example of an electronic apparatus including the organic EL device will be described.

  FIG. 10 is a schematic plan view of the wiring structure of the organic EL device. An organic EL device 200 shown in FIG. 10 includes a plurality of scanning lines 201, a plurality of signal lines 202 arranged orthogonal to the scanning lines, a plurality of power supply lines 203 extending in parallel to the signal lines 202, and each scanning line. 201 and a pixel portion 206 provided in the vicinity of the intersection of each signal line 202. That is, the organic EL device 200 of the present example is an active matrix display device that includes a plurality of pixel portions 206 and each pixel portion 206 is arranged in a matrix. Each scanning line 201 is connected to a scanning line driving circuit 205 including a shift register and a level shifter. Each signal line is connected to a data line driving circuit 204 including a shift register, a level shifter, a video line, and an analog switch. Each pixel portion 206 includes a switching transistor 212 to which a scanning signal is supplied to the gate via the scanning line 201, a holding capacitor 211 for holding a pixel signal supplied from the signal line 202 via the switching transistor 212, A driving transistor 213 to which the pixel signal held by the holding capacitor 211 is supplied to the gate, and a driving current from the power line 203 when electrically connected to the power line 203 through the driving transistor 213 are supplied. An organic EL element 210 that flows in is provided. Each organic EL element 210 is configured by interposing a light emitting layer between a pixel electrode (cathode) and a counter electrode (anode). The light emitting layer includes, for example, a hole transport layer, a light emitting layer, an electron injection layer, and the like. The thin film transistor of this embodiment described above is used as the switching transistor 212 or the driving transistor 213. Alternatively, the above thin film transistor may be used as a circuit element included in the scan line driver circuit 205 or the data line driver circuit 204.

  FIG. 11 is a schematic perspective view illustrating a configuration example of an electronic device. FIG. 11A shows an application example to a mobile phone. The cellular phone 1000 includes a display unit 1001, an antenna unit 1002, an audio output unit 1003, an audio input unit 1004, and an operation unit 1005. The electro-optical device is used as the display unit 1001. FIG. 11B shows an application example to a video camera. The video camera 1100 includes an image receiving unit 1101, an operation unit 1102, and a display unit 1103. The electro-optical device is used as the display unit 1103. The electro-optical device according to this embodiment can be applied to any electronic apparatus to which an active matrix electro-optical device can be applied, in addition to the above configuration example. For example, in addition to this, it can be used for a fax machine with a display function, a finder for a digital camera, a portable TV, a PDA, an electronic notebook, a television device, and the like.

  As described above, according to the present embodiment, the thermal plasma jet crystallization technique can be further improved, and the semiconductor film can be crystallized with higher uniformity than before. More specifically, a semiconductor film having high electrical conductivity and a small trap level density can be obtained.

  Note that the present invention is not limited to the contents of the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention.

It is a schematic diagram for demonstrating the crystallization method of the semiconductor film using thermal plasma. It is a schematic plan view explaining the scanning method in case thermal plasma is dotted. It is a schematic plan view explaining the scanning method in case thermal plasma is dotted. It is a figure explaining the scanning method of the thermal plasma in the case of providing a plurality of plasma sources. It is a figure explaining the scanning method of the thermal plasma in the case of providing a plurality of plasma sources. It is a graph which shows the relationship of the distance between an electrode and a board | substrate with respect to annealing time. It is a graph which shows the result of the half value width calculated | required from the Raman scattering spectroscopic analysis in each crystallization condition. It is a graph which shows the result of having measured the electrical conductivity about the polysilicon film obtained by crystallizing on each crystallization condition. It is a schematic cross section explaining the manufacturing method of a semiconductor element. It is a plane schematic diagram of the wiring structure of an organic EL device. It is a schematic perspective view explaining the structural example of an electronic device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Cathode, 102 ... Anode, 103 ... Thermal plasma, 104 ... Semiconductor film, 105 ... Crystallized semiconductor film, 106 ... Substrate, 107 ... Ejection hole, 200 ... Organic EL device, 201 ... Scanning line, 202 ... Signal Line 203, power line 204, data line driving circuit, 205 scanning line driving circuit, 206 pixel unit, 210 organic EL element, 211 holding capacitor, 212 switching transistor, 213 driving transistor, 700 Substrate, 701 ... underlying protective film, 702 ... semiconductor thin film, 703 ... thermal plasma, 704 ... semiconductor thin film, 705 ... gate insulating film, 706 ... gate electrode, 707 ... source / drain, 708 ... interlayer insulating film, 709 ... source / Drain extraction electrode, 1000 ... mobile phone, 1001 ... display unit, 1002 ... antenna unit, 1003 ... audio output unit, 004 ... audio input portion, 1005 ... the operating unit, 1100 ... video camera, 1101 ... an image receiving portion, 1102 ... the operating unit, 1103 ... the display unit

Claims (5)

A first step of forming a semiconductor film on a substrate;
A second step in which thermal plasma is applied to the semiconductor film while relatively moving along a first axis parallel to the surface of the semiconductor film;
Including
In the second step, Φ / v, which is a value obtained by dividing the first axial distance Φ of the thermal plasma ejection hole by the relative moving speed v of the thermal plasma and the substrate, is 5 milliseconds or more. It is carried out under the conditions that the distance D between the electrode part for generating the thermal plasma and the substrate is not less than 2 mm and not more than 15 mm.
A method for manufacturing a semiconductor film. The second step is performed under the condition that the Φ / v is 10 milliseconds to 20 milliseconds and the distance D is 5 mm to 12 mm.
The method for manufacturing a semiconductor film according to claim 1. A first step of forming a heat-treated semiconductor film using the manufacturing method according to claim 1;
A second step of forming a semiconductor element using the semiconductor film;
A method for manufacturing a semiconductor device, comprising:   An electro-optical device comprising a thin film transistor manufactured using the manufacturing method according to claim 3.   An electronic apparatus comprising the electro-optical device according to claim 4.

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