JP2007517410A - Pattern circuit and manufacturing method thereof - Google Patents

Abstract

A patterned circuit having raised features that are precisely aligned is provided. A circuit manufacturing method using photoresist on photoresist patterning is also provided.

Description

  The present invention relates to a pattern circuit feature on a substrate and a pattern circuit manufacturing method.

  A thick film circuit pattern obtained by etching copper or a thick film circuit pattern obtained by printing a polymer on a polymer film base may be referred to as a flexible circuit or a flexible printed wiring board. A flexible circuit generally includes a conductive wiring pattern supported on a base substrate such as a dielectric material layer. Originally designed for use in place of wiring harnesses, flexible circuits are often the only solution for miniaturization and operation required for today's state-of-the-art electronic assemblies It is. Flexible circuits exhibit attributes such as fine pitch wiring, complex circuit design and flexibility. Because it is thin, lightweight and ideal for complex devices, flexible circuit design solutions range from single-sided conductive paths to complex, multi-layer, three-dimensional packages. Electronic devices, medical devices, hard disk drive suspensions, inkjet printer pens and touch or finger sensors are common applications for flexible circuits.

  Multilayer wiring modules are widely used in the semiconductor industry and mechanically support integrated circuit chips and electrically connect the chips to printed wiring. The wiring module can be configured to support a single chip or multiple chips and is typically identified by the name SCM (single chip module) or MCM (multichip module).

  The wiring module provides wiring that serves to electrically connect the integrated circuit chip to signal lines, power lines, and other components provided in the printed wiring. In particular, the wiring module provides wiring that redistributes input and output (I / O) mounted on the chip at high density to the corresponding I / O on the printed wiring board. In addition to electrical wiring, the wiring module typically serves to mechanically connect the chip to the printed wiring board and can also perform other functions such as heat dissipation and environmental protection.

  One embodiment of the present invention includes a step of providing a substrate, a step of forming a first pattern layer of a photoresist on the substrate, and a conductive material in a pattern formed by the photoresist from the thickness of the photoresist layer. Forming a thin thickness and creating a second patterned layer of photoresist at least partially overlapping the first patterned layer of photoresist so as to expose at least a portion of the conductive material. And additional conductive material was formed in the first and second layers of photoresist such that the height of the thickest portion of conductive material did not exceed the height of the first layer of photoresist. Forming a film with the pattern.

  Another aspect of the present invention includes providing a substrate, applying an uncured photoresist layer to the substrate, curing at least a pattern to the photoresist, and uncured. Forming at least one first cavity in the photoresist by removing a portion of the photoresist from the at least a portion, and having a conductive material in the first cavity less than a thickness of the photoresist layer. Depositing to a thickness; applying a second uncured photoresist layer to the photoresist and conductive material layer; and a second portion at least partially with the at least one first cavity Harden the pattern into the photoresist except for at least one second portion that overlaps Removing at least one second portion of the uncured photoresist from the at least one second portion so that a second cavity at least partially overlaps the at least one first cavity. Forming the second cavity in the photoresist; and the height of the thickest portion of the conductive material does not exceed the height of the first layer of photoresist material, the conductive material being the at least one Depositing a desired thickness in one of the second cavities.

  Another aspect of the invention provides a dielectric film having a first surface and a second metal coated surface, and an uncured photoresist layer is applied to the second metal coated surface of the dielectric film. Applying at least one portion, curing at least a portion of the pattern into the photoresist, and removing the uncured photoresist from the at least portion to form at least one cavity in the photoresist. Depositing a metal in the first cavity to a thickness less than a thickness of the photoresist layer; applying a second uncured photoresist layer to the photoresist and the metal layer; At least one second portion, wherein the second portion partially overlaps the at least one first cavity; Curing a pattern into the photoresist and removing the uncured photoresist from the at least one second portion so that a second cavity is at least partly with the at least one first cavity. Forming at least one second cavity in the photoresist, wherein the total height of the thickest portion of the metal does not exceed the height of the first layer of photoresist. Depositing the desired thickness in the at least one second cavity.

  Another aspect of the invention comprises providing a substrate, applying an uncured negative photoresist layer to the substrate, curing a pattern to the photoresist, except at least in part, and the uncured. Forming at least one cavity in the photoresist by removing a cured photoresist from the at least portion; and depositing a conductive material in the first cavity to a thickness less than a thickness of the photoresist layer. Depositing, applying a positive photoresist layer to the negative photoresist and a conductive material layer, and exposing a positive portion, wherein a second portion partially overlaps the at least one first cavity. Forming a photoresist pattern on at least one of the second portions; and Removing at least a portion of the positive photoresist formed in the photoresist to form at least one second cavity in the photoresist, and the total thickness of the highest portion of the conductive material portion of the structure is photoresist Depositing a conductive material to a desired thickness within the at least one second cavity without exceeding the height of the first layer of material.

  Another aspect of the invention is a substrate, a conductive layer having a wiring pattern, and a raised feature on a portion of the wiring, where the width of the raised feature places the raised feature. And an elevated feature that is substantially the same as the width of the article.

  Another aspect of the invention is a substrate, a conductive layer having a wiring pattern, and a raised feature on a portion of the wiring having at least two layers of the same or different conductive material, Features an article comprising raised features, wherein the X and Y dimensions of the layers are substantially the same and the two layers are substantially longitudinally aligned.

  An advantage of at least one embodiment of the present invention is that it eliminates the need to accurately align the flexible circuit with the exposure tool when patterning circuit features.

  Another advantage of at least one embodiment of the present invention is that it allows circuit features to be formed on finer pitch wiring.

  Another advantage of at least one embodiment of the present invention is that the raised circuit features need only be aligned in non-critical directions. This makes it possible to maximize the width of the feature of the combined region.

  An advantage of at least one embodiment of the present invention is that it can tolerate imaging positioning errors that are greater than 50% of the characteristic dimensions of the circuit features.

  Other features and advantages of the invention will be apparent from the following drawings, detailed description, and claims.

  Aspects of the invention include additional methods of manufacturing differentiated thickness circuit features for electronic packaging and wiring applications. These methods use an additional process that involves increasing two stacked photoresist layers in conjunction with two separate circuit plating steps. This process is particularly applicable to arbitrary circuit configurations such as multi-layer metal layer packages and fine pitch wiring on flexible circuits. This requires die attach bumps or other raised features of the circuit, combined with high wiring density. At least one embodiment of the present invention provides good positioning between the raised features and other circuit features.

  An important advantage of at least one embodiment of the present invention is that there is no need to accurately align the substrate and the exposure apparatus to image aligned circuit features on fine pitch wiring. In the method of the present invention, a desired multi-stage structure is formed by using a combination of photoresist-on-photoresist patterning and recess formation. As the negative photoresist type, a wet type or a dry type can be used. The process described here uses a dry-type negative photoresist and a substrate with a conductive coating on only one side, but can be easily extended to a two-layer metal-layer circuit with the teachings described herein It is.

  In the conventional raised circuit feature formation process, circuit wiring is formed on the dielectric film by photolithography process and etching, and then the raised circuit feature is formed on these wirings using a second photolithography process. Form. For this purpose, it is necessary to accurately align the already formed wiring and the imaging of the desired circuit feature. This process is limited by alignment tolerances and cannot be applied to fine pitch circuits that exceed the alignment capabilities of the device. Besides this limitation, the photoresist material does not necessarily flow into the fine openings that are to form the circuit features.

  Many electronic packaging structures such as ball grid arrays, flip chip arrays and other integrated circuit package (ICP) configurations, and wiring connections and via pads to produce display panels, printed wiring boards, or additional circuit layers, etc. There is a need for the ability to form relatively thick raised circuit features among other relatively thinner features.

Typical processing methods define these relatively large “capture pads” between other thin film circuit features, perform electroplating, and then mask all features except for the capture pads to create these features. Protrusions are formed. Subsequently, a relatively small raised contact pad is electroplated thereon. The capture pad needs to be relatively large to allow positioning errors that occur during the second exposure plating step that defines a smaller contact pad. Assuming that the maximum positioning error is δμm, the circular capture pad needs to have a diameter D given by:
d + 2δ
Where d is the diameter of the smaller raised contact pad feature to ensure positioning of the smaller feature on the capture pad. The extra space required on the capture pad that causes positioning errors results in space loss, and without this extra space, circuit wiring and other features can be placed.

  However, in the trend of the ICP industry, higher wiring density is regarded as important. The at least one aspect of the processing method of the present invention can provide a market competitive advantage because it can produce raised circuit features that do not require large capture pads. .

  In one embodiment of the present invention, a seed layer of chromium, nickel, or an alloy thereof can be optionally stacked on the dielectric substrate using a vacuum sputtering technique. Next, a thin film layer of nickel, copper, gold, platinum, palladium, or an alloy thereof is formed using a vacuum sputtering technique to form a first conductive layer having a thickness of up to about 500 nm. This is followed by plating of a conductive material such as tin, nickel, copper, gold, platinum, palladium or alloys thereof, and the total thickness of the first conductive layer is about 1 μm to about 5 μm. Make it thicker. This process may be performed on one or both sides of the dielectric substrate. Instead of these steps, a dielectric substrate in which a conductive material layer is laminated on one side or both sides may be used. The laminated conductive layer is typically about 1-5 μm thick. In either case, the dielectric substrate may be a polymer film having a thickness of about 10 μm to about 600 μm, such as polyester, polyimide, liquid crystal polymer, polyvinyl chloride, acrylate, or polyolefin. Note that suitable thicknesses are not limited to these exemplary ranges.

Using a standard dry or wet lamination technique, a first negative photoresist layer is laminated to at least one side of the dielectric substrate having a conductive coating. For example, hot roller lamination may be performed using a dry film, or moisture may be added to the integrated surface before the dry film is laminated. A suitable dry membrane is available as SF310 from MacDermid. Inc. of Waterbury, Massachusetts. The thickness of the photoresist is about 1 μm to about 50 μm. The exposed portion of the resist is then cross-linked by exposing the photoresist with ultraviolet light or other suitable radiation through a mask or exposure apparatus. A suitable energy level is about 50 mJ / cm ² to about 500 mJ / cm ² at a wavelength of about 365 nm. The mask is a negative image of the conductive layer features, eg, wiring. Next, the unexposed portions of the photoresist are developed with a suitable solvent. For example, in the case of a water-soluble resist, a dilute aqueous solution, for example, a 0.5 to 1.5% sodium or potassium carbonate aqueous solution is applied until an unexposed portion is removed to obtain a desired pattern. You may develop by immersing a board | substrate in aqueous solution or spraying aqueous solution on a board | substrate.

  Next, using standard electroplating or electroless plating techniques, another layer of conductive material is plated on the exposed portion of the existing conductive layer to a thickness less than the thickness of the photoresist. For example, when using a 40 μm thick dry film photoresist, an additional conductive layer is plated on the 1-5 μm first conductive layer to a thickness of about 15 μm to about 25 μm.

Next, a second photoresist layer is laminated to at least one side of the metal coated dielectric substrate using standard dry or wet lamination techniques. For example, hot roller lamination may be performed using a dry film, or moisture may be added to the integrated surface before the dry film is laminated. A pre-formed pattern is filled with a photoresist having sufficient flow characteristics. The exposed portion of the resist is then cross-linked by exposing the photoresist with ultraviolet light or other suitable radiation through a mask or exposure apparatus. A suitable energy level is about 50 mJ / cm ² to about 500 mJ / cm ² at a wavelength of about 365 nm. The photoresist layer may be exposed without exposing it to UV light for the location of raised features (eg, die attach or wiring bumps). Next, the unexposed portions of the photoresist are developed with a suitable solvent. Typically, the opening in the second photoresist layer of the raised feature is larger than the opening formed in the first photoresist layer of the raised feature. Larger openings in the second photoresist layer can further tolerate positioning errors when building the raised features. A positive resist may be used instead of the negative photoresist.

  Alternatively, the second photoresist layer may be imaged so as to form a channel in the second resist layer in the region where the raised features are to be placed. By removing the unexposed photoresist to form the channel, a rectangular cavity is formed on the portion of the wiring where the raised features are desired. The raised features are formed by plating the conductive material in the rectangular cavities. This process requires a looser alignment than the alternative described in the previous paragraph, because it is only necessary to accurately align the photoresist layer in one direction rather than in two directions in the material plane.

  Another electroplating step is used to form raised features where the maximum height of the raised features does not exceed the height of the first photoresist layer. Suitable conductive materials for this step include tin, nickel, copper, gold, platinum, palladium or alloys thereof.

  If desired, features may be etched into the dielectric film including the substrate by plating the circuit with a concentrated base bath and etching portions of the dielectric substrate that are not covered by the cross-linked resist. . The exposed portion of the dielectric substrate may be a non-metalized portion of the substrate exposed by an opening in the photoresist layer, or may be on a non-metalized surface of the dielectric substrate. This etching step requires that the unmasked region of the polymer film is brought into contact with the concentrated alkaline etchant. As described in U.S. Pat. No. 5,227,008 and U.S. Pat. No. 6,403,211 there are effective alkaline etchants for introducing holes and associated voids into the dielectric film. And aqueous solutions of alkali metal hydroxides and mixtures of these amines. The time requirement for the controlled thinning of the dielectric film depends on the type and thickness of the polymer film. In film etching using an alkali etchant heated to 50 ° C. to 120 ° C., a time of about 10 seconds to about 20 minutes is usually required.

  Usually, the entire photoresist is then removed from the circuit in a 2-5% aqueous solution of alkali metal hydroxide at about 20 ° C. to about 80 ° C., preferably about 20 ° C. to about 60 ° C. Subsequently, the exposed portion of the first conductive layer is subjected to sulfuric acid peroxidation available under the trade name PERMA-ETCH from Electrochemicals Inc. of Maple Plain, Minnesota. Etching with an etchant such as a hydrogen etchant.

  One embodiment of the present invention will be described with reference to FIGS. FIG. 1 a shows a substrate 105 having a first conductive layer 110 and a thick laminated photoresist layer 115. FIG. 1 b shows the structure after exposing the photoresist layer with a radiation pattern to form a crosslinked portion 120 and a non-crosslinked portion 125. FIG. 1c shows the structure after developing a non-crosslinked portion of the photoresist layer to form a patterned mask having a desired circuit wiring pattern formed on the first conductive layer. FIG. 1d shows a structure in which a second conductive layer 130 is formed on the exposed first conductive layer by electroplating using a continuous electrolytic plating method. The thickness of the electroplating layer is a fraction of the thickness of the photoresist layer and is usually about 20% to about 75%. FIG. 1 e shows a structure having a stacked second photoresist layer 135. FIG. 1 f shows the structure after exposing the second photoresist layer with a radiation pattern to form a crosslinked portion 140 and an uncrosslinked portion 145. FIG. 1g shows the structure after the uncrosslinked portion of the second photoresist layer has been developed to form a mask for the desired raised features, eg, die attach bumps, on the circuit pattern. Together, the first and second patterned photoresist layers form regions that define the desired raised features. These can be contacted with an electrolytic plating aqueous solution. FIG. 1h shows the next step of depositing the conductive material in the second continuous electrolytic plating only in the region 150 where the raised features are desired. The sum of the thicknesses of the first and second continuous electrolytic platings does not exceed the thickness of the first photoresist layer. This forms a clear symmetrical raised feature. The width of the raised feature is the same as the width of the circuit wiring or other lower circuit feature (eg, capture pad). FIG. 1 i shows the structure after removing the photoresist layer and etching the exposed portion of the first conductive layer. The resulting article is a circuit of varying thickness that makes the amount of space occupied by the raised features as small as possible and ensures that they function. In the method of the present invention, since it is not necessary to accurately align the photoresist layer, a circuit feature having a characteristic dimension with an imaging positioning error of 50% or more can be allowed.

  Another embodiment of the present invention is shown in FIGS. It illustrates the main aspects of the process flow. Peripheral process steps such as flash plating are not shown. In this embodiment, the raised circuit features are further formed using the following method. FIG. 2a shows the initial configuration. This is because a first photosensitive resist (photoresist) 115 is applied to a dielectric substrate 105 (eg, polyimide) having a first conductive layer (eg, copper) (not shown) on the surface to be coated with the photoresist. It is formed by coating. FIG. 2b illustrates that the first photoresist layer is then exposed with a radiation pattern to form a crosslinked portion 120 and the uncrosslinked portion of the photoresist is developed (ie, stripped) to produce the desired circuit image or It shows generating a pattern. FIG. 2c shows the next step of electroplating a conductive material onto the circuit pattern. A plated conductive material 130 is deposited over the exposed portion of the first conductive layer by a photoresist development process. The thickness of the second conductive layer is less than the thickness of the first photoresist layer. FIG. 2d shows that without plating the first photoresist layer after plating, a second photoresist layer is coated on the structure and exposed with a radiation pattern to form a cross-linked portion 140 to remove the photoresist. The next step is to develop the bridging portion to form a channel feature that extends perpendicular to the longitudinal axis of the circuit imaging (eg, wiring) feature. Since the conductive material is not plated up to the level of the first photoresist layer, a clear cavity 155 is formed by the side wall of the channel formed by the first photoresist layer and the second photoresist. These cavities are located in a portion of the circuit feature (eg, wiring). Next, further plating is performed to fill the cavity with a conductive material up to the height of the first photoresist layer. After performing the second plating step, all the photoresist is removed. Next, as shown in FIG. 2 e, the exposed portion of the first conductive layer is etched away, leaving an insulating wiring having a raised feature 150. The width of the raised feature is the same as the width of the circuit wiring. With the accuracy according to the invention, the raised features can be aligned with minimal error to the surrounding circuitry.

  Note that the opening defined in the photoresist layer is formed without accurately aligning the second photoresist layer with the first photoresist layer. By the method of the present invention, a fine pitch feature can be designed in the X direction and a coarse pitch feature can be designed in the Y direction. The channel defined by the second developed photoresist layer need not be precisely aligned with the circuit pattern in the first photoresist layer. This is because the circuit pattern generally extends along the X direction. The reason why channel imaging need not be accurately aligned in the Y direction is because the pitch of channel imaging is coarse.

  Although the foregoing description generally describes the formation of raised features having length dimensions, such as squares and rectangles, the method of the present invention may be applied to raised features having curved dimensions, such as circular and elliptical shapes. It can also be used for features. FIG. 3 shows an actual flip chip circuit having, for example, a circular raised feature formed by the method of the present invention. In order to form the structure shown in FIG. 3, the first photoresist layer, which was formed and developed, was patterned for a wiring having a circular pad having a diameter of about 100 μm at the end. After electroplating the conductive material and partially filling the pattern, a second layer of photoresist was deposited and developed. The pattern of the second layer of photoresist includes a continuous circular opening having a diameter of about 150 μm. A circular opening was placed approximately overlying the circular pad feature formed by the previous step. The conductive material was again electroplated to form a pad feature that was approximately the height of the first photoresist layer. The photoresist layer was then removed, leaving the wiring with raised circular pad features. The raised pad feature includes two layers of deposited conductive material having substantially the same diameter and is substantially vertically aligned. This embodiment of the method of the present invention set the desired raised feature diameter with the first photoresist layer. The opening in the second photoresist layer should not only be plated on the circular feature overlying the circular feature with sufficient accuracy, but also on the wiring that connects to the different pads. Is possible.

  The invention is illustrated by the following examples.

  To demonstrate the present invention, an article with circuitry and raised features was made. A 38 μm-thick polyimide film having 3 μm copper on one side was used as a substrate. A 30 μm thick photoresist layer was coated on the copper. The photoresist portion was exposed to radiation (crosslinked), and the non-crosslinked portion of the photoresist was developed to form a 50 μm wiring pattern. Next, a 15 μm thick copper layer was plated on the exposed copper parts between the remaining photoresist. A 30 μm thick second photoresist layer was then coated over the structure. The photoresist portion was exposed to radiation (crosslinked), and the non-crosslinked portion of the photoresist was developed to form a 100 μm wide channel pattern in the second photoresist layer. Next, a second copper layer having a thickness of 15 μm was plated on a copper portion plated in advance in a rectangular opening formed from the remaining portions of the first and second photoresist layers. The photoresist was removed to expose wiring with raised features in specific areas. Next, the wiring is separated by etching 3 μm of copper to remove the original copper coating on the substrate.

  Various modifications and alterations of this invention will become apparent to those skilled in the art without departing from the scope and spirit of this invention. It should be understood that the present invention is not unnecessarily limited to the embodiments described herein.

Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 shows the steps of an embodiment of the method of the invention. Fig. 4 illustrates digital imaging of a flip chip circuit formed using the method of the present invention.

Claims (20)

Providing a substrate;
Producing a first patterned layer of photoresist on the substrate;
Depositing a conductive material in a pattern formed by the photoresist to a thickness less than the thickness of the photoresist layer;
Creating a second patterned layer of photoresist at least partially overlying the first patterned layer of photoresist to expose at least a portion of the conductive material;
Additional conductive material was formed in the first and second layers of photoresist so that the height of the thickest portion of the conductive material did not exceed the height of the first layer of photoresist. Forming a film with the pattern.   The method of claim 1, further comprising removing at least a portion of the photoresist.   The method of claim 1, wherein the substrate comprises a metal coated dielectric material.   The method of claim 3, wherein the metal coating is less than 5 μm thick.   The method of claim 1, wherein the thickness of the first deposited conductive material is about 20% to about 75% of the thickness of the first photoresist layer.   The method of claim 1, wherein the first photoresist layer is about 40 μm thick.   The method of claim 6, wherein the first deposited conductive material is about 15 to about 25 μm thick.   The method of claim 1, wherein the substrate is a dielectric material and a conductive material is deposited on the dielectric material prior to producing the first patterned layer of photoresist.   The method according to claim 8, wherein the conductive material on the dielectric material is deposited by sputtering.   The method according to claim 8, wherein the conductive material on the dielectric material is deposited by lamination.   9. The method of claim 8, further comprising removing an exposed portion of the conductive material on the dielectric material after removing the photoresist covering the conductive material. Providing a substrate;
Applying an uncured photoresist layer to the substrate;
Curing at least a portion of the pattern to the photoresist;
Forming at least one first cavity in the photoresist by removing the uncured photoresist from the at least a portion;
Depositing a conductive material in the first cavity to a thickness less than a thickness of the photoresist layer;
Applying a second uncured photoresist layer to the photoresist and conductive material layer;
Curing a pattern to the photoresist except for at least one second portion, wherein a second portion at least partially overlaps the at least one first cavity;
Removing the uncured photoresist from the at least one second portion so that a second cavity at least partially overlaps the at least one first cavity; Forming a cavity in the photoresist;
Depositing the conductive material in the at least one second cavity to a desired thickness without the height of the thickest portion of the conductive material exceeding the height of the first layer of photoresist material. And a method comprising: Providing a dielectric film having a first surface and a second metal coated surface;
Applying an uncured photoresist layer to the second metal-coated surface of the dielectric film;
Curing at least a portion of the pattern to the photoresist;
Forming at least one cavity in the photoresist by removing the uncured photoresist from the at least a portion;
Depositing a metal in the first cavity to a thickness less than a thickness of the photoresist layer;
Applying a second uncured photoresist layer to the photoresist and metal layer;
Curing a pattern to the photoresist except for at least one second portion, wherein a second portion partially overlaps the at least one first cavity;
Removing the uncured photoresist from the at least one second portion so that a second cavity at least partially overlaps the at least one first cavity; Forming a cavity in the photoresist;
Depositing metal in the at least one second cavity to a desired thickness without the total height of the thickest portion of metal exceeding the height of the first layer of photoresist. ,Method. Removing at least a portion of the photoresist;
The method of claim 13, further comprising: removing the coated metal on the portion of the dielectric substrate that was covered with the removed photoresist. Providing a substrate;
Applying an uncured negative photoresist layer to the substrate;
Curing at least a portion of the pattern to the photoresist;
Forming at least one cavity in the photoresist by removing the uncured photoresist from the at least a portion;
Depositing a conductive material in the first cavity to a thickness less than a thickness of the photoresist layer;
Applying a positive photoresist layer to the negative photoresist and conductive material layer;
Forming an exposed positive photoresist pattern on the at least one second portion, wherein a second portion partially overlaps the at least one first cavity;
Removing the exposed positive photoresist from the at least a portion such that a second cavity at least partially overlaps the at least one first cavity; Forming into steps;
The total thickness of the highest portion of the conductive material portion of the structure does not exceed the height of the first layer of photoresist material, so that the conductive material is in the desired thickness within the at least one second cavity. Forming a film. A substrate,
A conductive layer having a wiring pattern;
A raised feature on a portion of the wiring, wherein the raised feature has a width that is substantially the same as a width of the wiring portion on which the raised feature is disposed.   The article of claim 16, wherein the raised features are square. A substrate,
A conductive layer having a wiring pattern;
A raised feature on a portion of the wiring having at least two layers of the same or different conductive material, wherein the two layers have substantially the same X and Y dimensions; And a raised feature that is substantially longitudinally aligned.   The article of claim 18, wherein the raised feature is round. The article of claim 19, wherein the raised feature is circular.

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