JP2007335972A - Driving method of ccd solid-state imaging element, and ccd solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CCD solid-state imaging element provided with an electric charge storage means for preventing the generation of longitudinal lines in an imaged image. <P>SOLUTION: In a driving method for transferring electric charges in a vertical direction while changing applied voltages to two electrodes in pairs at the same time among transfer electrodes V1 to V8 configuring vertical electric charge transfer paths of the CCD solid-state imaging element provided with: the vertical electric charge transfer paths; the electric charge storage means LM for receiving the signal electric charges transferred through each vertical electric charge transfer path and temporarily storing the signal electric charges; and a horizontal electric charge transfer path for receiving the stored electric charges in the electric charge storage means LM and transferring the electric charges in the direction of an output stage, the applied voltages to the two electrodes V3, V7 in pairs are changed in different timing (shifted by a time t) for time zones (time zones of timings g to j) when the stored electric charges in the electric charge storage means LM are transferred to the horizontal electric charge transfer path. Thus, potential variations of a semiconductor substrate whereon the electric charge storage means LM is formed are suppressed and a defect such as the formation of the longitudinal lines can be avoided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a CCD (Charge Coupled Devices) type comprising a line memory for temporarily storing and holding transfer charges at a connecting portion between a vertical charge transfer path (vertical shift register) and a horizontal charge transfer path (horizontal shift register). The present invention relates to a solid-state imaging device, and more particularly to a CCD solid-state imaging device capable of capturing a high-quality image and a driving method thereof.

  An example of a CCD type solid-state imaging device having a line memory that temporarily stores and holds transfer charges at a connection portion between a vertical charge transfer path and a horizontal charge transfer path is described in Patent Document 1 below. Such a CCD type solid-state imaging device will be described with reference to FIG.

  On the semiconductor substrate of the CCD type solid-state imaging device 100, a large number of photodiodes 101 (R, G, B indicate the colors (red, green, blue) of the color filters stacked on each photodiode. ) Are arranged in a two-dimensional array, in the example shown in a square lattice, and a vertical charge transfer path 102 is formed along each column of the photodiodes 101. The vertical charge transfer path 102 includes a buried channel and vertical transfer electrodes V1, V2,..., V8 stacked thereon via an insulating film.

  Each vertical charge transfer path 102 includes two vertical transfer electrodes for one photodiode 101. In the illustrated example, the vertical transfer electrode on the upper side in the vertical direction and the photodiode 101 are connected by a read gate 103. The light receiving charge (signal charge) of the photodiode 101 is read out into a potential packet formed under the corresponding vertical transfer electrode through the reading gate 103. The read signal charges are transferred in the direction of the lower side of the semiconductor substrate by applying transfer pulses φV1, φV2,... ΦV8 to the vertical transfer electrodes V1, V2,.

  A line memory 104 connected to the end of each vertical charge transfer path 102 is provided on the lower side of the semiconductor substrate 100, and a horizontal charge transfer path 105 is provided in parallel with the line memory 104. The line memory 104 includes an impurity region partitioned by an element isolation unit corresponding to each vertical charge transfer path, an electrode stacked thereon via an insulating film, and an electrode to which a pulse signal φLM independent of the transfer pulse is applied. The signal charge transferred by the vertical charge transfer path 102 is received and temporarily stored.

  The horizontal charge transfer path 105 includes a buried channel and horizontal transfer electrodes H1 and H2 stacked on the insulating channel via an insulating film. The signal charge transferred from the line memory 104 is output by transfer pulses φH1 and φH2. Transfer in the column direction.

  An output amplifier 106 is provided at the output stage of the horizontal charge transfer path 105. The output amplifier 106 outputs a voltage value signal corresponding to the amount of signal charges transferred to the output stage of the horizontal charge transfer path 105 as an image signal.

  FIG. 6 is a schematic cross-sectional view of approximately 1.5 photodiodes shown in FIG. In this solid-state imaging device 100, a p-well layer 111 is formed on the surface portion of an n-type silicon substrate 110, and a pn junction (photodiode: photoelectric conversion) is formed between the surface portion of the p-well layer 111 and the p-well layer 111. An n region 112 constituting the device is formed.

  In the illustrated example, a high-concentration p region 113 constituting an element isolation region is formed on the left side of the n region 112, and a surface p layer 115 continuous with the p region 113 is provided on the surface of the n region 112. In the p-well layer 111, an n region (buried channel) 116 constituting a vertical charge transfer path for receiving and transferring the signal charge accumulated in the n region 112 is provided on the right side of the n region 112.

  A gate insulating film 120 made of silicon oxide is stacked on the outermost surface of the semiconductor substrate 110 on which these regions 112, 113, 115, and 116 are formed, and a light receiving surface of a photodiode (n region 112) is formed thereon. A light shielding film 121 having an opening 121a is laminated thereon. Under the light shielding film 121, a transfer electrode film (polysilicon film) 122 constituting a vertical charge transfer path is embedded via an insulating layer 123. A planarizing layer 125 is laminated on the light shielding film 121, a color filter layer 126 is laminated thereon, and a top microlens 127 is laminated on the top.

JP 2000-350099 A

  In the CCD type solid-state imaging device described with reference to FIGS. 5 and 6, when the signal charges transferred to the line memory 104 by the vertical charge transfer paths in the odd-numbered columns and even-numbered columns are transferred to the horizontal charge transfer paths, There is a case where an operation of alternately transferring a signal charge on the odd-numbered vertical charge transfer path and a signal charge on the even-numbered vertical charge transfer path from the corresponding part of the line memory 104 to the horizontal charge transfer path may be performed.

  In this case, for example, when the signal charges in the odd-numbered columns (or even-numbered columns) are transferred to the horizontal charge transfer path, the signal charges in the even-numbered columns (or odd-numbered columns) are held on the line memory 104 and transferred horizontally. If the solid-state imaging device is not driven so as not to leak to the path 105 side, a problem occurs. This will be described with reference to FIGS.

  When the CCD type solid-state imaging device as shown in FIG. 5 is driven in four phases, the transfer pulse φV1 applied to the vertical transfer electrode V1 is usually the same as the transfer pulse φV5 applied to the vertical transfer electrode V5 as shown in FIG. Similarly, φV2 = φV6, φV3 = φV7, and φV4 = φV8. That is, the same transfer pulse is applied to two pairs of electrodes (V1 and V5, V2 and V6, V3 and V7, V4 and V8).

  By applying the transfer pulses φV1 to φV4 to the electrodes V1, V2,..., V8, the length of the potential packet containing the signal charge in the direction along the vertical charge transfer path is 2 as shown in FIG. The process proceeds in the direction of the line memory (LM) 104 while expanding / contracting the electrode portion → the three electrode portion → the two electrode portion →.

  During the period in which the vertical charge transfer path is stopped, that is, the charge holding period, the signal charge is accumulated in the potential packet for two electrodes of the four electrodes, and the state immediately before that is the potential packet for three electrodes. Is accumulated within.

  When the potential packet is changed from the three-electrode state to the two-electrode state, that is, the electrodes V3 and V7 shown in FIGS. 8A and 8B are changed from the potential VM (for example, 0V) to the potential VL (for example, −8V). At timing k, when the pulse φLM applied to the electrode of the line memory 104 for transferring charges from the odd-numbered line memory to the horizontal charge transfer path is in the Lo state (the potential packet of the line memory becomes shallow). 6), the potential of the p-well layer 111 shown in FIG. 6 is greatly shaken by the influence of the VL voltage applied to the electrodes V3 and V7.

  As a result, there occurs a moment when the potential of the potential packet of the line memory 104 provided in the p-well layer 111 becomes further shallow. When the amount of signal charge accumulated in the potential packet is small, that is, there is no problem if the signal charge amount is obtained by photographing a dark scene, but the signal charge is close to the saturation amount in the potential packet after photographing a bright scene. Is accumulated, as shown in FIG. 8B, the signal charge held in the line memory of the even-numbered column overflows to the horizontal charge transfer path side.

  That is, the overflow of the even-numbered signal charge is added to the odd-numbered signal charge, and the amount of the even-numbered signal charge is reduced by the overflow. If this phenomenon occurs every time signal charge is transferred in the vertical direction, the signal charge amount in the odd-numbered columns increases, the signal charge amount in the even-numbered columns decreases, and vertical lines occur in the captured image of the bright scene. This causes the problem of end up.

  An object of the present invention is to provide a driving method of a CCD solid-state imaging device and a CCD solid-state imaging device capable of preventing the occurrence of vertical lines even when a bright scene is photographed.

  A method for driving a CCD solid-state imaging device and a CCD solid-state imaging device according to the present invention include a plurality of vertical charge transfer paths, charge holding means for receiving and temporarily holding signal charges transferred by the vertical charge transfer paths, A voltage applied to two pairs of electrodes among the vertical transfer electrodes constituting the vertical charge transfer path of a CCD type solid-state imaging device having a horizontal charge transfer path that receives the stored charge of the charge holding means and transfers it in the direction of the output stage. In a driving method or the like that performs charge transfer in the vertical direction while changing simultaneously, the potential level of the charge holding means is held at the charge transfer level in order to transfer the accumulated charge of the charge holding means to the horizontal charge transfer path. In a certain time zone, the voltage applied to the pair of two electrodes is changed at different timing for each electrode.

  In the CCD solid-state imaging device driving method and the CCD solid-state imaging device according to the present invention, the signal charges transferred by the vertical charge transfer path and held in the charge holding means are converted into signals by the vertical charge transfer paths in odd columns. Charges and signal charges from the vertical charge transfer paths in even columns are transferred to the horizontal charge transfer paths at different timings.

  According to the present invention, in the time zone in which the potential packet of the charge holding means is shallow in order to transfer the signal charge from the charge holding means to the horizontal charge transfer path, the potentials of the paired two electrodes are not changed simultaneously. Therefore, fluctuations in the potential of the semiconductor substrate can be suppressed. Thereby, the malfunction resulting from this fluctuation of potential is suppressed.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic view of the surface of a CCD solid-state imaging device according to an embodiment of the present invention. The illustrated CCD solid-state imaging device includes a CCD solid-state imaging device 10 and an imaging device driving circuit 30. Since the cross-sectional structure of the CCD type solid-state imaging device 10 is the same as that shown in FIG.

  The CCD solid-state imaging device 10 includes a large number of photodiodes 12 formed in an array on the surface of an n-type semiconductor substrate 11. In the illustrated example, the odd-numbered photodiodes 12 are formed so as to be shifted by 1/2 pitch with respect to the even-numbered photodiodes 12 to form a so-called honeycomb pixel array.

  Although the present embodiment will be described by taking a solid-state image sensor having a honeycomb pixel array as an example, the present embodiment is also applicable to the solid-state image sensor having a square lattice array described with reference to FIG.

  R, G, and B described in each photodiode 12 indicate the color (R = red, G = green, B = blue) of the color filter laminated on the photodiode, respectively.

  A vertical charge transfer path (vertical shift register: VCCD) 13 extending meandering in the vertical direction is formed between the photodiodes 12 adjacent in the horizontal direction, and each vertical charge transfer path is formed on the lower side of the semiconductor substrate 11. A line memory (charge holding means) 14 communicating with the end of 13 is provided.

  The vertical charge transfer path 13 includes an n-type buried channel formed in the p-well layer described with reference to FIG. 6 of the semiconductor substrate 11 and a vertical transfer electrode provided on the buried channel via an insulating film. The

  The line memory 14 includes an n-type impurity region formed in the p-well layer described with reference to FIG. 6 of the semiconductor substrate 11 and an electrode LM provided on the impurity region via an insulating film. The impurity region of the line memory 14 is partitioned corresponding to each vertical charge transfer path by the element isolation portion.

  The line memory 14 is provided with a horizontal charge transfer path (horizontal shift register: HCCD) 15. The horizontal charge transfer path 15 is also composed of an n-type buried channel formed in the p-well layer and horizontal transfer electrodes H1 and H2 provided on the buried channel via an insulating film. An output amplifier 16 is provided at the output stage of the horizontal charge transfer path 15.

  The signal charges accumulated in accordance with the amount of light received by each photodiode 12 are read out to the adjacent vertical charge transfer path 13, transferred in the direction of the line memory 14, and temporarily accumulated in the line memory 14. This signal charge is transferred to the horizontal charge transfer path 15 by applying a drive pulse φLM to the electrode LM of the line memory 14, and the signal charge transferred to the horizontal charge transfer path 15 is transferred along the horizontal charge transfer path 15. Are transferred to the output terminal. Then, the output amplifier 16 provided at the output terminal of the horizontal charge transfer path outputs a voltage value signal corresponding to the signal charge amount.

  The terms “vertical” and “horizontal” are used, but this simply means “one direction” or “a direction substantially perpendicular to this one direction”.

  The image sensor driving circuit 30 receives a command from a control CPU provided on the side of a device such as a digital camera in which the CCD solid-state imaging device is incorporated, and drives the vertical charge transfer path 13 of the CCD solid-state imaging device 10. Transfer pulses φV 1 to φV 8, horizontal transfer pulses φH 1 and φH 2 that drive the horizontal charge transfer path 15, and a pulse φLM that drives the electrode LM of the line memory 14 are generated and output to the CCD solid-state imaging device 10.

  FIG. 2 is an enlarged schematic diagram in the dotted rectangular frame II shown in FIG. A vertical charge transfer path 13 meandering in the vertical direction is provided on the side of each column of photodiodes 12 arranged in a honeycomb. V <b> 1, V <b> 2,..., V <b> 8 illustrated are vertical transfer electrodes provided in the vertical charge transfer path 13.

  The line memory 14 is not provided in proximity to the photodiode 12 closest to the line memory 14 but is provided at a position separated by a predetermined distance between the vertical charge transfer paths 13 of each column. This is because the intervals are equal and connected to the line memory 14 or the horizontal charge transfer path 15. Vertical charge transfer electrodes V5, V6, V7, V8, V1, and V2 are also provided in the extended portion of the vertical charge transfer path between the predetermined distances.

  As a result, the electrodes LM of the line memory 14 (shown separately but driven by the same pulse φLM) are arranged at equal intervals in the horizontal direction, and the electrodes LM are arranged in the horizontal charge transfer path 15 and so on. The horizontal transfer electrodes H1 and H2 are alternately arranged at intervals.

  FIG. 3 is a diagram illustrating drive timing in the CCD solid-state imaging device according to the present embodiment. The general operation is as follows.

  When charge transfer is performed in the vertical charge transfer path (vertical shift register), the signal charge of each photodiode for one row is transferred from each vertical charge transfer path to the line memory and stored and held.

  Next, among the signal charges on the line memory, the signal charges in the odd-numbered columns are transferred to the horizontal charge transfer path (horizontal shift register), and then the horizontal charge transfer path transfers this signal charge to the output stage side. . Thereby, an image signal corresponding to the charge amount of each signal charge in the odd-numbered column is output from the output amplifier.

  Next, the signal charges in the even-numbered columns are transferred from the line memory to the horizontal charge transfer path on the empty horizontal charge transfer path. The horizontal charge transfer path transfers this signal charge to the output stage side. As a result, an image signal corresponding to the charge amount of each signal charge in the even column is output from the output amplifier.

  By repeating the above operation, an image signal corresponding to the signal charge of each row of photodiodes shown in FIG. 1 is output to the outside of the imaging apparatus.

  In the present embodiment, when the above-described drive control of the image sensor is performed, in the present embodiment, a time zone in which the potential packet of the line memory is shallow (a time zone in which the electrode LM of the line memory is maintained at the charge transfer level (Lo level)). ), The timing control of the vertical transfer pulse is performed as follows.

  In the state of the potential packet shown in the uppermost stage of FIGS. 4A and 4B, that is, the potential packet is formed under the electrodes V4 and V5 and the electrodes V8 and V1, and the signal charge is accumulated in each potential packet. The potentials of the electrodes V2 and V6 change from the potential VL to the potential VM at the timing a shown in FIG.

  As a result, each potential packet spreads over three electrodes, and the potential packet close to the line memory loses its barrier to the line memory, and the signal charge in this potential packet flows into the potential packet of the line memory. .

  When the potential of the electrodes V4 and V8 changes from the potential VM to the potential VL at the next timing b, the potential packet on the vertical charge transfer path is reduced from three electrodes to two electrodes, and at the next timing c, the potentials of the electrodes V7 and V3. Changes from the potential VM to the potential VL, the potential packet spreads over three electrodes in the line memory direction.

  Hereinafter, timing d when the potentials of the electrodes V1 and V5 are changed from VM to VL, timing e when the potentials of the electrodes V4 and V8 are changed from VL to VM, timing f when the potentials of the electrodes V2 and V6 are changed from VM to VL, electrodes V1, By proceeding with the timing g at which the potential of V5 changes from VL to VM, the potential packet repeats expansion and contraction of 2 electrodes → 3 electrodes → 2 electrodes → 3 electrodes, and signal charges are transferred in the direction of the line memory. Is called.

  The timings g1 and g2 shown in FIG. 3 are the same timing, but the timing g1 indicates the timing when the electrodes V1 and V5 change from the potential VL to the potential VM, and the timing g2 indicates that the potential of the line memory LM is at the Hi level (charge accumulation level). ) To Lo level (charge transfer level).

  As shown in FIG. 4, when the potentials of the electrodes V1 and V5 change to the potential VM at the timing g1, the potential packet spreads over three electrodes. At the same timing g2, the potential of the line memory LM changes to the Lo level. At this time, the potential of the horizontal transfer electrode H1 of the horizontal charge transfer path aligned with the line memory of the odd-numbered column is at the Hi level, and the potential of the horizontal transfer electrode H2 aligned with the line memory of the even-numbered column is at the Lo level. It has become.

  A barrier BA is formed between the horizontal transfer electrodes H1, H2 and the line memory LM, and this barrier BA varies with the potential levels of the horizontal transfer electrodes H1, H2. For this reason, when the potential of the line memory LM changes to the Lo level at the timing g2, the accumulated charges of the odd-numbered line memory LM flow into the potential packet formed under the horizontal transfer electrode H1.

  However, even if the potential of the line memory LM changes to the Lo level, a barrier BA exists between the potential packet of the even-numbered line memory LM and the potential packet formed under the horizontal transfer electrode H2. The accumulated charge in the line memory LM in the even-numbered column remains accumulated in the potential packet of the line memory LM.

  However, at this time (when the line memory is at the Lo level and the potential packet is shallow), the potential of the p-well layer in which the line memory LM is formed fluctuates greatly, and the lines in the even-numbered columns If the signal charge amount stored in the memory LM is close to the saturation charge amount, the charge stored in the line memory of the even-numbered column leaks to the potential packet below the horizontal transfer electrode H2 over the barrier BA. This leaked charge is mixed with the signal charges in the odd-numbered columns along with the charge transfer in the horizontal charge transfer path, and the above-mentioned problem described in [Problems to be solved by the invention] occurs.

  Therefore, in the time zone in which the potential of the line memory is held at the Lo level, the potential of the vertical transfer electrode V3 is changed from the potential VM to the potential VL at the timing h, and the vertical transfer is performed at the timing i shifted from the timing h by the time t. The potential of the electrode V7 is changed from the potential VM to the potential VL.

  As a result, compared to the case where the potentials of the electrodes V3 and V7 are simultaneously changed from the potential VM to the potential VL (in the case of FIG. 7), the potential fluctuation in the p-well layer is suppressed, and the accumulated charge in the line memory LM in the even-numbered columns Leakage to the horizontal charge transfer path is suppressed.

  At the next timing j, the potential of the line memory LM is changed from the Lo level to the Hi level. Thereafter, as shown in FIG. 3, the output of the signal charges in the odd-numbered columns through the horizontal charge transfer path, the line memories in the even-numbered columns. Charge transfer from the LM to the horizontal charge transfer path, and output of the signal charges in the even-numbered columns through the horizontal charge transfer path are performed. As a result, the potential state on the vertical charge transfer path becomes the uppermost state in FIGS. 4A and 4B, and thereafter, the same operation as described above is repeated, so that the image signal for one screen becomes the horizontal charge. Output from the transfer path.

  As described above, according to the present embodiment, since the vertical charge transfer and the charge transfer from the line memory to the horizontal charge transfer path can be performed simultaneously in parallel, the image signal is transmitted to the outside of the image sensor at a high frame rate. Can be read out. In addition, since the vertical charge transfer can be performed while suppressing the potential fluctuation of the well layer at this time, it is possible to suppress the degradation of the image quality of the captured image due to the potential fluctuation.

  Since the CCD solid-state imaging device driving method and the CCD solid-state imaging device according to the present invention can output high-quality captured image data at a high frame rate, the CCD solid-state imaging device mounted on a digital camera or the like can be used. It is useful to apply.

It is explanatory drawing of a CCD type solid-state imaging device provided with the line memory which concerns on one Embodiment of this invention. It is an expansion schematic diagram of the dotted-line rectangular frame II shown in FIG. 2 is a drive timing chart of the CCD type solid-state imaging device shown in FIG. 1. FIG. 4 is a transition diagram of potential states of charge transfer paths and line memories driven by the drive timing chart of FIG. 3. It is explanatory drawing of the CCD type solid-state imaging device provided with the conventional line memory. FIG. 6 is a schematic cross-sectional view of approximately one pixel of the CCD solid-state imaging device shown in FIG. 1 or FIG. 5. It is a timing chart explaining the subject of the present invention. FIG. 8 is a transition diagram of potential states of a charge transfer path and line memory driven by the drive timing chart of FIG. 7.

Explanation of symbols

10 CCD type solid-state imaging device 11, 110 Semiconductor substrate 12, 103 Photodiode (photoelectric conversion device)
13 vertical charge transfer path 14 line memory 15 horizontal charge transfer path 16 output amplifier 30 image sensor drive circuit 111 p well layer 116 embedded channel of vertical charge transfer path

Claims (4)

  A plurality of vertical charge transfer paths, charge holding means for receiving and temporarily holding signal charges transferred by each vertical charge transfer path, and a horizontal charge transfer path for receiving accumulated charges of the charge holding means and transferring them in the direction of the output stage. In the driving method of performing charge transfer in the vertical direction while simultaneously changing the applied voltage to two pairs of vertical transfer electrodes constituting the vertical charge transfer path of the CCD solid-state imaging device comprising: In the time zone in which the potential level of the charge holding means is held at the charge transfer level in order to transfer the accumulated charge of the means to the horizontal charge transfer path, the voltage applied to the pair of two electrodes is set for each electrode. A method for driving a CCD type solid-state imaging device, characterized by being changed at different timings.   The signal charge transferred by the vertical charge transfer path and held in the charge holding means is changed at different timings between the signal charge by the vertical charge transfer path in the odd-numbered column and the signal charge by the vertical charge transfer path in the even-numbered column. 2. The method for driving a CCD type solid-state imaging device according to claim 1, wherein the transfer is performed to the horizontal charge transfer path.   A plurality of vertical charge transfer paths; charge holding means for receiving and temporarily holding signal charges transferred by the vertical charge transfer paths; and a horizontal charge transfer path for receiving stored charges of the charge holding means and transferring them in the direction of the output stage. A CCD comprising a CCD solid-state imaging device and imaging device driving means for transferring charges in the vertical direction while simultaneously changing applied voltages to two pairs of vertical transfer electrodes constituting the vertical charge transfer path In the type solid-state imaging device, the image sensor driving means is in a time zone in which the potential level of the charge holding means is held at the charge transfer level in order to transfer the accumulated charge of the charge holding means to the horizontal charge transfer path. A CCD type solid-state imaging device comprising means for changing the voltage applied to the pair of two electrodes at different timings for each electrode.   The signal charge transferred by the vertical charge transfer path and held in the charge holding means is changed at different timings between the signal charge by the vertical charge transfer path in the odd-numbered column and the signal charge by the vertical charge transfer path in the even-numbered column. 4. The CCD solid-state image pickup device according to claim 3, wherein the image is transferred to the horizontal charge transfer path.

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