JP2007335722A - Semiconductor package and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stacked semiconductor package which can be made compact and has no decline in yield with an increase of the number of semiconductor chips to be stacked. <P>SOLUTION: On a semiconductor unit mounting portion of a package substrate 1, a plurality of semiconductor units 5A and 5B are mounted in layers. The individual semiconductor units 5A and 5B include semiconductor chips 7A and 7B, conductor layers 8A and 8B to which the semiconductor chips 7A and 7B are flip-chip bonded, and sealing resins 10A and 10B for sealing the semiconductor chips 7A and 7B and flip-chip bonding portions 9A and 9B between the conductor layers 8A and 8B and the semiconductor chips 7A and 7B. The conductor layers 8A and 8B of the plurality of semiconductor units 5A and 5B are electrically connected to the connection pad 3 of the package substrate 1, and the plurality of semiconductor units 5A and 5B and electrically connections are sealed by a sealing resin 13 between the conductor layers 8A and 8B and the connection pad 3 of the package substrate 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor package manufacturing method and a semiconductor package.

  In recent years, a stacked multi-chip package (Stacked Multi-Chip Package) in which a plurality of semiconductor chips are stacked and sealed in one package has been put into practical use in order to realize miniaturization and high-density mounting of semiconductor devices. (For example, refer to Patent Document 1). In such a stacked multichip package, a plurality of semiconductor chips are sequentially stacked on an interposer having mounting terminals. The plurality of semiconductor chips are stacked face up to each other in order to be electrically connected to the connection terminals of the interposer via bonding wires.

  In such a stacked multichip package, as the number of semiconductor chips stacked for higher density mounting increases, the number of pins increases, and as a result, the size is reduced so as to be as close to the chip size as possible. Becomes difficult. Moreover, in recent years, the number of signal lines has increased dramatically in order to increase the functionality of semiconductor chips. Therefore, the advantages of stacking semiconductor chips for miniaturization and high-density mounting are diminishing.

  In a conventional stack type multichip package, screening such as a burn-in test is performed after the package is manufactured (after resin sealing). For this reason, all such screening terminals must be output to the external terminals, which is also a factor that hinders downsizing of the stack type multichip package.

Further, since the screening is performed after the package is manufactured in this way, even if an initial failure or failure occurs in one of the semiconductor chips constituting the semiconductor package, the entire semiconductor package becomes defective. The yield of semiconductor packages decreases with the power of the number of stacked layers of each semiconductor chip. For example, when a semiconductor chip with a yield of 98% per chip is subjected to a burn-in test after stacking, the yield after stacking is reduced to 92% or less for 4 layers, and the yield after stacking is decreased to 88% for 6 layers. To do.
JP 2002-231879 A

  An object of the present invention is to provide a method of manufacturing a stack type semiconductor package that can be downsized to a size close to the chip size and that does not decrease the yield as the number of stacked semiconductor chips increases. And it is providing the semiconductor package manufactured by such a method.

  According to one aspect of the present invention, (a) a semiconductor chip is flip-chip connected to a conductive material, and the semiconductor chip and a flip-chip connecting portion between the conductive material and the semiconductor chip are sealed with a sealing material, Next, a step of fabricating a semiconductor unit having a conductive layer electrically connected to the semiconductor chip formed on the upper surface by patterning the conductive material, (b) a semiconductor unit mounting portion, and the semiconductor unit mounting A plurality of the semiconductor units are mounted in a stacked state on the semiconductor unit mounting portion of the package base having a connection pad arranged around the portion and a mounting terminal electrically connected to the connection pad. (C) electrically connecting each conductor layer of the plurality of semiconductor units and the connection pads of the package base; and (d) A plurality of semiconductor units; and a step of sealing an electrical connection portion between each conductor layer of the plurality of semiconductor units and a connection pad of the package base with a sealing material. A method is provided.

  According to another aspect of the present invention, a package base having a semiconductor unit mounting portion, a connection pad disposed around the semiconductor unit mounting portion, and a mounting terminal electrically connected to the connection pad; A semiconductor unit comprising a semiconductor chip, a conductor layer to which the semiconductor chip is flip-chip connected, and a sealing material for sealing the semiconductor chip and a flip-chip connection portion between the conductor layer and the semiconductor chip, A plurality of semiconductor units mounted in a stacked state on the semiconductor unit mounting portion; a connection portion that electrically connects each conductor layer of the plurality of semiconductor units and a connection pad of the package base; and A plurality of semiconductor units, and a seal that seals electrical connection portions between the conductor layers of the plurality of semiconductor units and the connection pads of the package base. Semiconductor package characterized by comprising a timber is provided.

  According to the method for manufacturing a semiconductor package according to one aspect of the present invention and the semiconductor package according to another aspect, the size can be reduced to a size close to the chip size, and the yield decreases as the number of semiconductor chips increases. No semiconductor package can be obtained.

Embodiments of the present invention will be described below. In the following, embodiments of the present invention will be described with reference to the drawings. However, the drawings are provided for illustration, and the present invention is not limited to the drawings.
(First embodiment)

  First, the first embodiment will be described. FIG. 1 is a cross-sectional view showing a configuration of a semiconductor package according to the present embodiment.

  In FIG. 1, reference numeral 1 denotes a package substrate in which solder balls 2 are formed as mounting terminals and a wiring layer 4 having connection pads 3 electrically connected to the solder balls 2 is formed on the upper surface. Yes. Examples of the package substrate 1 include a polyimide film and a glass epoxy substrate. The connection pad 3 is made of, for example, copper or gold. On the package base 1, two semiconductor units, that is, a first semiconductor unit 5A and a second semiconductor unit 5B are stacked and mounted. In FIG. 1, 41 is a wiring layer formed on the lower surface of the package substrate 1, 42 is a connection via for electrically connecting the wiring layer 4 and the wiring layer 41, and 43 is a solder resist layer.

  The first semiconductor unit 5A includes a first semiconductor chip 7A, a first conductor layer 8A electrically connected to an electrode pad of the first semiconductor chip 7A, the first semiconductor chip 7A and the first semiconductor chip 7A. A first sealing resin 10A for sealing the electrical connection portion 9A between the semiconductor chip 7A and the first conductor layer 8A. The first semiconductor chip 7A is electrically connected to the first conductor layer 8A by flip chip connection. Similarly, the second semiconductor unit 5B includes a second semiconductor chip 7B, a second conductor layer 8B electrically connected to an electrode pad of the second semiconductor chip 7B, and a second semiconductor chip 7B. And a second sealing resin 10B for sealing the electrical connection portion 9B between the second semiconductor chip 7B and the second conductor layer 8B. The second semiconductor chip 7B is electrically connected to the second conductor layer 8B by flip chip connection. For example, a memory chip such as a NAND flash memory is applied to the first and second semiconductor chips 7A and 7B, but the present invention is not limited to this. Further, the flip chip connection of the first and second semiconductor chips 7A and 7B to the first and second conductor layers 8A and 8B may be either solid phase diffusion connection or metal fusion connection.

  In the first and second semiconductor units 5A and 5B, the first and second semiconductor chips 7A and 7B are both face up, and not only the second conductor layer 8B but also the surface of the first conductor layer 8A. Are also laminated so as to be exposed. The exposed first and second conductor layers 8A and 8B and the connection pads 3 of the wiring layer 4 formed on the upper surface of the package base 1 are electrically connected via bonding wires 11, respectively. Connected. Further, the lower surface of the second semiconductor unit 5B and the upper surface of the first semiconductor unit 5A, and the lower surface of the first semiconductor unit 5A and the upper surface of the package substrate 1 are bonded via an adhesive layer 12. Furthermore, the electrical connection portion between the first and second conductor layers 8A and 8B and the connection pad 3 formed on the upper surface of the package base 1, and the first and second semiconductor units 5A and 5B are sealed. The sealing resin 13 is collectively sealed by a mold. In some cases, as shown in FIG. 2, between the first conductor layer 8A and the second conductor layer 8B, between the first conductor layer 8A and the connection pad 3 on the package substrate 1, You may make it connect via the bonding wire 11, respectively.

  FIG. 3 is a cross-sectional view for explaining an example of a manufacturing method of the semiconductor unit 5 used as the first and second semiconductor units 5A and 5B. This method uses an etching method for pattern formation of the conductor layer 8.

  First, the semiconductor chip 7 is placed face down on the sheet-like conductive material 20, and the electrode pads of the semiconductor chip 7 and the conductive material 20 are joined (FIG. 3A). As the conductive material 20, for example, a metal sheet having a thickness of about 20 to 100 μm made of metal such as copper or iron is used. The surface of these metal sheets may be subjected to Sn plating, Ni / Au plating, or the like.

  Next, the semiconductor chip 7, the conductive material 20, and their electrical connection portions 9 are sealed by a collective molding of the sealing resin 10 (FIG. 3B). An epoxy thermosetting resin or the like is used for the sealing resin 10 to be molded. The electrical connection portion 9 between the semiconductor chip 7 and the conductive material 20 may be sealed with an underfill resin. For the underfill resin, for example, NCF (Non Conductive Film) is used.

  Furthermore, the thickness of the conductive material 20 is reduced to, for example, about 5 μm by etching (FIG. 3C). By performing such a thinning process, the patterning property of the conductor layer 8 can be enhanced.

  Subsequently, an etching resist layer 22 patterned by a photolithography method is formed on the lower surface of the thinned conductive material 20. That is, after a resist layer is formed on the entire lower surface of the conductive material 20 by roll lamination of a dry film resist or application of a liquid resist, this resist layer is exposed and developed to form a patterned resist layer 22 for etching ( FIG. 3 (d)).

  Thereafter, the portion of the conductive material 20 where the etching resist layer 22 is not formed is removed by etching, and the etching resist layer 22 is further removed, whereby the semiconductor unit 5 having the patterned conductor layer 8 is manufactured. (FIG. 3E).

  The semiconductor unit 5 can also be manufactured by the following method, for example. That is, FIG. 4 is a cross-sectional view for explaining another example of the method for manufacturing the semiconductor unit 5. This method uses an additive method for pattern formation of the conductor layer 8.

  First, the semiconductor chip 7 is placed face down on a support plate 23 having a smooth surface, and temporarily fixed with an adhesive 24 (FIG. 4A). Bumps 25 are formed in advance on the electrode pads of the semiconductor chip 7 and temporarily fixed so that the surface of the pumps 25 is in contact with the support plate 23. The material and thickness of the support plate 23 are not particularly limited as long as the support plate 23 can support the semiconductor chip 7. In general, a flat plate made of iron, aluminum or the like having a thickness of about 100 to 150 μm is used.

  Next, the semiconductor chip 7 temporarily fixed to the support plate 23 is sealed with a mold of a sealing resin 10 such as an epoxy thermosetting resin (FIG. 4B).

  The semiconductor chip 7 sealed with the sealing resin 10 is removed from the support plate 23, and the surface on the removed side, that is, the entire surface of the sealing resin 10 on the upper surface side of the semiconductor chip 7 is thinly conductive by flash plating or the like. A seed layer 26 is formed (FIG. 4C).

  A plating resist layer 27 patterned by photolithography is formed on the surface of the conductive seed layer 26. That is, after forming a resist layer on the entire surface of the conductive seed layer 26 by roll lamination of a dry film resist or application of a liquid resist, the resist layer 27 is exposed and developed to form a patterned resist layer 27 for plating. To do. Further, a copper plating layer 28 is formed by electrolytic copper plating on the conductive seed layer 26 where the resist layer 27 for plating is not formed (FIG. 4D).

  Thereafter, the plating resist layer 27 is removed, and unnecessary portions of the conductive seed layer 26 are removed by flash etching, whereby the semiconductor unit 5 having the patterned conductor layer 8 is fabricated (FIG. 4 ( e)).

  In the semiconductor unit 5 manufactured by the method as described above, since the conductor layer 8 and the electrode pad of the semiconductor chip 7 are joined before the patterning of the conductor layer 8, the connection reliability is high.

  The method shown in FIG. 4, that is, the method using the additive method for forming the pattern of the conductor layer 8 can form a fine pattern because the pattern side surface of the conductor layer 8 is almost vertical. From the viewpoint of being able to manufacture at a low cost and facilitating process management, the method shown in FIG. 3, that is, a method using an etching method for pattern formation of the conductor layer 8 is preferable.

  In the semiconductor package of the first embodiment shown in FIG. 1, for example, the solder balls 2 are formed using the first semiconductor unit 5A and the second semiconductor unit 5B manufactured by the method as described above as mounting terminals. The first and second semiconductors are disposed on the package base 1 on the upper surface of which the wiring layer 4 having the connection pads 3 electrically connected to the solder balls 2 is formed via the adhesive layer 12. The chips 5A and 5B are both mounted face-up and stacked so that not only the second conductor layer 8B but also the surface of the first conductor layer 8A is exposed, and the first and second conductor layers 8A are mounted. , 8B and the connection pads 3 on the upper surface of the package substrate 1 are connected by bonding wires 11 and then sealed together with a sealing resin 13.

  According to the semiconductor package of the present embodiment, screening such as a burn-in test can be performed at the stage of the semiconductor unit before manufacturing the package (before resin sealing). For this reason, the number of external terminals for such screening can be reduced, the size of the package can be reduced, and the yield of the semiconductor package can be improved.

  That is, FIG. 7 shows a stack type multichip package having a conventional structure in which a plurality of semiconductor chips are stacked and sealed as they are. In this stacked multi-chip package, a plurality of semiconductor chips 7 are stacked face-up on the same package base 1 as the semiconductor package in the first embodiment, and the electrode pads and the package base 1 of each semiconductor chip 7 are stacked. The upper connection pads 3 are electrically connected via bonding wires 11. The electrical connection portions by the plurality of semiconductor chips 7 and the bonding wires 11 are collectively sealed with a sealing resin 13.

  In such a stack type multi-chip package, screening such as burn-in test is performed after the package is manufactured (after resin sealing), so all the screening terminals must be output to the external terminals. Is inhibited. In addition, the yield of semiconductor packages decreases as the number of stacked semiconductor chips increases.

  On the other hand, in the semiconductor package of the present embodiment, since the burn-in test can be performed at the stage of the semiconductor unit, the number of external terminals for screening can be reduced, and the semiconductor package can be downsized. In addition, it is possible to suppress a decrease in yield as a semiconductor package accompanying an increase in the number of stacked semiconductor chips.

  Further, as described above, in the present embodiment, the first and second semiconductor chips 5A and 5B are joined to the first and second conductor layers 8A and 8B, respectively. Since it is performed before patterning, the connection reliability is high.

That is, FIG. 8 is a cross-sectional view showing a conventional semiconductor package manufacturing process.
In FIG. 8, first, bumps 31 are formed on the electrode pads of the semiconductor chip 7 with gold or the like (FIG. 8A). Next, the semiconductor chip 7 on which the bumps 31 are formed is placed face down on the package base 34 on which the mounting terminals 32 and the wiring layers 33 are formed (FIG. 8B). An underfill resin layer 35 is provided in advance on the wiring layer 33 and the package base 34. Thereafter, the bumps 31 provided on the semiconductor chip 7 and the wiring layer 33 are bonded by heating and pressing, and the underfill resin layer 35 is cured (FIG. 8C). Further, these are sealed with a sealing resin 36 (FIG. 8D).

  In such a semiconductor package, since the bumps 31 on the semiconductor chip 7 are bonded to the already patterned wiring layer 33, a highly accurate alignment technique is required to obtain high connection reliability.

  On the other hand, in the semiconductor package of the present embodiment, the first and second semiconductor chips 5A and 5B are joined to the first and second conductor layers 8A and 8B, respectively. Therefore, excellent connection reliability can be easily obtained.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 5 is a cross-sectional view showing the configuration of the semiconductor package according to the present embodiment. In addition, the same code | symbol is attached | subjected about the part which is common in 1st Embodiment mentioned above, and the overlapping description is abbreviate | omitted.

  As shown in FIG. 5, in the present embodiment, a third semiconductor unit 5C having substantially the same size as the first semiconductor unit 5A is stacked on the first semiconductor unit 5A. The third semiconductor unit 5C includes a third semiconductor chip 7C, a third conductor layer 8C electrically connected to an electrode pad of the third semiconductor chip 7C, the third semiconductor chip 7C, In addition to the third sealing resin 10C that seals the electrical connection portion 9C between the third semiconductor chip 7C and the third conductor layer 8C, the third conductor layer 8C of the third sealing resin 10C includes A fourth conductor layer 8D is formed on the surface opposite to the formed surface, that is, the lower surface of the third semiconductor chip 7C, and the third conductor layer 8C and the fourth conductor layer 8D 3 are electrically connected through the conductive pillars 17 penetrating the sealing resin 10C. The third semiconductor chip 7C is electrically connected to the third conductor layer 8C by flip chip connection. For example, a memory chip such as a NAND flash memory is applied to the third semiconductor chip 7C, but is not limited thereto. Further, the flip chip connection of the third semiconductor chip 7C to the third conductor layer 8C may be either solid phase diffusion connection or metal fusion connection.

  The first and third semiconductor units 5A and 5C are stacked so that the first conductor layer 8A of the first semiconductor unit 5C and the fourth conductor layer 8D of the third semiconductor unit 5C face each other. The bumps 16 provided on one of the first conductor layer 8A and the fourth conductor layer 8D (for example, the first conductor layer 8A) are joined to the other conductor layer (for example, the fourth conductor layer 8D). Is electrically connected. The third conductor layer 8 </ b> C of the third semiconductor unit 5 </ b> C and the connection pads 3 of the wiring layer 4 formed on the upper surface of the package substrate 1 are electrically connected via the bonding wires 11. Note that the fourth conductor layer 8D of the third semiconductor unit 5C and the first conductor layer 8A of the first semiconductor unit 5A are connected via a connecting material such as a solder ball or solder paste. Good.

  FIG. 6 is a cross-sectional view for explaining an example of a method of manufacturing a semiconductor unit used as the third semiconductor unit 5C.

  First, the semiconductor chip 7 is placed face down on a support plate 23 having a smooth surface similar to that used in FIG. 4, and temporarily fixed with an adhesive 24 (FIG. 6A). A bump 25 is formed in advance on the electrode pad 5 of the semiconductor chip 7 and temporarily fixed so that the surface of the pump 25 is in contact with the support plate 23. The support plate 23 is provided with a support column 29 for forming the conductive column 17 in advance.

  Next, the semiconductor chip 7 temporarily fixed to the support plate 23 is sealed with a mold of a sealing resin 10 such as an epoxy thermosetting resin (FIG. 6B).

  The semiconductor chip 7 sealed with the sealing resin 10 is removed from the support plate 23, and a thin conductive seed layer 26 is formed on the entire upper and lower surfaces of the semiconductor chip 7 of the sealing resin 10 by flash plating or the like. It forms (FIG.6 (c)).

  A plating resist layer 27 patterned by photolithography is formed on the surface of each conductive seed layer 26. That is, after a resist layer is formed on the entire surface of each conductive seed layer 26 by roll lamination of a dry film resist or application of a liquid resist, this resist layer is exposed and developed to form a patterned resist layer 27 for plating. Form. Further, a copper plating layer 28 is formed by electrolytic copper plating on the conductive seed layer 26 where the plating resist layer 27 is not formed (FIG. 6D).

  Thereafter, the plating resist layer 27 is removed, and unnecessary portions of the conductive seed layer 26 are removed by flash etching, whereby the patterned conductor layer 8 (in the semiconductor unit 5C, the third and fourth conductors). The semiconductor unit 5 having the layers 8C, 8D and the conductive pillars 17) is formed (FIG. 6E)).

  In the semiconductor package of the second embodiment shown in FIG. 5, for example, the third semiconductor unit 5C manufactured by the method as described above, together with the first semiconductor unit 5A, includes, for example, solder balls 2 as mounting terminals. On the package substrate 1 formed with the wiring layer 4 having the connection pads 3 electrically connected to the solder balls 2 on the upper surface, the third and first layers are connected via the adhesive layer 12. Each of the semiconductor chips is mounted face-up, and the space between the opposing first conductor layer 8A and fourth conductor layer 8D, third conductor layer 8C and the connection pad 3 on the upper surface of the package substrate 1 is measured. These are manufactured by electrically connecting the bumps 16 and the bonding wires 11 together and then sealing them together with a sealing resin 13.

  According to the semiconductor package of the second embodiment, similar to the semiconductor package of the first embodiment, screening such as a burn-in test can be performed before the package is manufactured (before resin sealing) and at the stage of the semiconductor unit. Therefore, the number of external terminals for such screening can be reduced, the size of the package can be reduced, and the yield of the semiconductor package can be improved. In addition, since the first and third semiconductor chips 5A and 5C are joined to the first and third conductor layers 8A and 8C before the patterning of the conductor layers 8A and 8C, the connection reliability is improved. Can be expensive.

  Furthermore, according to the semiconductor package of the second embodiment, by using the third semiconductor unit 8C in which the fourth conductor layer 8D is formed, the same or nearly the same size semiconductor unit is stacked and mounted. can do.

  In the first and second embodiments described above, two semiconductor units are stacked, but the number of stacked semiconductor units is not particularly limited. Although not shown, in the first embodiment, the second semiconductor unit 8B is configured on the second semiconductor unit 8B in the same manner as the third semiconductor unit 8C in the second embodiment having substantially the same size. A fifth semiconductor unit is mounted, or in the second embodiment, a fifth semiconductor unit 8C is configured on the third semiconductor unit 8C in a smaller size and the same as the first semiconductor unit 8A. It is also possible to mount a semiconductor unit. As described above, the number of stacked semiconductor units and the type of stacked semiconductor units are not particularly limited, and can be appropriately selected according to the application.

  Furthermore, in both the first embodiment and the second embodiment, the mounting terminal is an area type, but it goes without saying that it may be a peripheral type provided only in the peripheral portion. .

  Embodiments of the present invention can be expanded or modified within the scope of the technical idea of the present invention, and these expanded and modified embodiments are also included in the technical scope of the present invention.

It is sectional drawing which shows the structure of the semiconductor package which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the modification of the semiconductor package shown in FIG. It is sectional drawing which shows an example of the manufacturing process of the semiconductor unit used for manufacture of the semiconductor package which concerns on 1st Embodiment. It is sectional drawing which shows the other example of the manufacturing process of the semiconductor unit used for manufacture of the semiconductor package which concerns on 1st Embodiment. It is sectional drawing which shows the structure of the semiconductor package which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the example of the manufacturing process of the semiconductor unit used for manufacture of the semiconductor package which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the conventional stack type multichip package. It is sectional drawing which shows the manufacturing process of the conventional semiconductor package.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Package base | substrate, 2 ... Solder ball, 3 ... Connection pad, 5 ... Semiconductor unit, 5A ... 1st semiconductor unit, 5B ... 2nd semiconductor unit, 5C ... 3rd semiconductor unit, 8 ... Conductor layer, 8A ... 1st conductor layer, 8B ... 2nd conductor layer, 8C ... 3rd conductor layer, 8D ... 4th conductor layer, 9 ... Electrical connection part, 9A ... 1st electrical connection part, 9B ... 2nd electrical connection part, 9C ... 3rd electrical connection part, 10, 13 ... Sealing resin, 10A ... 1st sealing resin, 10B ... 2nd sealing resin, 10C ... 3rd sealing Stop resin, 11 ... bonding wire, 16, 25 ... bump, 17 ... conductive column, 20 ... conductive material, 22 ... resist layer for etching, 26 ... conductive seed layer, 28 ... copper plating layer.

Claims (5)

(A) The semiconductor chip is flip-chip connected to the conductive material, the semiconductor chip and the flip-chip connecting portion between the conductive material and the semiconductor chip are sealed with a sealing material, and then the conductive material is patterned. A step of producing a semiconductor unit in which a conductor layer electrically connected to the semiconductor chip is formed on the upper surface;
(B) On the semiconductor unit mounting portion of the package base having a semiconductor unit mounting portion, a connection pad arranged around the semiconductor unit mounting portion, and a mounting terminal electrically connected to the connection pad; Mounting a plurality of the semiconductor units in a stacked state; and
(C) electrically connecting each conductor layer of the plurality of semiconductor units and connection pads of the package base;
(D) a semiconductor comprising: a plurality of semiconductor units; and a step of sealing an electrical connection portion between each conductor layer of the plurality of semiconductor units and a connection pad of the package base with a sealing material. Package manufacturing method.   2. The method of manufacturing a semiconductor package according to claim 1, wherein the patterning of the conductive material is performed by an etching method.   2. The method of manufacturing a semiconductor package according to claim 1, wherein the patterning of the conductive material is performed by an additive method.   At least one of the semiconductor units has another conductor layer electrically connected to the conductor layer formed on the upper surface via a conductive column provided through the sealing material on the lower surface. The method of manufacturing a semiconductor package according to claim 1, wherein the semiconductor package is manufactured. A package base having a semiconductor unit mounting portion, a connection pad disposed around the semiconductor unit mounting portion, and a mounting terminal electrically connected to the connection pad;
A semiconductor unit comprising a semiconductor chip, a conductor layer to which the semiconductor chip is flip-chip connected, and a sealing material for sealing the semiconductor chip and a flip-chip connection portion between the conductor layer and the semiconductor chip, A semiconductor unit mounted in a stacked state on the semiconductor unit mounting portion, and
A connection part for electrically connecting each conductor layer of the plurality of semiconductor units and a connection pad of the package base;
A semiconductor package comprising: the plurality of semiconductor units; and a sealing material that seals electrical connection portions between the conductor layers of the plurality of semiconductor units and the connection pads of the package base.

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