JP2007329301A - Method and device for analyzing defect distribution feature - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a defect distribution feature analyzing device capable of extracting the feature distribution of a distribution state of defective chips, based on the determination result of an electric inspection, through the use of a method being the same as a pattern defect feataure distribution extracting method. <P>SOLUTION: The defect distribution feature analyzing device 2 extracts the feature distribution from a real defect distribution, based on the position coordinates of the plurality of real defects on a wafer which are obtained by inspecting the wafer in the middle of the manufacturing of the chips on the wafer. The device 2 includes a virtual defect generator 4 for generating a plurality of virtual defects to be arranged at position coordinates converted based on the arrayal information of the defective chips on the wafer, which is determined by electrically inspecting the chips after the chips are manufactured. The feature distribution is extracted from the distribution of the virtual defects, based on the position coordinates of the virtual defects. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention provides a defect distribution feature analysis that extracts a characteristic distribution of defects from arrangement information on a wafer of a plurality of defective chips determined by electrical inspection of the chips after a plurality of chips are produced on the wafer. The present invention relates to a method and a distribution feature analysis apparatus for defects.

  In the manufacture of semiconductor devices, a plurality of chips are produced on a wafer, and for the purpose of improving and stabilizing the yield of the plurality of chips, a pattern defect inspection or foreign matter inspection is performed on each wafer after each manufacturing process, and the inspection results Analysis has been carried out. For early detection of the cause of chip defects, it is important to detect pattern defects and foreign substances by inspection within each manufacturing process. The inspection results are monitored, and the number of pattern defects and foreign substances generated is a specified value. There has been proposed a monitoring method for issuing an alarm when the above is reached (see, for example, Patent Document 1).

  Also, after the manufacture of the semiconductor device is completed, an electrical inspection is performed on all the chips on the wafer, and whether each chip is a good chip or a defective chip is determined for each chip. There has been proposed a method for searching for the cause of defects by using it. In this exploration method, a method has been proposed in which a fail bit map as a determination result is combined with inspection results of pattern defects and foreign matters in each manufacturing process (see, for example, Patent Document 2).

In addition, the pattern defect distribution is analyzed from the position coordinates on the wafer where the pattern defect occurred, and the pattern defect distribution is changed into a repeated distribution feature, a dense distribution feature, a linear distribution feature, a ring, a block distribution feature, a random distribution feature, etc. There has been proposed a method for monitoring the presence or absence of a specific distribution on a wafer by classification (see, for example, Patent Document 3).
JP 2004-63708 A Japanese Patent No. 2986410 JP 2003-59984 A

  For the early detection of the cause of defects, it is important to detect pattern defects and foreign substances by inspection within each manufacturing process as proposed in Patent Document 1, but patterns that have been miniaturized in recent years It is difficult to detect all pattern defects and foreign matters that cause defects in a chip having a defect. In addition, due to restrictions on the number of pattern defect and foreign matter inspection devices introduced, it is difficult to inspect all wafers in the manufacturing process, and the cause of defects can be determined only by pattern defect inspection of some wafers in the manufacturing process. It is difficult to discover.

  On the other hand, electrical inspection is performed on all chips on all wafers, but because the number of data of judgment results is enormous, it is difficult to grasp the distribution of defective chips on all wafers. Managed by chip yield per wafer. However, in the management by yield, when the total number of chips per wafer is small, the generation of a small number of defective chips greatly reduces the yield, but when the total number of chips is large, the yield is increased even if a certain number of defective chips are generated. It was hard to be detected as a drop in

  Even if the yield is the same, that is, even if the number of defective chips is the same, the distribution of defective chips randomly distributed over the entire surface of the wafer often causes each defective chip to have a different cause of failure. In a distribution having a dense distribution feature concentrated in one place or a distribution having a characteristic distribution having the same tendency among a plurality of wafers, defective chips are often generated due to the same cause of failure. Abnormal wafers with defective chips due to the same cause of failure need to be detected early because it will lead to the occurrence of defective chips due to the cause of failure later, but as mentioned above, pattern defect inspection of some conventional wafers In addition, it is considered that abnormal wafers are hard to be found in the yield management of electrical inspection.

  In order to find abnormal wafers, the distribution of defective chips in the determination results of electrical inspection performed on all wafers may be classified into a specific characteristic distribution. Although the method for classifying the data into a specific characteristic distribution is proposed in Patent Document 3, it is intended for pattern defects and cannot be directly applied to the determination result of the electrical inspection.

  Accordingly, an object of the present invention is to provide a defect distribution feature analysis method capable of extracting a characteristic distribution of a defective chip distribution from a determination result of an electrical inspection by a method similar to the method for extracting a pattern defect characteristic distribution. Another object of the present invention is to provide a defect distribution feature analysis apparatus.

  The present invention that has solved the above problems is based on the position coordinates on the wafer of actual defects such as a plurality of pattern defects and foreign matters obtained by inspecting the wafer during the production of a plurality of chips on the wafer. In a defect distribution feature analysis method and a defect distribution feature analysis apparatus for extracting a characteristic distribution from a distribution of actual defects, a plurality of defective chips determined by electrical inspection of the chip after the chip is manufactured A plurality of virtual defects arranged at the position coordinates converted based on the arrangement information on the wafer are generated, and the characteristic distribution is extracted from the distribution of the virtual defects based on the position coordinates of the virtual defects. It is characterized by that.

  According to the present invention, a distribution feature analysis method and a distribution feature analysis that enable a characteristic distribution of a defective chip distribution to be extracted from a determination result of an electrical inspection by a method similar to the pattern defect characteristic distribution extraction method. Equipment can be provided.

  Hereinafter, an embodiment of a defect distribution feature analysis method and a defect distribution feature analysis apparatus according to the present invention will be described with reference to the drawings.

  As shown in FIG. 1, a distribution feature analysis device (defect distribution feature analysis device) 2 according to an embodiment of the present invention is used in a distribution feature analysis system 1. The distribution feature analysis system 1 includes a pattern defect inspection apparatus 21 and 22 that generates pattern defect data by detecting a pattern defect and a foreign substance by inspecting the wafer during the production of a plurality of chips on the wafer, and the generated pattern defect. A pattern defect data server 6 for storing data, and after a plurality of chips are produced on the wafer, electrical inspection is performed on the chips on the wafer, and a defective chip is detected as a determination result of the inspection to generate electrical inspection data. Electrical inspection apparatus 23 to 26, electrical inspection data server 7 having an electrical inspection database 10 for storing the generated electrical inspection data, and pattern defects on the wafer based on the electrical inspection data and pattern defect data And a distribution feature analysis device 2 for analyzing the characteristic distribution of defective chips.

  The pattern defect inspection devices 21 and 22, the pattern defect data server 6, the electrical inspection devices 23 to 26, the electrical inspection data server 7, and the distribution feature analysis device 2 are connected via a network 18. The electrical inspection data server 7 includes, in addition to the electrical inspection database 10, a chip placement map database 8 that stores a chip placement map indicating where the chips are placed on the wafer for each wafer, and the electrical power of defective chips. And a characteristic value conversion database 9 for storing a correspondence between the characteristic value for converting the characteristic value of the physical inspection data into the characteristic amount of the virtual defect and the characteristic amount.

  The distribution feature analysis apparatus 2 includes a distribution feature analysis unit 3 that analyzes the presence / absence of a feature distribution on the wafer of pattern defects and foreign matter based on the pattern defect data stored in the pattern defect data server 6, and a feature distribution A defect cause analysis unit 5 is provided for analyzing a manufacturing process and a manufacturing apparatus that cause a pattern defect and a foreign matter to be generated based on information on the abnormal wafer. The failure cause analysis unit 5 includes a feature amount comparison unit 19 that can determine the priority order for analyzing the manufacturing process and the manufacturing apparatus that caused the plurality of analyzed characteristic distributions.

  The distribution feature analysis apparatus 2 includes a virtual defect generation unit 4 that generates a plurality of virtual defects arranged at position coordinates on a wafer converted based on arrangement information of a plurality of defective chips on the wafer. For the generated virtual defect, the distribution feature analysis unit 3 and the defect cause analysis unit 5 can be moved in the same manner as the pattern defect and the foreign matter. Specifically, the distribution feature analysis unit 3 extracts a characteristic distribution from the distribution state of the virtual defect based on the position coordinates of the virtual defect. The defect cause analysis unit 5 analyzes a manufacturing process or a manufacturing apparatus that has caused a defective chip based on information on the abnormal wafer by using a wafer having a characteristic distribution as an abnormal wafer.

  The virtual defect generation unit 4 includes an electrical inspection data acquisition unit 11 that acquires electrical inspection data from the electrical inspection database 10, a chip placement map acquisition unit 12 that acquires a chip placement map from the chip placement map database 8, and an electrical inspection. A coordinate setting unit 13 that sets the position coordinates of the virtual defect corresponding to the defective chip from the data and the chip arrangement map, a feature amount conversion unit 16 that converts the defect category of the defective chip into a virtual feature amount of the virtual defect, and the virtual The distribution feature analysis unit 3 includes a determination threshold value changing unit 17 that changes a determination threshold value for extracting the characteristic distribution of the virtual defect based on the feature amount.

  The coordinate setting unit 13 includes a coordinate calculation unit 15 that calculates the position coordinates of the virtual defect corresponding to the defective chip from the electrical inspection data and the chip arrangement map, and sets the calculated position coordinates. In addition, the coordinate setting unit 13 includes a pitch correction unit 14 that corrects a plurality of chips to a pitch different from the pitch at which the chips are arranged on the wafer, and sets position coordinates for the virtual defect with the corrected pitch.

  The distribution feature analysis unit 3, the virtual defect generation unit 4, and the failure cause analysis unit 5 are programs that can execute the distribution feature analysis method, the virtual defect generation method, and the failure cause analysis method, respectively. This can be realized by executing. The distribution feature analysis unit 3, the virtual defect generation unit 4, and the failure cause analysis unit 5 may be realized on a single computer, or may be distributed to a plurality of computers connected by the network 18. .

  Next, a distribution feature analysis method based on electrical inspection data by the distribution feature analyzer 2 will be described using the flowchart shown in FIG. First, in step S <b> 1, the electrical test data acquisition unit 11 acquires electrical test data from the electrical test database 10.

  In step S2, the virtual defect generation unit 4 generates a virtual defect. Information on the arrangement of defective chips is converted into position coordinates of virtual defects. Further, the defect category of the defective chip is converted into a virtual defect feature amount. Details of this point will be described later.

  In step S3, the distribution feature analysis unit 3 performs a distribution feature analysis from a distribution based on the position coordinates of the virtual defect. Specifically, the determination threshold is changed based on the feature amount, and it is determined whether the virtual defect distribution belongs to the characteristic distribution based on the changed determination threshold. If it is determined that the virtual defect distribution belongs to the characteristic distribution, the original wafer is regarded as an abnormal wafer in which an abnormal distribution of defective chips exists. Details of this point will also be described later.

  In step S4, the distribution feature analysis unit 3 determines whether or not there is an abnormal distribution. If there is no abnormal distribution, the process proceeds to step S6, and if there is an abnormal distribution, the process proceeds to step S5.

  In step S5, the failure cause analysis unit 5 displays the abnormal distribution on the display, prompts the person in charge to grasp the status of the abnormal distribution, and analyzes the cause of the defective chip from the original wafer manufacturing history and the like.

  In step S6, the electrical inspection data server 7 stores the analysis result by the distribution feature analysis unit 3 and the analysis result by the failure cause analysis unit 5 if present. Thus, the distribution feature analysis method based on the electrical inspection data by the distribution feature analysis apparatus 2 is completed.

  Next, the virtual defect generation method in step S2 of FIG. 2 will be described in detail. First, as shown in FIG. 3, in step S <b> 11, the chip arrangement map acquisition unit 12 extracts the chip arrangement map identifier from the electrical inspection data (electric inspection data) for each wafer stored in the electric inspection database 10. (See FIG. 5 (a) below).

  In step S12, the chip arrangement map acquisition unit 12 acquires a chip arrangement map from the chip arrangement map database 8 based on the identifier of the chip arrangement map. As the chip arrangement map, the column pitch in the column direction of the chip arrangement, the row pitch in the row direction, the X-axis and Y-axis position coordinates of the reference point of the reference chip serving as a reference for arrangement, and the column in which the reference chip is arranged Numbers and line numbers are increased.

  In step S13, the pitch correction unit 14 sets the fixed column pitch and the fixed row pitch according to the threshold value of the adjacent defect distance for determining whether adjacent defects in the distribution feature analysis unit 3 are dense or not. The column pitch and the row pitch acquired from the chip arrangement map database 8 are corrected.

In step S14, the coordinate calculation unit 15 calculates the position coordinates of the virtual defect for each defective chip. The X coordinate is calculated by the following equation.
(X coordinate) = (X coordinate of the reference point of the reference chip) + ((defective chip column number) − (reference chip column number)) × (column pitch) + (imaginary when the reference chip is a defective chip) (X-axis distance between defect and reference point)

Similarly, the Y coordinate is calculated by the following equation.
(Y coordinate) = (Y coordinate of the reference point of the reference chip) + ((defective chip row number) − (reference chip row number)) × (row pitch) + (imaginary when the reference chip is a defective chip) (Y-axis distance between the defect and the reference point)

  In step S15, the electrical inspection database 10 stores the position coordinates of the virtual defect corresponding to each defective chip.

  In step S <b> 16, the feature amount conversion unit 16 converts, for each defective chip, from the characteristic value, for example, the defect category of the defective chip, to the feature amount of the virtual defect, for example, the defect area of the virtual defect, based on the characteristic value conversion database 9. Convert.

  In step S <b> 17, the electrical inspection database 10 stores the feature amount of the virtual defect in association with each defective chip. This completes the virtual defect generation method in step S2 of FIG.

  Next, the distribution feature analysis method by the distribution feature analysis unit 3 in step S3 of FIG. 2 will be described in detail. First, as shown in FIG. 4, in step S <b> 21, a superimposition map is created by dividing the virtual defect distribution into regions of repetitive units that are considered to generate repetitive distribution features. As the repeating unit, a stepping repeating unit by a stepper at the time of exposure can be considered.

  In step S22, the adjacent defect distance is calculated using the nearest point Voronoi diagram from the overlay map.

  Prior to step S23, the determination threshold value changing unit 17 changes the determination threshold value for extracting the characteristic distribution of the virtual defect. In step S23, it is determined whether the distribution of virtual defects belongs to the repeated distribution feature from the magnitude relationship between the calculated adjacent defect distance and the changed determination threshold. If it is determined that the virtual defect distribution belongs to the repeated distribution feature, the process proceeds to step S24, and the repeated distribution feature is extracted from the virtual defect distribution. By this extraction, this wafer is an abnormal wafer having an abnormal distribution. If it is determined that the virtual defect distribution does not belong to the repeated distribution feature, the process proceeds to step S25.

  In step S25, the adjacent defect distance and the Voronoi area are calculated for each wafer based on the position coordinates (distribution) of the virtual defect using the nearest point Voronoi diagram.

  Prior to step S26, the determination threshold value changing unit 17 changes the determination threshold value for extracting the characteristic distribution of the virtual defect. In step S26, it is determined whether the distribution of virtual defects belongs to the dense distribution feature from the magnitude relationship between the calculated adjacent defect distance and the changed determination threshold. If it is determined that the virtual defect distribution belongs to the dense distribution feature, the process proceeds to step S27, and the dense distribution feature is extracted from the virtual defect distribution. By this extraction, this wafer is an abnormal wafer having an abnormal distribution. If it is determined that the virtual defect distribution does not belong to the dense distribution feature, the process proceeds to step S28.

  Prior to step S28, the determination threshold value changing unit 17 changes the determination threshold value for extracting the characteristic distribution of virtual defects. Then, in step S28, it is determined whether or not the virtual defect distribution belongs to the linear distribution feature from the magnitude relationship between the calculated adjacent defect distance and Voronoi region area and the changed determination threshold. If it is determined that the virtual defect distribution belongs to the linear distribution feature, the process proceeds to step S29, and the linear distribution feature is extracted from the virtual defect distribution. By this extraction, this wafer is an abnormal wafer having an abnormal distribution. If it is determined that the virtual defect distribution does not belong to the linear distribution feature, the process proceeds to step S30.

  Prior to step S30, the determination threshold value changing unit 17 changes the determination threshold value for extracting the characteristic distribution of the virtual defect. In step S30, it is determined whether or not the virtual defect distribution belongs to the ring / bulk distribution feature from the magnitude relationship between the calculated adjacent defect distance and Voronoi region area and the changed determination threshold. If it is determined that the virtual defect distribution belongs to the ring / bulk distribution feature, the process proceeds to step S31, and the ring / bulk distribution feature is extracted from the virtual defect distribution. By this extraction, this wafer is an abnormal wafer having an abnormal distribution. If it is determined that the virtual defect distribution does not belong to the ring / lump distribution feature, the process proceeds to step S32.

  In step S32, wafers that do not correspond to any of the repeated distribution feature, the dense distribution feature, the linear distribution feature, and the ring / lump distribution feature are classified as random distribution features, and this wafer is a wafer having no abnormal distribution. Become. The distribution feature analysis method by the distribution feature analysis unit 3 in step S3 in FIG.

(Specific example 1)
In Specific Example 1, a distribution feature analysis method based on electrical inspection data using the distribution feature analysis apparatus 2 of FIG. 1 will be specifically described.

  As shown in FIG. 5A, the electrical inspection database 10 identifies, as electrical inspection data, a wafer identifier A that can be extracted from a wafer corresponding to each wafer and a chip arrangement map of chips on the wafer for each wafer. And a possible chip placement map identifier B. As a result, the chip arrangement map identifier B can be extracted from the wafer identifier A for each wafer.

  In addition, as shown in FIG. 5B, the electrical test database 10 includes, as shown in FIG. 5B, for each of the defective chips C1 to C10, row numbers L1 and column numbers R4, which are array information on the wafer, The defect category 1 is stored. The defective chips C1 to C10 are classified and stored in several categories according to the result of the electrical inspection, respectively, but in specific example 1, all the defective chips C1 to C10 are the same category 1 for easy understanding. It is said. A category map as shown in FIG. 6 can be created from these electrical inspection data. In the category map, chips 32 are arranged in the wafer 31. The defective chips C1 to C10 in the chip 32 are indicated by “1” in category 1, and the non-defective chips are indicated by blanks. Non-defective chips may also be represented by a predetermined category. The category of defective chips may be expressed by letters, symbols, etc. in addition to numbers.

  Electrical inspection data as shown in FIGS. 5A and 5B is acquired from the electrical inspection database 10 in step S1 of FIG. Next, a virtual defect is generated in step S2. Specifically, the chip arrangement map identifier B in FIG. 5A is extracted from the electrical inspection data of the wafer 31 in step S11 in FIG.

  In step S12, a chip arrangement map is acquired from the chip arrangement map database 8 based on the chip arrangement map identifier B. As shown in FIGS. 7 and 8, in the chip arrangement map, for each chip arrangement map identifier B, the column pitch PR in the column direction of the chip arrangement, the row pitch PL in the row direction, and the reference chip 35 are arranged. The column number R6 and the row number L4, and the position coordinates x0 and y0 on the plane of the X axis 33 and the Y axis 34 of the reference point 36 of the reference chip 35 which is the reference for arrangement are raised. Step S13 is omitted for easy understanding. The origin O is a coordinate origin composed of the X axis 33 and the Y axis 34.

In step S14, the position coordinates X and Y coordinates of the virtual defect in FIG. 9B are calculated for each of the defective chips C1 to C10. For example, the X coordinate x1 of the defective chip C1 is calculated by the following equation. Note that the interval in the X-axis direction between the virtual defect and the reference point 36 when the reference chip 35 is a defective chip is half of the column pitch PR.
x1 = x0 + (R4-R6) × PR + PR / 2

Similarly, the Y coordinate y1 is calculated by the following equation. Note that the interval in the Y-axis direction between the virtual defect and the reference point 36 when the reference chip 35 is a defective chip is half the row pitch PL.
y1 = y0 + (L1-L4) × PL + PL / 2

  In step S15, the X coordinate x1 to x10 and the Y coordinate y1 to y10 which are the position coordinates of the virtual defect corresponding to the respective defective chips C1 to C10 are stored in the electric inspection database 10 shown in FIGS. 9A and 9B. Remember. By storing the X coordinates x1 to x10 and the Y coordinates y1 to y10, virtual defects d1 to d10 are generated as shown in FIG. In specific example 1, one virtual defect d1 to d10 is arranged at the center of the defective chips C1 to C10. However, the present invention is not limited to this, and a plurality of virtual defects may be arranged for one defective chip. Alternatively, it may be arranged at a specific position inside and outside the defective chip. Specifically, the virtual defect may be set not at the center of the defective chip but at any position such as the lower left or upper right of the defective chip, and may be set at a unified position in the wafer 31 for each defective chip.

  In this way, by generating the virtual defect position coordinates and using the virtual defect position coordinates instead of the pattern defect position coordinates, the distribution feature analysis using the normal pattern defect position coordinates can be performed. The present invention can be applied to distribution feature analysis using coordinates, which means that distribution feature analysis of defective chips has become possible. The characteristic distribution of the defective chips C1 to C10 can be extracted from the determination result of the electrical inspection by a method similar to the method for extracting the characteristic distribution of pattern defects.

(Specific example 2)
In the second specific example, the distribution feature based on the electrical inspection data using the distribution feature analyzing apparatus 2 in FIG. 1 is used in the case of correcting the column pitch and the row pitch in step S13 in FIG. The analysis method will be described. In order to simplify the description, the electrical inspection data is the same as the electrical inspection data of the specific example 1 shown in FIGS. 5 (a) and 5 (b) and FIG. Similarly to the first specific example, step S1 in FIG. 2 and steps S11 and S12 in FIG. 3 are executed to obtain a chip arrangement map as shown in FIGS. At this time, as shown in FIG. 7, the column pitch PR and the row pitch PL are acquired.

  Next, as shown in FIG. 11, in step S13, a fixed row pitch PR0 having a fixed value corresponding to the threshold value of the adjacent defect distance for determining whether or not adjacent defects in the distribution feature analysis unit 3 are dense. The column pitch PR and the row pitch PL are corrected to a fixed row pitch PL0 having a fixed value. As shown in FIG. 12, as the chip arrangement map, a chip arrangement map arranged in the column direction at the column pitch PR0 and arranged in the row direction at the row pitch PL0 can be obtained. Also in the chip arrangement map of FIG. 12, as in the chip arrangement map of FIG. 8, the reference chip 35 is arranged at the row number L4 of the column number R6, and the reference point 36 of the reference chip 35 is set to the position coordinates x0 and y0. ing.

In step S14, the position coordinates X and Y coordinates of the virtual defects d1 to d10 are calculated for each of the defective chips C1 to C10. For example, the X coordinate x1 of the defective chip C1 is calculated by the following equation.
x1 = x0 + (R4-R6) × PR0 + PR0 / 2

Similarly, the Y coordinate y1 is calculated by the following equation.
y1 = y0 + (L1-L4) × PL0 + PL0 / 2

  Hereinafter, similarly to the first specific example, by performing step S15, the X coordinate x1 to x10 and the Y coordinate y1 which are the position coordinates of the virtual defect corresponding to the respective defective chips C1 to C10 are stored in the electrical inspection database 10. Through y10 are stored, and virtual defects d1 through d10 are generated as shown in FIG.

  Thus, the column pitch and the row pitch, so-called chip size, are set to values different from the actual chip size. Since the chip size is different for each semiconductor device mounted on the chip, when the column pitch and row pitch of the chip size are used as they are, the adjacent defect distance of the virtual defect varies depending on the chip size. Since the distribution feature analysis is performed using the adjacent defect distance, the characteristic distribution may or may not be extracted depending on the chip size. Therefore, in the second specific example, the chip size is changed to the fixed column pitch PR0 and the row pitch PL0 corresponding to the adjacent defect distance in the pattern feature distribution feature analysis, regardless of the actual column pitch PR and the row pitch PL. Regardless, the distribution feature analysis of the defective chip can be performed with the same analysis parameters as the distribution feature analysis of the pattern defect. The characteristic distribution of the defective chips C1 to C10 can be extracted from the determination result of the electrical inspection by a method similar to the method for extracting the characteristic distribution of pattern defects.

(Specific example 3)
In specific example 3, the feature amount of the virtual defect will be described by taking as an example a case where a plurality of defective chip defect categories exist in one wafer. The electrical inspection data is usually given a category according to the inspection result. Also, in the third specific example, as in the first specific example, a distribution feature analyzing method based on electrical inspection data using the distribution feature analyzing apparatus 2 in FIG. 1 will be described. In order to simplify the explanation, the electrical inspection data is the electrical data of the specific example 1 shown in FIGS. 5 (a), 5 (b) and 6 as shown in FIGS. Inspection data, wafer identifier, chip arrangement map identifier, row number and column number are the same. The defect category of the defective chip was stored in the electric test database 10 as shown in FIG. 13B and FIG. Further, similarly to the specific example 1, step S1 in FIG. 2 and steps S11 to S15 in FIG. 3 are executed, and as shown in FIG. Correspondingly, the X coordinates x1 to x10 and the Y coordinates y1 to y10 which are the position coordinates of the virtual defects d1 to d10 are stored, and the virtual defects d1 to d10 are generated as shown in FIG.

  As shown in FIG. 16, the characteristic value conversion database 9 of FIG. 1 associates one characteristic value of a defective chip, for example, one feature amount of a virtual defect, for example, a defect area, in association with one another, so that it can be extracted. The category of the characteristic value and the defect area of the feature amount are stored. Usually, the larger the defect area of the pattern defect, the more serious damage is caused to the chip. Therefore, a small defect area is assigned to the category of minor defects for the chip so that the user can handle the defect as well. The category is assigned a larger defect area than the minor defect category. As the feature amount, in addition to the defect area, the defect size and the number of virtual defects in the chip can also be used.

  In step S16 of FIG. 3, the defect area is extracted from the category based on the characteristic value conversion database 9 for each of the defective chips C1 to C10. In step S17, the electrical inspection database 10 stores the defect areas of the virtual defects d1 to d10 corresponding to the respective defective chips C1 to C10.

  Next, in step S3 of FIG. 2, a distribution feature analysis is performed from a distribution based on the position coordinates (X coordinates x1 to x10, Y coordinates y1 to y10) of the virtual defects d1 to d10. Characteristic distributions F1 and F2 belonging to the dense distribution feature were extracted by the distribution feature analysis. As shown in FIG. 18, in extracting the characteristic distribution F1, in determining whether the characteristic distribution F1 is a dense distribution feature, the total defect area is 7. Since it is small, it is difficult to determine that the characteristic distribution F1 is a dense distribution feature by raising the determination threshold. This is because it is considered that there are few defective chips having a fatal failure cause in the characteristic distribution F1.

  On the other hand, when extracting the characteristic distribution F2, in determining whether the characteristic distribution F2 is a dense distribution feature, the total defect area is as large as 9.0 although the number of defects is as small as two. The threshold value is lowered to make it easier to determine that the characteristic distribution F2 is a dense distribution feature. In this way, a fine determination threshold can be set by using the total number of defects and the defect area. A fatal defect can be preferentially extracted. When it is determined that the characteristic distributions F1 and F2 are dense distribution characteristics, the wafer 31 is regarded as an abnormal wafer having an abnormal distribution. In step S4, it is determined whether or not there is an abnormal distribution. Since the wafer 31 has an abnormal distribution, the process proceeds to step S5.

  In step S5, the cause of failure of the defective chip is analyzed from the manufacturing history of the wafer 31 and the like. Since two characteristic distributions F1 and F2 are extracted from the wafer 31, priority is set as to which of the characteristic distributions F1 and F2 the cause of failure of the defective chip is analyzed first. The priority order is set by the feature amount comparison unit 19 of FIG. As shown in FIG. 18, in the characteristic distribution F1, the total sum of the defect areas is as small as 7.2 even though the number of defects is as large as 4, so the priority is set low and the characteristic distribution F1. Although F2 has a small number of defects as small as two, the total sum of defect areas is as large as 9.0, so the priority is set high and ranked first. The cause of failure of the defective chips belonging to each of the characteristic distributions F2 to F1 is analyzed. By determining the priority order in this way, it is possible to start the analysis of the cause of failure from the characteristic distribution that is considered to include more defective chips having a cause of fatal failure, and to elucidate the cause of fatal failure early can do.

1 is a configuration diagram of a distribution feature analysis system including a distribution feature analysis device according to an embodiment of the present invention. It is a flowchart of the distribution feature analysis method which concerns on embodiment of this invention. It is a flowchart of the virtual defect generation in the distribution feature analysis method according to the embodiment of the present invention. It is a flowchart of the distribution feature extraction method in the distribution feature analysis method according to the embodiment of the present invention. (A) is a configuration table (No. 1) of the electropsy database of Example 1, and (b) is a configuration table (No. 2) of the electropsy database of Example 1. It is a category map of the electroanalysis data of the specific example 1. 10 is a configuration table of a chip arrangement map database of specific example 1; It is a top view (chip arrangement map) of a wafer in which chips are arranged. (A) is a configuration table (No. 1) of an electropsy database after calculating position coordinates, and (b) is a configuration table (No. 2) of an electropsy database after calculating position coordinates. It is a distribution map on the wafer of the virtual defect of the specific example 1. 12 is a configuration table of a chip arrangement map database after column pitch and row pitch correction of specific example 2; It is a distribution map on the wafer of the virtual defect after the column pitch of Example 2 and a row pitch correction | amendment. (A) is a configuration table (No. 1) of an electropsy database according to Example 3 of the present invention, and (b) is a configuration table (No. 2) of an electropsy database according to Example 3. It is a category map of the electroanalysis data of the specific example 3. (A) is a configuration table (No. 1) of an electrosurgical database after the position coordinates are calculated and the category characteristic values are converted into defect areas. It is the structure table | surface (the 2) of the electric test | inspection database after converting into. 10 is a configuration table of a characteristic value conversion database of Example 3. It is a distribution map on the wafer of the virtual defect of specific example 3, and characteristic distribution. FIG. 11 is a table showing determination of priorities of a plurality of characteristic distributions for analyzing a cause of occurrence of a defective chip by raising and lowering a determination threshold when classifying characteristic distributions using the defect density of specific example 3. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Distribution feature analysis system 2 Distribution feature analysis apparatus 3 Distribution feature analysis part 4 Virtual defect generation part 5 Defect cause analysis part 6 Pattern defect data server 7 Electrical inspection data server 8 Chip arrangement map database 9 Characteristic value conversion database 10 Electropsy database DESCRIPTION OF SYMBOLS 11 Electrographic test data acquisition part 12 Chip arrangement | positioning map acquisition part 13 Coordinate setting part 14 Pitch correction part 15 Coordinate calculation part 16 Feature-value conversion part 17 Determination threshold value change part 18 Network 21, 22 Pattern defect inspection apparatus 23, 24, 25, 26 Electrical inspection device 31 Wafer 32 Chip 35 Reference chip 36 Reference point C1 to C10 Defective chip d1 to d10 Virtual defect

Claims (6)

Defect distribution for extracting a characteristic distribution from the distribution of the actual defects based on the position coordinates of the plurality of actual defects on the wafer obtained by inspecting the wafer during the production of a plurality of chips on the wafer In the feature analysis method,
Analysis device
Generating a plurality of virtual defects arranged at the position coordinates converted based on the arrangement information on the wafer of a plurality of defective chips determined by electrical inspection of the chip after the chip is manufactured;
A defect distribution feature analysis method, wherein the characteristic distribution is extracted from the virtual defect distribution based on the position coordinates of the virtual defect. In the process of generating the virtual defect,
The defect distribution feature analysis method according to claim 1, wherein the position coordinates are set at a pitch different from a pitch at which the plurality of chips are arranged. Converting the defect category of the defective chip into a virtual feature amount of the virtual defect;
3. The defect distribution according to claim 1, wherein when extracting the characteristic distribution of the virtual defect based on the virtual feature amount, a determination threshold value for extraction is changed. Feature analysis method. Defect distribution for extracting a characteristic distribution from the distribution of the actual defects based on the position coordinates of the plurality of actual defects on the wafer obtained by inspecting the wafer during the production of a plurality of chips on the wafer In the feature analyzer,
A virtual defect that generates a plurality of virtual defects arranged at the position coordinates converted based on arrangement information on the wafer of a plurality of defective chips determined by electrical inspection of the chip after the chip is manufactured Having a generator,
A defect distribution feature analysis apparatus, wherein the characteristic distribution is extracted from the virtual defect distribution based on the position coordinates of the virtual defect.   The defect distribution feature analysis apparatus according to claim 4, wherein the virtual defect generation unit includes a coordinate setting unit that sets the position coordinates at a pitch different from a pitch in which the plurality of chips are arranged. A feature amount conversion unit that converts a defect category of the defective chip into a virtual feature amount of the virtual defect;
5. A determination threshold value changing unit that changes a determination threshold value for extraction when extracting the characteristic distribution of the virtual defect based on the virtual feature value. 5. The defect distribution feature analysis apparatus according to 5.

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