JP2007324165A - Surface treatment method of silicon substrate and fabrication process of solar cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a surface treatment process of a silicon substrate in which a low reflection surface suitable for solar cell can be achieved while preventing a porous layer from occurring due to etching in a silicon substrate. <P>SOLUTION: A silicon substrate is placed in an evacuated reactor vessel and the surface of the silicon substrate is etched by supplying etching gas containing ClF<SB>3</SB>. Before unacted ClF<SB>3</SB>intrudes into the silicon substrate, etching gas supply is stopped and purge gas is supplied in order to desorb/remove unacted ClF<SB>3</SB>from the surface of the silicon substrate. These steps are repeated a plurality of times. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a silicon substrate surface treatment method and a solar cell manufacturing method, in which fine irregularities are formed on the surface of a substrate for use in a solar cell.

  In order to increase the photoelectric conversion efficiency, so-called crystalline solar cells using a single crystal or polycrystalline silicon (Si) substrate have innumerable fine irregularities formed on the surface of the silicon substrate, and the light reflectance of the silicon substrate surface is reduced. We are trying to reduce it. For this reason, in the conventional manufacturing process of solar cells, a method of wet etching a single crystal or polycrystalline silicon substrate in an alkaline aqueous solution to form pyramidal irregularities on the silicon substrate surface has been widely used.

  However, in the above-described wet etching, since the etching rate of Si strongly depends on the crystal plane orientation, when polycrystalline silicon is used as the substrate, uniform unevenness cannot be formed on the entire surface of the substrate. There has been a problem that the light reflectance on the surface of the silicon substrate is reduced only to about 30%.

As a method for solving this problem, a method of forming fine irregularities on the surface by etching a silicon substrate using chlorine trifluoride (ClF ₃ ) gas has been proposed (for example, Non-Patent Documents 1 and 2). , See Patent Documents 1 and 2).

Specifically, a silicon substrate is placed in a quartz or stainless steel reaction vessel that has been evacuated, and ClF ₃ gas diluted with, for example, argon (Ar) or nitrogen (N ₂ ) gas is introduced into the reaction vessel. At this time, the exhaust system connected to the reaction vessel is equipped with a pressure adjusting exhaust valve and a vacuum pump, and the gas pressure in the reaction vessel is kept constant by adjusting the opening of the exhaust valve. The silicon substrate surface can be exposed to a ClF ₃ gas atmosphere for a predetermined time. The gas pressure disclosed in the above literature is in the range of 0.1 to 100 Torr, and the treatment time is in the range of 10 to 30 minutes.

When the silicon substrate is exposed to a ClF ₃ gas atmosphere, the reaction of 3Si + 4ClF ₃ → 3SiF ₄ ↑ + 2Cl ₂ ↑ occurs due to the chemical action of ClF ₃ adsorbed on the silicon substrate surface, and the Si atoms of the silicon substrate are volatile SiF ₄ molecules. When this is detached from the surface of the silicon substrate, etching of Si proceeds.

Further, as shown in Non-Patent Document 2, when a natural oxide film is present on the surface of the silicon substrate to be subjected to the above-described treatment, the film thickness and film quality of the natural oxide film are not uniform. The reaction proceeds non-uniformly even in a minute region on the substrate surface. Thus, after etching using ClF ₃ gas, innumerable irregularities are formed on the surface of the silicon substrate taken out to the atmosphere, and the dimension of the irregularities is approximately several tens nm to several hundreds nm depending on processing conditions. It is known that its tip is relatively sharp. The surface of the silicon substrate on which the unevenness is formed by the ClF ₃ gas etching described above can reduce the light reflectance to about 10%, and is desirable as the light receiving surface of the solar battery cell.

  However, when a solar cell is produced using a silicon substrate with irregularities formed by the above-described treatment, the irregularities on the surface of the silicon substrate are sharp when the silver electrode is formed and fired on the light receiving surface side. It has been pointed out that the pn junction is electrically degraded and destroyed.

Further, in ClF ₃ gas etching, fluorine (F) and chlorine (Cl) atoms are generated by dissociative adsorption of ClF _{3 on} the silicon surface, and these F and Cl atoms, particularly F atoms having a relatively small atomic radius are contained in Si. Therefore, the etching reaction proceeds even inside the silicon substrate. Thus, a so-called porous layer (pore diameter: several tens of nanometers to several hundreds of nanometers, depth: several tens of nanometers to several hundreds of nanometers) in which innumerable fine pores exist in the vicinity of the silicon substrate surface is formed. The thickness of the porous layer also increases.

  When such a porous layer is present on the light receiving surface, carriers generated by receiving light are recombined inside the porous layer, and in the cell characteristics of the produced solar cell, an open circuit voltage, a short circuit current, There is a problem that the fill factor and conversion efficiency are lowered and the cell characteristics are deteriorated.

As a means for solving the above problems, after performing ClF ₃ gas etching, the silicon substrate is subjected to alkaline aqueous solution, for example, sodium hydroxide (NaOH) or potassium hydroxide (KOH) aqueous solution, or a mixed acid composed of hydrofluoric acid and nitric acid ( There has been proposed a method of performing wet etching using HF / HNO ₃ / H ₂ O), smoothing the tips of the uneven portions formed on the surface, and removing the porous layer (for example, Patent Document 1 or 2).

And it is shown that a favorable uneven | corrugated shape can be formed by optimizing the composition ratio of an etching liquid, a dilution rate, temperature, processing time. Actually, a solar cell was produced using a silicon substrate surface-treated by such a method, and the cell characteristics were measured and evaluated. As a result, compared with the case of only ClF ₃ gas etching, the leakage current was reduced, the open-circuit voltage, It has been reported that the short circuit current, the fill factor, and the conversion efficiency all increase and the cell characteristics are improved.

Tadashi Kadoma, Yoshinobu Ishizaki, Yoji Saito "Texturing and optical evaluation of silicon using chlorine trifluoride" IEICE Transactions C-11 vol. J80-C-11, No. 11, pp. 412-413 (1997) S. Saitou, O .; Yamaoka, A .; Yoshida “Plasmaless Cleaning Process of Silicon Surface Using Chlorine Trifluoride” Appl. Phys. Lett. , Vol. 56, pp. 1119-1121 (1990). JP 2000-101111 A JP 2005-150614 A

  However, the silicon substrate subjected to these wet etchings has a problem that the light reflectance increases as the surface irregularities are etched. That is, maintaining low reflection on the surface of the silicon substrate, smoothing irregularities on the surface of the substrate, and removing the porous layer are mutually contradictory, and it is extremely difficult to realize both. . Further, in combination with wet etching, a large amount of acid / alkaline chemical solution is used and discarded, which is not preferable because it causes not only an increase in cost but also an increase in environmental load.

  The present invention has been made in view of the above problems, and is a silicon substrate capable of realizing a low-reflectance surface suitable for solar cells while preventing the generation of a porous layer caused by etching inside the silicon substrate. A surface treatment method and a solar cell manufacturing method are provided.

The surface treatment method for a silicon substrate according to claim 1 includes: (a) a step of placing the silicon substrate in a evacuated reaction vessel; and (b) supplying an etching gas containing ClF ₃ into the reaction vessel. Etching the silicon substrate surface to form irregularities; and (c) supplying a purge gas into the reaction vessel to remove unreacted etching gas components adsorbed on the silicon substrate surface. A step, wherein the step (b) and the step (c) are alternately repeated.

  According to a fifth aspect of the present invention, there is provided a method for producing a solar battery cell, wherein the method for treating a surface of a silicon substrate according to any one of the first to fourth aspects is performed.

According to the silicon substrate surface treatment method according to claim 1 and the solar cell manufacturing method according to claim 5, after forming fine irregularities on the silicon substrate surface using an etching gas containing ClF ₃ , silicon Since the component of the unreacted etching gas adsorbed on the substrate surface is removed, it is possible to realize a surface with low reflectance suitable for solar cells while preventing the generation of a porous layer caused by etching inside the silicon substrate.

<Embodiment 1>
<A. Configuration>
FIG. 1 is a diagram schematically showing a configuration of a surface treatment apparatus for a silicon substrate according to the first embodiment. As shown in FIG. 1, the surface treatment apparatus for a silicon substrate according to the first embodiment accommodates a silicon substrate 2, and a reaction vessel 1 made of quartz, aluminum, or stainless steel for performing a predetermined treatment on the surface. have.

A substrate stage 3 for holding the silicon substrate 2 is provided in the reaction vessel 1. The reaction vessel 1 is supplied with an etching gas supply tube 4 for supplying ClF ₃ gas (etching gas) diluted with Ar, a purge gas supply tube 5 for supplying N ₂ gas (purge gas), and the gas in the reaction vessel 1. A gas exhaust pipe 6 for exhaust is connected.

  The etching gas supply pipe 4 is provided with a gas supply valve 7 for turning on / off the supply of the etching gas. The purge gas supply pipe 5 is provided with a gas supply valve 8 for turning on / off the supply of the purge gas. Further, the gas exhaust pipe 6 is provided with a gas exhaust valve 9 for turning on / off the gas exhaust. A control unit 10 for driving and controlling the gas supply valves 7 and 8 and the gas exhaust valve 9 is provided.

  Note that the silicon substrate 2 includes not only a substrate made of only polycrystalline or single crystal silicon but also a silicon substrate formed on a glass substrate, for example.

<B. Treatment method of silicon substrate surface>
<B-1. Treatment method of silicon substrate surface>
Next, an example of a method for treating the surface of a silicon substrate using the surface treatment apparatus according to the first embodiment will be described with reference to FIG. FIG. 2 is a view for explaining the processing method of the surface treatment apparatus according to the first embodiment. Here, FIG. 2 shows an etching gas flow rate that is the flow rate of the etching gas supplied to the reaction vessel 1 with respect to the processing time, a purge gas flow rate that is the flow rate of the purge gas supplied to the reaction vessel 1, and gas is exhausted from the reaction vessel 1. The evacuation speed and the gas pressure in the reaction vessel 1 are shown.

  First, the silicon substrate 2 to be surface-treated is placed on the substrate stage 3 in the reaction vessel 1 evacuated through the gas exhaust pipe 6. Here, from the start of the process to the completion, the gas exhaust valve 9 is in an ON state and exhausts the reaction vessel 1 at a constant exhaust speed.

Next, in the process of time T ₁ <t <T ₂ , by supplying an etching gas containing ClF ₃ into the reaction vessel 1, the silicon substrate surface is etched to form irregularities. Specifically, first, with the gas exhaust valve 9 turned on, the gas supply valve 7 provided in the etching gas supply pipe 4 is turned on, and the ClF ₃ gas diluted with Ar is placed in the reaction vessel 1. (That is, ClF ₃ / Ar mixed gas) is supplied. At this time, the gas pressure in the reaction vessel 1 increases due to the introduction of the etching gas. Hereinafter, this process may be referred to as an “etching gas supply process”.

In this etching gas supply step, etching of the silicon substrate surface occurs due to ClF ₃ incident on and attached to the surface of the silicon substrate 2, and irregularities start to be formed on the surface of the silicon substrate. At this time, if the gas supply time (T ₂ -T ₁ ) is set sufficiently short, ClF ₃ adsorbed on the silicon substrate surface (F, Cl, etc. in addition to this does not enter the silicon substrate 2). The formation of the porous layer can be prevented from starting.

Next, in the process of time T ₃ <t <T ₄ , purge gas is supplied into the reaction vessel 1 to remove unreacted etching gas components adsorbed on the silicon substrate surface. Specifically, the gas supply valve 8 provided in the purge gas supply pipe 5 is turned on to supply N ₂ gas into the reaction vessel 1. At this time, the gas pressure in the reaction vessel 1 increases due to the introduction of the purge gas. Hereinafter, this process may be referred to as a “purge gas supply process”.

In this purge gas supply step, a large number of N ₂ molecules are incident on the surface of the silicon substrate 2 to remove unreacted ClF ₃ (F, Cl, etc.) adsorbed on the surface of the silicon substrate 2. Separation is promoted and removed promptly. Thus, the etching of the silicon substrate 2 (that is, the formation of surface irregularities and the porous layer) can be almost completely stopped by the purge gas supply process.

Next, in the process of time T ₅ <t <T ₆ , the ClF ₃ / Ar mixed gas which is an etching gas is again supplied into the container. Then, adsorption of ClF ₃ to the surface of the silicon substrate 2 occurs again, and etching of the silicon substrate surface resumes. Therefore, the uneven shape on the surface of the silicon substrate becomes larger.

Next, in the process of time T ₇ <t <T ₈ , N ₂ gas is supplied into the reaction vessel 1. Then, ClF ₃ (in addition to this, F, Cl, etc.) adhering to the surface of the silicon substrate is removed before entering the inside of the silicon substrate 2. As a result, no porous layer is formed due to the residue of ClF ₃ or the like on the surface of the silicon substrate. Thereafter, an etching gas supply process is performed at time T ₉ <t <T ₁₀ , and a purge gas supply process is performed at time T ₁₁ <t <T ₁₂ .

  As described above, the etching gas supply process and the purge gas supply process are alternately repeated a plurality of times, and while the formation of the porous layer is suppressed, the unevenness on the surface of the silicon substrate 2 is selectively grown to finish the process.

<B-2. Setting of etching gas supply time>
Next, for example, in order to appropriately set the etching gas supply time corresponding to the time T ₂ -T ₁ in FIG. 2, an experimental result of examining the etching gas supply time and the formation of the porous layer will be described.

In this experiment, a p-type semiconductor polycrystalline silicon substrate 2 (150 mm square) is used, the ClF ₃ gas flow rate is set to 10 sccm, the dilution Ar gas flow rate is set to 490 sccm, and the ClF ₃ / Ar mixed gas in the reaction vessel 1 is set. The exhaust speed was adjusted so that the total pressure of the gas was 10 Torr. Then, the etching gas supply was turned off and the silicon substrate 2 was taken out to the atmosphere after a predetermined time from the start of the supply of the etching gas comprising the ClF ₃ / Ar mixed gas. Note that the temperature of the silicon substrate 2 being processed is room temperature.

  FIG. 3 is a diagram showing the thickness (nm) of the porous layer formed on the silicon substrate surface with respect to the etching gas supply time (seconds). As shown in FIG. 3, if the etching gas supply time is within 30 seconds, the porous layer is hardly formed on the silicon substrate surface. However, it was found that the porous layer started to form after 30 seconds and the thickness of the porous layer increased almost linearly as the gas supply time increased. From FIG. 3, it was found that it is appropriate to set the etching gas supply time to 30 seconds or less.

<B-3. Specific processing conditions>
Next, specific processing conditions of the silicon substrate surface processing method according to the first embodiment will be described. In the etching gas supply step, the processing conditions were set to ClF ₃ gas flow rate: 10 sccm, Ar gas flow rate: 490 sccm, ClF ₃ / Ar gas pressure: 10 Torr, etching gas supply time: 15 seconds. In the purge gas supply step, the processing conditions were set to N ₂ gas flow rate: 5000 sccm, N ₂ gas pressure: 10 Torr, and purge gas supply time: 30 seconds.

  After the etching gas supply process and the purge gas supply process were alternately repeated 20 times under the above processing conditions, the silicon substrate 2 was taken out to the atmosphere. In this case, the total supply time of the etching gas is 5 minutes (= 15 seconds × 20 times), and the total supply time of the purge gas is 10 minutes (= 30 seconds × 20 times).

  FIG. 4 is a diagram showing the light reflectance of the polycrystalline silicon substrate 2 etched under the above-described etching conditions. As shown in FIG. 4, after the treatment, the light reflectance can be greatly reduced to about 10% in the visible light region after the treatment. Furthermore, as a result of observing the surface of the silicon substrate 2, innumerable irregularities having a diameter of several hundred nm were formed on the surface of the silicon substrate 2, but formation of a porous layer was not recognized inside. As a result of trial manufacture of a solar battery cell using this silicon substrate 2, as shown in “Example 1” of FIG. 5, the open circuit voltage Voc, the short circuit current Jsc, the fill factor F.V. F. , Conversion efficiency Effi. However, it was larger than Comparative Example 1 and Comparative Example 2, and good cell characteristics could be obtained.

  Here, FIG. 5 is a diagram showing the characteristics of the solar battery cell using the silicon substrate surface-treated by different processing methods. "Comparative example 1" in FIG. 5 is a wet etching method that has been widely used conventionally (etching solution: 10% KOH aqueous solution to which isopropyl alcohol is added, liquid temperature: 90 ° C., immersion time: 20 minutes) Thus, the characteristics of a solar battery cell produced using a polycrystalline silicon substrate having irregularities formed on the surface.

Further, “Comparative Example 2” in FIG. 5 is a characteristic of a solar battery cell manufactured using a silicon substrate subjected to the following surface treatment. First, the polycrystalline silicon substrate surface was continuously etched for 5 minutes by a ClF ₃ / Ar mixed gas (the gas flow rate and pressure were the same as those in the first embodiment). Here, when the surface of the silicon substrate after etching was observed, a porous layer having a thickness of about 250 nm was formed. Next, the porous layer formed on the silicon substrate surface was etched by being immersed in a 10% NaOH aqueous solution for about 5 minutes. Then, the photovoltaic cell of the comparative example 2 was produced according to the normal manufacturing process.

  And "Example 3" in FIG. 5 is the characteristic of the photovoltaic cell using the silicon substrate 2 processed by the surface treatment method of Embodiment 3 described later.

<C. Effect>
In the surface treatment method according to the first embodiment, fine irregularities are formed little by little on the surface of the silicon substrate using an etching gas containing ClF _3, and the component of the unreacted etching gas is generated inside the silicon substrate each time. Since it is removed with a purge gas before entering the surface, it is possible to realize a surface with low reflectance suitable for solar cells while preventing the generation of a porous layer caused by etching inside the silicon substrate.

  This makes it possible to achieve both the confinement of incident light and the reduction of carrier recombination. As a result, the open circuit voltage Voc, the short-circuit current Jsc, the fill factor F.V. F. , Conversion efficiency Effi. It is possible to realize a favorable solar battery cell having a large.

In the first embodiment, Ar is used as a dilution gas for ClF ₃ , but it is not always necessary to dilute, and the dilution gas is not limited to Ar. Other inert gases (He, Ne, Kr,...) And N ₂ gas can be used as the dilution gas.

In the first embodiment, N ₂ is used as the purge gas, but an inert gas (He, Ne, Ar,...) May be used instead. Further, when the ClF ₃ gas is sufficiently diluted and supplied as in the first embodiment, the purge gas is not necessarily required, and only the supply of the ClF ₃ gas is turned off and the dilution gas is continuously supplied. The etching reaction on the surface of the silicon substrate 2 can be stopped. In this case, the dilution gas also serves as the purge gas.

  In the first embodiment, the time for one etching gas supply step is 15 seconds. However, the same experiment is performed by changing the supply time. As a result, the same effect can be obtained within 30 seconds. I was able to.

<Embodiment 2>
In the first embodiment, an etching gas and a purge gas are alternately supplied into the reaction vessel 1, and unreacted ClF ₃ (in addition to this, F, Cl, etc.) adsorbed on the silicon substrate surface is removed in the purge gas supply step. Separated. However, it may be difficult to completely remove these unreacted ClF ₃ (in addition to this, F, Cl, etc.). In this case, the etching reaction may continue to proceed inside the silicon substrate, and a porous layer may be formed.

Therefore, in the silicon substrate surface treatment method according to the second embodiment, as shown in FIG. 6, unreacted ClF ₃ (adsorbed on the silicon substrate surface by stopping the exhaust of the reaction vessel 1 in the purge gas supply step). In addition, the removability of F, Cl, etc. is enhanced. Here, FIG. 6 is a diagram for explaining the silicon substrate surface treatment method according to the second embodiment. A silicon substrate surface treatment method according to the second embodiment will be described below with reference to FIG.

<A. Configuration>
Since the configuration of the silicon substrate surface treatment apparatus according to the second embodiment is the same as that of the first embodiment, a detailed description thereof will be omitted.

<B. Treatment method of silicon substrate surface>
First, as in the first embodiment, the silicon substrate 2 to be surface-treated is placed on the substrate stage 3 in the reaction vessel 1 evacuated through the gas exhaust pipe 6. Next, in the process of time T ₁ <t <T ₂ , by supplying an etching gas containing ClF ₃ into the reaction vessel 1, the silicon substrate surface is etched to form irregularities. Here, the gas exhaust valve 9 is in an ON state and exhausts the reaction vessel 1 at a constant exhaust speed.

Next, in the purge gas supply process at time T ₃ <t <T ₄ , the purge gas is supplied into the reaction vessel 1 to remove unreacted etching gas components before entering the silicon substrate. At this time, in the silicon substrate surface treatment method according to the second embodiment, the gas exhaust valve 9 installed in the middle of the gas exhaust pipe 6 is turned off simultaneously with turning on the gas supply valve 7 of N ₂ gas. And exhausting the reaction vessel 1 is stopped. As a result, the N ₂ gas introduced into the reaction vessel 1 is not exhausted, and the N ₂ gas pressure in the reaction vessel 1 greatly increases as shown in FIG.

Since a large number of N ₂ molecules are incident on the surface of the silicon substrate 2, unreacted ClF ₃ adsorbed on the surface of the silicon substrate 2 (in addition to this, F, Cl, etc.) , Detachment is promoted and quickly removed. Since the surface treatment method other than turning off the gas exhaust valve 9 when introducing the purge gas is the same as that of the first embodiment, a detailed description thereof will be omitted.

<C. Effect>
According to the silicon substrate surface treatment method of the second embodiment, the exhaust valve 9 is turned off in the purge gas supply step. As a result, in the purge gas supply process, the flux of N ₂ molecules incident on the surface of the silicon substrate 2 can be made larger than in the first embodiment, and ClF ₃ adsorbed on the surface (in addition to this, F, Cl, etc.) can be improved. As a result, the purge gas supply time can be shortened compared to the case where the reaction vessel 1 described in the first embodiment is always evacuated.

  As in the first embodiment, the same effect can be obtained if the etching gas supply time is 30 seconds or less.

<Embodiment 3>
In the third embodiment, in the purge gas supply step, a part of the purge gas is converted into plasma by discharge, and the plasma-generated purge gas is used, so that ClF ₃ (which is a component of the unreacted etching gas adsorbed on the silicon substrate surface). In addition, a surface treatment method for a silicon substrate that can desorb and remove F, Cl, etc.) with higher efficiency will be described.

<A. Configuration of surface treatment apparatus for silicon substrate>
FIG. 7 is a diagram schematically showing the configuration of the silicon substrate surface treatment apparatus according to the third embodiment. As shown in FIG. 7, in the silicon substrate surface treatment apparatus according to the third embodiment, a configuration capable of generating inductively coupled RF plasma is added to the configuration of the first embodiment.

  Specifically, a dielectric 11 such as alumina is disposed on the upper portion of the reaction vessel 1. An antenna 12 is disposed above the reaction vessel 1 via a dielectric 11. A matching device 13 is connected to the antenna 12. The matching unit 13 is connected to an RF power source 14 having a frequency of 13.56 MHz, for example. The control unit 10 is connected to the RF power source 14 and is configured to control the operation of the RF power source 14. Other configurations are the same as those of the first embodiment, and the same components are denoted by the same reference numerals, and redundant description is omitted.

  In the silicon substrate surface treatment apparatus according to the third embodiment, for example, a high-frequency current generated from an RF power supply 14 having a frequency of 13.56 MHz is supplied to the antenna 12 via the matching unit 13 and is radiated from the antenna 12. Electric power is introduced into the reaction vessel 1 through a dielectric 11 such as quartz or alumina.

  If the gas pressure in the reaction vessel 1 is within an appropriate range (1 mTorr to 100 Torr), gas plasma is easily generated by RF discharge. Further, the RF power source 14 is electrically connected to the control unit 10, and the RF power source 14 can be turned on / off, that is, the plasma can be turned on / off in synchronization with the timing of supplying or exhausting the etching gas or purge gas. It has become.

<B. Treatment method of silicon substrate surface>
Next, an example of a processing method using the above-described silicon substrate surface processing apparatus will be described with reference to FIG. FIG. 8 is a diagram for explaining the silicon substrate surface treatment method according to the third embodiment. For example, when the purge gas supply process starts at t = T ₃ , T ₇ , T ₁₁ , the control unit 10 controls the RF power supply 14 to be turned on simultaneously with turning on the N ₂ gas supply valve 7. To do.

When the RF power source 14 is turned on, nitrogen plasma is generated in the reaction vessel 1, and not only N ₂ gas particles supplied from the purge gas supply pipe 5 but also chemically active in the reaction vessel 1. Nitrogen atoms (N) and ions (N ₂ ⁺ , N ⁺ ) also exist. Further, an electric field region called an ion sheath is generated on the surface of the silicon substrate 2 placed in the plasma, and N ₂ ⁺ and N ⁺ ions in the plasma are accelerated and enter the substrate surface. When these particles are incident on the surface of the silicon substrate 2, ClF ₃ (in addition to this, F, Cl, etc.), which is a component of the unreacted etching gas adsorbed, is efficiently desorbed and removed. .

Next, specific processing conditions of the present invention will be described. In the etching gas supply step, the same processing conditions as those of the first embodiment (ClF ₃ gas flow rate: 10 sccm, Ar gas flow rate: 490 sccm, ClF ₃ / Ar gas pressure: 10 Torr, etching gas supply time: 15 seconds) were set. In the purge gas supply step, the processing conditions were set to N ₂ gas flow rate: 500 sccm, N ₂ gas pressure: 10 Torr, RF power: 300 W, purge gas and RF power supply time: 10 seconds.

  After this etching gas supply step and purge gas supply step were repeated 20 times, the silicon substrate 2 was taken out from the reaction vessel 1 to the atmosphere. Here, the total supply time of the etching gas is 5 minutes (= 15 seconds × 20 times), and the total supply time of the purge gas is 3 minutes and 20 seconds (= 10 seconds × 20 times).

As a result of trial manufacture of a solar battery cell using a polycrystalline silicon substrate 2 subjected to ClF ₃ gas etching under these conditions, no porous layer was generated on the surface of the silicon substrate, and “Example 3” in FIG. Good cell characteristics as shown in FIG. Thus, by converting the purge gas into plasma, ClF ₃ adsorbed on the silicon surface (in addition to this, F, Cl, etc.) can be desorbed and removed more efficiently, and the purge gas supply time can be reduced to 30. It has become possible to shorten the time from seconds to 10 seconds.

<C. Effect>
In the silicon substrate surface treatment method according to the _third embodiment, as in the first embodiment, the supply of the etching gas containing ClF ₃ and the supply process of the purge gas are alternately performed. It is possible to form a good low-reflective silicon surface without any defects. And the solar cell of a favorable characteristic is realizable.

  Furthermore, since the surface treatment method for a silicon substrate according to the third embodiment converts the purge gas into plasma, the purge gas supply time can be shortened.

  As in the first embodiment, the same effect can be obtained if the etching gas supply time is 30 seconds or less.

Further, as described in the second embodiment, the exhaust valve 9 may be turned off during the purge gas introduction. By turning off the exhaust valve 9, the flux of N ₂ molecules incident on the surface of the silicon substrate 2 can be increased, and the removability of ClF ₃ adsorbed on the surface of the silicon substrate 2 is further enhanced. Can do. As a result, the purge gas supply time can be further shortened.

1 is a schematic diagram illustrating a configuration of a surface treatment apparatus for a silicon substrate according to a first embodiment. FIG. 5 is a diagram for explaining the silicon substrate surface treatment method according to the first embodiment; It is a figure which shows the relationship between the etching gas supply time which concerns on Embodiment 1, and the thickness of a porous layer. It is a figure which shows the light reflectivity of the silicon substrate surface which concerns on Embodiment 1. FIG. 3 is a diagram showing a table of cell characteristics of the solar battery cell according to Embodiment 1. FIG. 6 is a diagram for explaining a silicon substrate surface treatment method according to Embodiment 2. FIG. FIG. 6 is a schematic diagram showing a configuration of a surface treatment apparatus for a silicon substrate according to a third embodiment. FIG. 6 is a diagram for explaining a surface treatment method for a silicon substrate according to a third embodiment.

Explanation of symbols

1 reaction vessel, 2 silicon substrate, 3 substrate stage, 4 etching gas supply pipe, 5 purge gas supply pipe, 6 gas exhaust pipe, 7 etching gas supply valve, 8 purge gas supply valve, 9 gas exhaust valve, 10 controller, 11 dielectric Body, 12 antennas, 13 matcher, 14 RF power supply.

Claims (5)

(A) installing a silicon substrate in a evacuated reaction vessel;
(B) etching the silicon substrate surface to form irregularities by supplying an etching gas containing ClF ₃ into the reaction vessel;
(C) removing a component of the unreacted etching gas adsorbed on the silicon substrate surface by supplying a purge gas into the reaction vessel;
With
A surface treatment method for a silicon substrate, wherein the step (b) and the step (c) are alternately repeated.   2. The method for surface treatment of a silicon substrate according to claim 1, wherein the step (c) includes a step of stopping exhaust in the reaction vessel while supplying the purge gas.   3. The method according to claim 1, wherein the step (c) includes a step of converting a part of the purge gas into a plasma, and removing a component of the unreacted etching gas with the purged purge gas. 4. A method for surface treatment of a silicon substrate.   4. The surface treatment of a silicon substrate according to claim 1, wherein the one step (b) includes a step of supplying the etching gas into the reaction vessel for a period of 30 seconds or less. Method. A method for manufacturing a solar cell, comprising applying the surface treatment method for a silicon substrate according to any one of claims 1 to 4.

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