JP2007323260A - Image memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image memory system quickly reading the pixel data of the same section of adjacent lines necessary for image processing. <P>SOLUTION: This image memory system 11 is provided with: a plurality of memories 13; and a memory controller 15 for making the plurality of memories 13 store the image data. The memory controller 15 writes the adjacent lines of the image data in the same memory address of the different memories. A memory controller circuit 15 reads the data from the same memory address of the plurality of memories 13, and simultaneously reads the pixel data of the same section of the plurality of adjacent lines. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image memory system that stores image data, and more particularly to a technique that can cope with random access at high speed.

  Conventionally, in a broadcasting station or the like, a video switching device called a switcher is used for video switching or editing work. The switcher is provided with a special effect device that gives a special effect to the image.

  The special effect device performs an interpolation process using an image memory system to reduce, rotate, and deform the image. The image memory system includes a frame memory, and a luminance signal, a color difference signal, and a key signal for one frame are written in the frame memory. As the frame memory, a synchronous DRAM (hereinafter referred to as SDRAM) is preferably used. Then, a plurality of pixel data in a predetermined range is read from the frame memory by random access, and interpolation processing is performed using the data of the plurality of pixels.

  The plurality of pixel data in a predetermined range for interpolation is pixel data of the same part of adjacent lines, and the same part here means that the position along the line direction is the same (the same applies hereinafter). . For example, data of 4 points (2 pixels × 2 lines) is read out, and data of 8 points (4 pixels × 2 lines) is read out, for example. In the special effect device, it is desired that such data of a plurality of pixels can be read at high speed.

In an example of the prior art that speeds up access to the SDRAM, the memory controller determines whether or not the bank address is continuous by a plurality of continuous commands, and rearranges the commands so that the bank addresses are not continuous ( Patent Document 1).
JP 2001-256106 A

  However, in the conventional image memory system, since each line is simply written in the memory in order, the pixel data of the same part of the adjacent line is arranged at different addresses in one memory, and the data In order to read out data, it is necessary to designate different addresses in order, and thus there is a problem that it is not easy to speed up the reading operation of a plurality of pixel data necessary for interpolation. In particular, in a broadcasting station apparatus, in order to ensure real-time properties suitable for live broadcasting, and further to process HD (High Definition) video, it is possible to perform interpolation without causing data loss with a high-speed pixel clock. It is required to read out data, and therefore further speedup is desired.

  The above-mentioned Patent Document 1 speeds up access to a memory by rearranging commands, but satisfies the requirement of reading out a plurality of pixel data of the same portion of adjacent lines at the maximum speed as described above. is not.

  The present invention has been made to solve the conventional problems, and an object of the present invention is to provide an image memory system capable of reading out pixel data of the same portion of an adjacent line necessary for image processing at high speed. .

  An image memory system of the present invention includes a plurality of memories and a memory controller that distributes and stores image data in the plurality of memories, and the memory controller assigns adjacent lines of image data to the same memory address of different memories. And a read control means for simultaneously reading out pixel data of the same portion of a plurality of adjacent lines by reading data from the same memory address of the plurality of memories.

  With this configuration, adjacent lines are written to the same memory address of different memories, and data is read from the same memory address of multiple memories, so that pixel data of the same part in adjacent lines can be read simultaneously using the same memory address. Therefore, it is possible to read out pixel data of the same part of the adjacent line necessary for image processing at high speed.

  In the image memory system of the present invention, the read control means accepts designation of a read pixel address in the image data and includes the read pixel address based on a line number and a line direction address included in the read pixel address. Data in a predetermined memory address portion including a memory address corresponding to the read pixel address is read out from a plurality of memories each storing line data and adjacent line data.

  With this configuration, it is possible to receive the designation of the pixel address of the readout position, perform readout control according to the pixel address, and read out the pixel data of the same portion of the adjacent line necessary for image processing at high speed.

  In the image memory system of the present invention, the writing control unit repeatedly performs a process of writing the data of a plurality of lines arranged in the image data to the same address area of the plurality of memories, respectively. When moving to the address area, at least one line is written redundantly.

  With this configuration, adjacent line data can be appropriately distributed and written to the same address in a plurality of memories, and the pixel data of the same part of the adjacent line can be read simultaneously using the written data. Can do. In addition, regarding the data written in the portion where the address area changes, the pixel data of the same portion of the adjacent line can be simultaneously read using the data written in duplicate.

  Also, in the image memory system of the present invention, the plurality of memories are n + 1 (n is a positive number) from 0 to n, and the write control means includes 0 to n−1. For the memory, control is performed to write each line to the memory whose memory number is the same as the remainder obtained by dividing the line number by n. For the nth memory, data on the same line as the 0th memory is stored as 0. Control is performed with a shift of one line to the number memory.

  With this configuration, adjacent line data can be appropriately distributed and written to the same address in a plurality of memories, and the pixel data of the same portion of the adjacent line is read at high speed using the data written in this way. be able to.

  In the image memory system of the present invention, each memory has a plurality of banks for performing pipeline processing, and the write control means writes the same data to the plurality of banks of the respective memories. The memory number n + 1 is a number obtained by adding 1 to the number of banks.

  With this configuration, the same data can be copied to a plurality of banks in the same memory in order, and data can be written simultaneously into the 0th and nth memories, so that data can be written efficiently and at high speed.

  In the image memory system according to the present invention, the readout control means may have the same memory address from a memory having a memory number corresponding to a remainder obtained by dividing a line number of a pixel at a readout position by n and a memory number obtained by adding 1 to the remainder. Read data. With this configuration, it is possible to read out the pixel data of the same portion of the adjacent line from the same memory address of the plurality of memories by using the data appropriately distributed to the plurality of memories by the above writing processing, and for image processing. Necessary data can be read at high speed.

  Another aspect of the present invention is a memory control method for an image memory system that distributes and stores image data in a plurality of memories, and writes adjacent lines of the image data to the same memory address in different memories. By reading data from the same memory address of the plurality of memories, pixel data of the same portion of a plurality of adjacent lines is read simultaneously. This aspect also provides the above-described advantages of the present invention.

  According to the present invention, adjacent lines of image data are written to the same memory address of different memories, and data is read from the same memory address of a plurality of memories, so that pixel data of the same part in adjacent lines can be read simultaneously. In addition, it is possible to provide an image memory system having an effect that the pixel data necessary for image processing can be read at a high speed by random access.

  Hereinafter, an image memory system according to an embodiment of the present invention will be described with reference to the drawings.

  An image memory system according to an embodiment of the present invention is shown in FIG. The image memory system of this embodiment is provided in a video special effect device provided in a switcher for a broadcasting station. The image memory system stores image data, and outputs data necessary for interpolation from the stored image data. Data necessary for the interpolation is pixel data of the same part of a plurality of lines. In the following example, 8-point reading is performed. 8-point reading is a process of reading data of 4 pixels × 2 lines. In particular, the present embodiment enables simultaneous reading of 8 points and improves the reading speed.

  In FIG. 1, the image memory system 11 includes a plurality of memories 13, a memory controller circuit 15 that controls the memories 13, and a buffer 17 that is disposed in front of the memory controller circuit 15. A write switch 19 and a read switch 21 are provided before and after each memory 13 and are controlled by a memory controller circuit 15.

  In the present embodiment, five memories 13 are provided as shown. Each memory 13 is a synchronous DRAM (SDRAM) and includes four banks. The five memories 13 constitute one frame memory, and store one frame of data.

  The memory controller circuit 15 is a circuit that controls writing to and reading from each memory 13, and performs random access to the memory 13. The image data to be written is input to the buffer 17 and supplied to the memory controller circuit 15. The memory controller circuit 15 controls the write switch 19 to write data to the memory 13. Read pixel address data is also input to the buffer 17 and supplied to the memory controller circuit 15. The read pixel address is the address of the pixel at the read position in the image. The memory controller circuit 15 controls the appropriate read switch 21 according to the read pixel address, and outputs necessary data from the memory 13.

  FIG. 2 shows one frame of image data written to the image memory system 11. The present embodiment is suitable for HD (High Definition) video, and one frame of image data is composed of 1920 × 1080 pixel data. That is, the number of horizontal lines is 1080, and the number of pixels in each line is 1920.

  Each line is divided into four segments for writing to memory. Each segment from the left end to the third contains 512 pixels, and the remaining one segment contains 384 pixels. The width of the segment (512 pixels) is set so as to match the width of one bank of the memory described later, that is, 512 columns per row (column). Such a segment is referred to as a pixel segment in this embodiment. Pixel segments are numbered from left to right and from top to bottom. For example, line 0 includes pixel segments 0-3, and line 1 includes pixel segments 4-7. The last line 1079 includes pixel segments 4316-4319.

  In this embodiment, the pixel position in the image data of FIG. 2 is referred to as a pixel address (X, Y). X is a line direction address (0 to 1919), and represents a pixel position (the number of pixels from the left end) on the line. Y is a line number (0-1079) and represents the vertical position of the line to which the pixel belongs. For example, the pixel P in FIG. 2 is the rightmost pixel in the pixel segment 0 of the line 0, and the pixel address is (511, 0).

  FIG. 3A and FIG. 3B are diagrams showing the image data in more detail, and show the data at the beginning of lines 0 and 1. The pixel data P is 30-bit data. One pixel data P is composed of a luminance signal Y, a color difference signal Cb or Cr, and a key signal K as shown in FIG.

  In the present embodiment, as will be described in detail later, in the image data reading process, 8-point reading is performed for interpolation processing. In 8-point readout, the pixel address at the upper left of the readout range is designated as the readout pixel address, and 8 pixels (2 lines × 4 pixels) including the readout pixel address are read out. In the example shown in the figure, a pixel address (0, 0) is designated, and the first four pixels on lines 0 and 1 are read out.

  FIG. 4 shows a write control operation in the present embodiment. As shown in the figure, one frame of image data is written in five memories 0 to 4.

  Among the five memories, for the memories 0 to 3, the memory controller circuit 15 performs control to write each line into the memory having the number of mod (line number / 4). mod (line number / 4) is the remainder of dividing the line number by 4.

  Further, for the fifth memory 4, the memory controller circuit 15 performs control to write data on the same line as the memory 0 while shifting the data to the memory 0 by one line. That is, the memory 4 is written with the same data as the memory 0 after the line 4 except for the line 0.

  Thus, line 0 is written to memory 0 as shown. Lines 4, 8... Are written into memory 0 and memory 4. .. Are written in the memory 1, the lines 2, 6... Are written in the memory 2, and the lines 3, 7,.

  The lower half of FIG. 4 shows the arrangement of data in the memories 0 to 4. Here, one bank of each memory is shown. In each memory, one row (column) stores one pixel segment. Therefore, one line is written in four rows. Although not shown, each row (column) is composed of 512 columns, and data of one pixel is written in one column.

  Specifically, in memory 0, pixel segments 0-3 on line 0 are written to row addresses 0-3, pixel segments 16-19 on line 4 are written to row addresses 4-7, and thereafter A line is written into four rows. The same applies to other memories. In the memory 0 and the memory 4, the data is shifted by four row addresses, so that the data is shifted by one line.

  The writing process has been described above. As described above, the memory controller circuit 15 writes one line at a time to the same address area (4 columns area) of five memories, and then writes one line at a time to the next same address area of the five memories, This process is repeated.

  As a result of such a writing process, as shown in the figure, the memory controller circuit 15 can write adjacent lines of image data to the same memory address in different memories. It is suitably used.

  In addition, the memory controller circuit 15 writes the lines redundantly when the address area changes. For example, the line 4 is written to the row addresses 0 to 3 of the memory 4 and the row addresses 4 to 8 of the memory 0 in an overlapping manner. This redundant writing also functions favorably in the reading process described later.

  5 and 6 show the overall configuration of each memory. FIGS. 5A, 5B, and 5C are the memory 0, the memory 1, and the memory 2, respectively. FIGS. 6A and 6B are the memory 3 and the memory 4, respectively. It is. As shown in the figure, each memory is composed of four banks 0-3. The four banks 0 to 3 have a configuration for realizing pipeline processing, and the same data is written therein.

  FIG. 7 shows the order of writing data to four banks of five memories. In FIG. 7, step S <b> 0 writes the line 0 to the buffer 17 at the same time as writing the line 0 to the bank 0 of the memory 0. In step S 1, the data of line 0 written to the buffer 17 is written to the bank 1, and the line 1 is written to the bank 0 of the memory 1 and simultaneously written to the buffer 17. In step S 2, the data on line 0 is written to bank 2, the data on line 1 is written to bank 1, and further, line 2 is written to bank 0 of memory 2 and simultaneously written to buffer 17. Thereafter, the same processing is repeated, and each step performs copying of lines between banks and writing of new lines.

  In FIG. 7, step S4 writes the data of line 1 from buffer 17 to bank 3, writes the data of line 2 from buffer 17 to bank 2, writes the data of line 3 from buffer 17 to bank 1, 4 is written to memory 0 and bank 0 of memory 4. The memory 0 and the memory 4 are processed in the same step for the data after the line 4.

  As described above, in this embodiment, the number of memories is set to one more than the number of banks, so that writing to the memory 0 and the memory 4 can be performed simultaneously, and data can be written efficiently and at high speed. be able to.

  Next, the read control operation in the present embodiment will be described. The memory controller circuit 15 receives an input of the read pixel address and reads data of 8 pixels (4 pixels × 2 lines) including the pixel of the read pixel address, as will be described below.

  In the read control, the memory controller circuit 15 specifies a memory having a number of mod (line number / 4) and a memory having the next number based on the line number of the read pixel address. Since these two memories have undergone the above writing process, the line to which the pixel of the read pixel address belongs and the next line are stored at the same memory address. Therefore, the memory controller circuit 15 reads out necessary four-pixel data from these two memories using the same memory address. The head memory address of the four pixels is a memory address corresponding to the read pixel address, and more specifically, a memory address when the pixel of the read pixel address is written in the memory of mod (line number / 4). In this manner, the memory controller circuit 15 can read data of 8 pixels including the read pixel address by simultaneous reading of two lines by utilizing the data arrangement of the memory.

  FIG. 8 shows the above read process in more detail. In FIG. 8, the read pixel address = (A, B). It is assumed that B ÷ 4 = C remainder D and A ÷ 512 = E remainder F. 512 is the number of pixels of one pixel segment.

  The memory controller circuit 15 reads data from the memory D and the memory D + 1 because mod (line number / 4) is D. The pixel data (A, B) is written in the column address F of the row address C + E in the memory D. Therefore, the memory controller circuit 15 reads the data of the column addresses F to F + 3 of the row address C + E of the memory D and the memory D + 1. By this processing, the memory controller circuit 15 can read data of 8 pixels including the pixel of the read pixel address (A, B) at the upper left corner.

  FIG. 9 shows a specific example of the above processing. In the example shown in the figure, 8 points of data at the upper left corner of one frame are read out. In this case, the read pixel address is (0, 0). 0 ÷ 4 = 0 remainder 0 and 0 ÷ 512 = 0 remainder 0. Therefore, the memory controller circuit 15 reads the data at the column address 0 to 3 at the row address 0 from the memory 0 and the memory 1. In this way, data of 8 points at the upper left corner of one frame is read out.

  FIG. 10 shows another example. In the example of FIG. 10, the read pixel address is (0, 3). In this case, 3 ÷ 4 = 0 remainder 3 and 0 ÷ 512 = 0 remainder 0. Therefore, the memory controller circuit 15 reads the data at the column address 0 to 3 at the row address 0 from the memory 3 and the memory 4.

  From the example of FIG. 10, it can be seen that the fifth memory 4 is provided. If there is no memory 4, the line next to the line written in the memory 3 is not written to the same memory address of another memory. For this reason, some lines cannot be read at high speed using the same memory address. On the other hand, in this embodiment, the memory 4 is provided, and the data is duplicated in the memory 4 and the memory 0, so that an arbitrary line and the next line are always stored at the same address of the two memories. Is done. Therefore, the memory controller circuit 15 can read any two lines of data from the same memory address.

  FIG. 11 shows pipeline processing using a plurality of banks. In the example of the figure, data of 8 pixels corresponding to the read pixel address (A, B) is read from the bank 0. Data corresponding to the read pixel address (A + 1, B) is read from the bank 1. Similarly, data corresponding to read pixel addresses (A + 2, B) and (A + 3, B) are read from banks 2 and 3, respectively. At the time of reading, bank precharge and bank active processes are performed in parallel with data reading. This process is a general pipeline process.

  The image memory system 11 according to the embodiment of the present invention has been described above. In the present embodiment, the memory controller circuit 15 functions as the write control means and the read control means of the present invention. According to the present embodiment, the memory controller circuit 15 writes adjacent lines to the same memory address of different memories, and reads data from the same memory address of a plurality of memories. As a result, the image memory system 11 can simultaneously read out the pixel data of the same portion in the adjacent line using the same memory address, and therefore the pixel data of the same portion in the adjacent line necessary for image processing can be read at high speed. Can be read. For example, the above-described 8-point reading can be performed by random access, which can meet the demand for high speed required by a special effect device for HD of a broadcasting station.

  Further, according to the present embodiment, as described above, the memory controller circuit 15 accepts the designation of the readout pixel address in the image data, and based on the line number and the line direction address included in the readout pixel address, the readout pixel Data of a predetermined memory address portion including a memory address corresponding to a read pixel address is read from a plurality of memories each storing data of a line including an address and data of an adjacent line. In this way, designation of the pixel address of the readout position is accepted, readout control is performed according to the pixel address, and pixel data of the same portion of the adjacent line necessary for image processing can be read out at high speed.

  Further, according to the present embodiment, the memory controller circuit 15 repeats the process of writing the data of a plurality of lines arranged in the image data to the same address area of the plurality of memories, respectively, so that one address area can be changed to another address. When moving to the area, at least one line is written redundantly. In the above example, one line is written to the memory 0 and the memory 4 redundantly. By such processing, adjacent line data can be appropriately distributed and written to the same address of a plurality of memories, and pixel data of the same part of the adjacent line can be read simultaneously using the written data. . In addition, regarding the data written in the portion where the address area changes, the pixel data of the same portion of the adjacent line can be simultaneously read using the data written in duplicate.

  Further, according to the present embodiment, the plurality of memories are n + 1 memories from 0 to n (n is a positive number, 4 in the above embodiment), and the memory controller circuit 15 To the (n-1) th memory, control is performed to write each line to the memory whose memory number is the same as the remainder obtained by dividing the line number by "n". Control is performed to write the data on the same line with a shift of one line to the 0th memory. As a result, the data of the adjacent line can be appropriately distributed and written to the same address of a plurality of memories, and the pixel data of the same part of the adjacent line can be read at high speed using the data written in this way. Can do.

  Further, according to the present embodiment, each memory has a plurality of banks for performing pipeline processing, and the write control means writes the same data to the plurality of banks of each memory, and the number of memories n + 1 is a number obtained by adding 1 to the number of banks. As a result, the same data is sequentially copied to a plurality of banks in the same memory, and the data can be written simultaneously into the 0th and nth memories, so that the data can be written efficiently and at high speed.

  In addition, according to the present embodiment, the memory controller circuit 15 reads the data of the same memory address from the memory having the memory number that coincides with the remainder obtained by dividing the line number of the pixel at the reading position by n and the memory number obtained by adding 1 to the remainder. Is read. This makes it possible to read out the pixel data of the same part of the adjacent line from the same memory address of the plurality of memories using the data appropriately distributed to the plurality of memories by the above writing processing, which is necessary for the image processing. Data can be read at high speed.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and it goes without saying that those skilled in the art can modify the above-described embodiments within the scope of the present invention.

  As described above, the image memory system according to the present invention has an effect of being able to read out the pixel data of the same portion of the adjacent line necessary for image processing at high speed, and is useful as a special effect device for HD. is there.

The figure which shows the image memory system in embodiment of this invention Diagram showing image data written to the image memory system (A) Diagram showing a part of pixel data of image data (b) Diagram showing a part of pixel data of image data The figure which shows writing control operation of image data (A) Diagram showing data written in memory 0 (b) Diagram showing data written in memory 1 (c) Diagram showing data written in memory 2 (A) Diagram showing data written in memory 3 (b) Diagram showing data written in memory 4 Diagram showing write operation to multiple banks The figure which shows the reading control operation | movement of 2 line simultaneous reading Diagram showing a specific example of read control operation The figure which shows another specific example of read-out control operation Diagram showing pipeline processing using multiple banks

Explanation of symbols

11 Image Memory System 13 Memory 15 Memory Controller Circuit 17 Buffer 19 Write Switch 21 Read Switch

Claims (7)

Multiple memories,
A memory controller for sorting and storing image data in the plurality of memories,
The memory controller is
Write control means for writing adjacent lines of image data to the same memory address in different memories;
An image memory system comprising reading control means for simultaneously reading out pixel data of the same portion of a plurality of adjacent lines by reading data from the same memory address of the plurality of memories.   The read control unit receives designation of a read pixel address in the image data, and based on a line number and a line direction address included in the read pixel address, the data of the line including the read pixel address and the data of an adjacent line are obtained. 2. The image memory system according to claim 1, wherein data of a predetermined memory address portion including a memory address corresponding to the read pixel address is read from a plurality of memories stored therein.   The writing control means repeats the process of writing the data of a plurality of lines arranged in the image data to the same address area of the plurality of memories, respectively, and moves from one address area to another address area. 3. The image memory system according to claim 1, wherein lines are written in duplicate. The plurality of memories are n + 1 (n is a positive number) from 0 to n,
The write control means performs control for writing each line to the memory of the memory number that matches the remainder of dividing the line number by n for the 0th to n−1th memories, On the other hand, the image memory system according to claim 1, wherein control is performed so that data on the same line as the 0th memory is written to the 0th memory while being shifted by one line. Each memory has a plurality of banks for pipeline processing,
The write control means writes the same data to the plurality of banks of each memory,
5. The image memory system according to claim 4, wherein the memory number n + 1 is a number obtained by adding 1 to the number of banks.   The read control means reads out data at the same memory address from a memory having a memory number corresponding to a remainder obtained by dividing a line number of a pixel at a reading position by n and a memory number obtained by adding 1 to the remainder. The image memory system according to 4 or 5. A memory control method of an image memory system for distributing and storing image data in a plurality of memories,
Write adjacent lines of the image data to the same memory address in different memories,
A memory control method, wherein pixel data of the same portion of a plurality of adjacent lines is read simultaneously by reading data from the same memory address of the plurality of memories.

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