JP2007318807A - Multiplex differential transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To transmit bit information signals of six bits using three signal lines to suppress generation of noise and to further reduce the number of signal lines. <P>SOLUTION: In a signal transmitter for multiplex differential transmission system connecting a signal transmitter and a signal receiver via a signal transmission line constituted of three signal lines, first and second differential drivers generate first and second output signals having a predetermined first signal voltage level and their reverse first and second outputs in response to first and second bit information signals of two bits, respectively. The second differential driver generates third output signals having a second voltage level and its reverse second output signals in response to third bit information signals of two bits. After the first output signal and the reverse third signal are synthesized, the synthesized signal is transmitted to the first transmission line. After the second output signal and the reverse first signal are synthesized, the synthesized signal is transmitted to the second transmission line. After the third output signal and the reverse second signal are synthesized, the synthesized signal is transmitted to the third transmission line. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multiple differential transmission system for transmitting a bit information signal of a plurality of bits using a signal transmission path composed of a small number of signal lines.

  In recent years, in flat panel displays typified by liquid crystal televisions and plasma televisions, the signal speed for transferring image information has been increased as the image quality increases from VGA (Video Graphics Array) to XGA (eXtended Graphics Array). Yes. Therefore, low-amplitude differential transmission devices have come to be used as high-speed digital data transmission devices.

  This differential transmission device is a transmission device that sends signals of opposite phases to each other through one balanced cable or two wiring patterns formed on a printed circuit board. Features include low noise, strong resistance to external noise, low voltage amplitude, high-speed data transmission, and the like, and the introduction of the high-speed transmission technique is progressing particularly in the display field.

Japanese Patent No. 3507687. JP-A-4-230147.

  The differential transmission device has many merits in high-speed transmission as described above compared with a normal single-ended transmission device. However, since two signal lines are required for 1-bit data transmission, in order to realize multi-bit data transmission, the number of signal lines increases and the wiring area of the signal lines on the printed circuit board increases. Had problems such as. For this reason, it has become a big problem in realizing further high-speed transmission in the future.

  Regarding this problem, for example, in the data transmission system disclosed in Patent Document 1, three signal lines are used, and one signal line is used as a complementary data line, whereby three 2-bit data transmissions are performed. (The differential transmission device according to the prior art requires four signal lines), and the number of signal lines has been reduced, but transmission using three signal lines is possible. There is a problem that the signal is not balanced and the radiation noise becomes larger than that of a normal differential transmission method.

  Further, in Patent Document 2, differential transmission of a 3-bit bit information signal is performed using three signal lines. However, there is a limitation that output signals of all three differential drivers must be different, or all three. It is not possible to transmit the state of 0 and 1 bits, and only 6 states can be transmitted from 3 bits (8 states) except for the state of all 0 and 1 bits. There was a point.

  The object of the present invention is to solve the above problems, to suppress the generation of noise, and to further reduce the number of signal lines, it is possible to transmit a 6-bit bit information signal using three signal lines It is an object to provide a multiple differential transmission system, and a signal transmitter and a signal receiver therefor.

According to a first aspect of the present invention, there is provided a signal transmitter including a signal transmitter, a signal receiver, and first, second, and third signal lines that connect the signal transmitter and the signal receiver. A signal transmitter for a multiple differential transmission system with a path,
In response to the 2-bit first bit information signal, a bipolar 4-level first output signal having a predetermined first signal voltage level, and an inverted first output signal which is a phase inverted signal of the first output signal A first differential driver that generates
In response to a 2-bit second bit information signal, a bipolar quaternary second output signal having the first signal voltage level, and an inverted second output signal that is a phase inverted signal of the second output signal; A second differential driver for generating
In response to a 2-bit third bit information signal, a bipolar four-valued third output signal having a second signal voltage level different from the first signal voltage level, and a phase inversion of the third output signal A third differential driver for generating an inverted second output signal that is a signal,
The first output signal and the inverted third output signal are combined and then transmitted to the first signal line,
The second output signal and the inverted first output signal are combined and then transmitted to the second signal line,
The third output signal and the inverted second output signal are combined and then transmitted to the third signal line.

A signal receiver according to a second aspect of the present invention is a signal receiver that receives three output signals received from the signal transmitter via a signal transmission path composed of first, second, and third signal lines. There,
A first termination resistor connected between the first signal line and the second signal line;
A second termination resistor connected between the second signal line and the third signal line;
A third termination resistor connected between the third signal line and the first signal line;
A first termination voltage generated by the first termination resistor, a second termination voltage generated by the second termination resistor, and a third termination voltage generated by the third termination resistor; And a decoding processing means for decoding and outputting the first, second and third bit information signals.

  A multiple differential transmission system according to a third aspect of the invention includes the signal transmitter according to the first aspect of the invention and the signal receiver according to the second aspect of the invention.

A signal transmitter according to a fourth aspect of the present invention is a signal transmitter comprising a signal transmitter, a signal receiver, and first, second and third signal lines connecting the signal transmitter and the signal receiver. A signal transmitter for a multiple differential transmission system with a path,
In response to a 1-bit first bit information signal, a bipolar binary first output signal having a predetermined first signal voltage level and an inverted first output signal which is a phase inverted signal of the first output signal A first differential driver that generates
In response to a 1-bit second bit information signal, a bipolar binary second output signal having a predetermined second signal voltage level different from the first signal voltage level by a first differential voltage; A second differential driver that generates an inverted second output signal that is a phase inverted signal of the second output signal;
In response to a 1-bit third bit information signal, a bipolar binary third output signal having the first signal voltage level, and an inverted third output signal that is a phase inverted signal of the third output signal; A third differential driver for generating
In response to a 1-bit fourth bit information signal, a bipolar binary fourth output signal having the second signal voltage level, and an inverted fourth output signal that is a phase inverted signal of the fourth output signal; A fourth differential driver for generating
In response to the 1-bit fifth bit information signal, the first signal voltage level has a predetermined third signal voltage level that differs from the first differential voltage by a second differential voltage that is smaller than the first differential voltage. A fifth differential driver for generating a bipolar binary fifth output signal and an inverted fifth output signal that is a phase inverted signal of the fifth output signal;
In response to the 6-bit information signal of 1 bit, the second signal voltage level is different from the second differential voltage by a third differential voltage that is smaller than the first differential voltage and larger than the second differential voltage. A sixth differential driver for generating a bipolar binary sixth output signal having a predetermined fourth signal voltage level and an inverted sixth output signal that is a phase inverted signal of the sixth output signal;
The first output signal, the second output signal, the inverted fifth output signal, and the inverted sixth output signal are combined and then transmitted to the first signal line,
The inverted first output signal, the inverted second output signal, the third output signal, and the fourth output signal are combined and then transmitted to the second signal line,
The inverted third output signal, the inverted fourth output signal, the fifth output signal, and the sixth output signal are combined and then transmitted to the third signal line.

A signal receiver according to a fifth aspect of the present invention is a signal receiver that receives three output signals received from the signal transmitter via a signal transmission path composed of first, second, and third signal lines. There,
A first termination resistor connected between the first signal line and the second signal line;
A second termination resistor connected between the second signal line and the third signal line;
A third termination resistor connected between the third signal line and the first signal line;
A first termination voltage generated by the first termination resistor, a second termination voltage generated by the second termination resistor, and a third termination voltage generated by the third termination resistor; And decoding processing means for decoding and outputting the first to sixth bit information signals.

  A multiplex differential transmission system according to a sixth invention is characterized by comprising the signal transmitter according to the fourth invention and the signal receiver according to the fifth invention.

  Therefore, according to the multiple differential transmission system according to the present invention, a 6-bit bit information signal can be differentially transmitted using three signal lines, in a state in which an increase in noise is suppressed, and compared with the prior art. Thus, differential transmission of a multi-bit bit information signal can be performed with less wiring.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

First embodiment.
FIG. 1 is a block diagram showing a configuration of a multiple differential transmission system according to a first embodiment of the present invention. In FIG. 1, the multiplex differential transmission system includes a signal transmitter 10, a signal receiver 20, and a signal transmission path 30 that connects these and includes three signal lines 31, 32, and 33. Is done.

  FIG. 2 is a waveform diagram showing the relationship between the signal waveforms of the output signals S11a, S11b, S12a and S12b of the differential drivers 11 and 12 of FIG. . FIG. 3 is a waveform diagram showing the relationship between the signal waveforms of the output signals S13a and S13b of the differential driver 13 of FIG. Further, FIG. 4 is a diagram showing the relationship between the bit information signals B1 and B2 inputted in the differential driver 13 of FIG. 1 and the output signals S11a and S11b. FIG. 5 is a diagram showing the relationship between the bit information signals B3 and B4 input in the differential driver 14 of FIG. 1 and the output signals S12a and S12b. FIG. 6 is a diagram showing the relationship between the bit information signals B5 and B6 inputted in the differential driver 15 of FIG. 1 and the output signals S13a and S13b.

In FIG. 1, a signal transmitter 10
(A) In response to the parallel 2-bit bit information signals B1 and B2, as shown in FIGS. 2 and 4, for example, a bipolar quaternary output signal having signal voltage levels of + 2V, + 1V, −1V, and −2V A differential driver 11 that outputs S11a and an inverted output signal S11b that is a phase inverted signal thereof;
(B) In response to the parallel 2-bit bit information signals B3 and B4, as shown in FIGS. 2 and 5, a bipolar quaternary output signal S12a having the same signal voltage level as that of the differential driver 11, and its A differential driver 12 that outputs an inverted output signal S12b that is a phase inverted signal;
(C) In response to the parallel 2-bit bit information signals B5 and B6, as shown in FIGS. 3 and 6, the signal voltage levels are slightly different from those of the differential drivers 11 and 12, for example, +2.2 V, +1. The differential driver 13 outputs a bipolar quaternary output signal S13a having signal voltage levels of 1V, -1.1V, and -2.2V, and an inverted output signal S13b that is a phase inverted signal thereof. The

  The output signal S11a and the inverted output signal S13b are combined and then transmitted to the signal receiver 20 via the signal line 31, and the output signal S12a and the inverted output signal S11b are combined and then transmitted via the signal line 32. The signal is transmitted to the signal receiver 20, and the output signal S 13 a and the inverted output signal S 12 b are combined and then transmitted to the signal receiver 20 via the signal line 33. Here, each differential driver 11, 12, 13 outputs output signals S11a-S16a and its inverted output signals S11b-S16b in synchronization with a clock synchronized with the input bit information signals B1-B6.

The signal receiver 20 includes three A / D converters 21, 22, 23, a clock recovery circuit 24, a table memory 25a, a decoding processor 25 made of, for example, a CPU or DSP, and three terminations. It comprises resistors 41, 42 and 43. Here, the voltage on the signal receiver 20 side of each signal line 31, 32, 33 is set to Vs1, Vs2, Vs3. Further, a termination resistor 41 having a resistance value R1 is connected between the signal line 31 and the signal line 32, and a termination resistor 42 having a resistance value R2 is connected between the signal line 32 and the signal line 33. A termination resistor 43 having a resistance value R 3 is connected between the signal line 33 and the signal line 31. The termination voltage V1 generated by the termination resistor 41 is A / D converted by the A / D converter 21, and then output to the decoding processor 25. The termination voltage V2 generated by the termination resistor 42 is A / D converted by the A / D converter 22 and then output to the decoding processor 25. Further, the termination voltage V3 generated by the termination resistor 43 is A / D converted by the A / D converter 23 and then output to the decoding processor 25. The clock recovery circuit 24 includes, for example, a rising edge detection circuit and a PLL circuit, and includes signal lines 31, 32, and 33.
The rising edge of each signal transmitted by, is detected, a clock having a predetermined frequency is generated in synchronization with the detection result, and is output to the A / D converters 21, 22, 23 and the decoding processor 25.

  7 and 8 show bit information signals B1-B6 transmitted in the multiplex differential transmission system of FIG. 1, and termination voltages V1, V2, V3 generated by termination resistors 41, 42, 43 of the signal receiver 20. It is a figure which shows the relationship. The decoding processor 25 has a built-in table memory 25a in which the information tables of FIGS. 7 and 8 are stored in advance. The decoding processor 25 refers to the table in the table memory 25a and based on the termination voltages V1, V2, and V3 input from the A / D converters 21, 22, and 23, a 6-bit bit information signal B1. -B6 is judged and bit information signals B1-B6 of the judgment result are outputted. In the determination of the bit information in the decoding processor 25, the input termination voltages V1 to V6 are within a range of ± 10% of the termination voltage values in FIGS. 7 and 8, for example (this error range is the differential driver). 11 and 12 and the differential driver 13 is determined in accordance with the difference in signal voltage level.

As described above, according to the present embodiment, when each output signal and inverted output signal are transmitted by being superimposed on the three signal lines 31, 32, 33 by the differential drivers 11, 12, 13, respectively, The termination voltages V1, V2, and V3 appearing in the termination resistors 41, 42, and 43 connected to the adjacent signal lines all have different voltage values depending on the ²⁶ states of the 6-bit bit information signal. From these combinations, the original bit information signals B1-B6 can be decoded based on the termination voltages V1, V2, V3 detected by the A / D converters 21, 22, 23. In addition, the voltage applied to each signal line 31, 32, 33 of the signal transmission path 30 is 0 in total in any bit information transmission, and noise radiated from each signal line 31, 32, 33 is mutually mutually. Since they cancel each other, transmission with less noise is possible as in the normal differential transmission method.

  In the first embodiment, the differential drivers 11 and 12 output a bipolar quaternary output signal and an inverted output signal having substantially the same signal voltage level, while the differential driver 13 is a differential driver. As long as the output signal is a bipolar quaternary output signal and an inverted output signal having signal voltage levels different from those of 11 and 12. Preferably, the differential driver 13 outputs a bipolar quaternary output signal and an inverted output signal having a signal voltage level higher than the signal voltage level of the differential drivers 11 and 12.

In the first embodiment,
(1) Signal voltage levels of the differential drivers 11, 12, 13, and 14 = ± 1, ± 2;
(2) Signal voltage levels of the differential drivers 15 and 16 = ± 1.1, ± 2.2;
For example,
(1) Signal voltage levels of the differential drivers 11, 12, 13, and 14 = ± 1, ± 3;
(2) Signal voltage levels of the differential drivers 15 and 16 = ± 1.1, ± 3.3;
Or
(1) Signal voltage levels of the differential drivers 11, 12, 13, and 14 = ± 2, ± 3;
(2) Signal voltage levels of the differential drivers 15 and 16 = ± 2.2, ± 3.3;
It may be.

Second embodiment.
FIG. 9 is a block diagram showing a configuration of a multiple differential transmission system according to the second embodiment of the present invention. The multiple differential transmission system according to the second embodiment differs from the first embodiment in the following points.
(1) In place of the signal receiver 10 including three differential drivers 11, 12, 13 that output a pair of output signals and inverted output signals in response to 2-bit bit information signals, respectively, A signal receiver 10A including six differential drivers 11A, 12A, 13A, 14A, 15A, and 16A that output a pair of output signals and inverted output signals in response to bit information signals of bits is provided.
(2) A signal receiver 20A is provided instead of the signal receiver 20, and the signal receiver 20A includes a decoding processor 25 including a table memory 25b having a table different from the table of the table memory 25a.
Hereinafter, the difference will be described in detail.

  FIG. 10 is a waveform diagram showing the relationship between the signal waveforms of the output signals S11a, S11b, S12a, S12b, S13a, S13b, S14a, and S14b of the differential drivers 11A, 12A, 13A, and 14A of FIG. . FIG. 11 is a waveform diagram showing the relationship between the signal waveforms of the output signals S15a, S15b, S16a, and S16b of the differential drivers 15A and 16A of FIG. 9 and the assigned bit information.

In the signal transmitter 10A of FIG.
(1) In response to the 1-bit bit information signal B1, the differential driver 11A outputs a bipolar binary output signal S11a having a signal voltage level of ± 1 V, for example, and its inverted output signal S11b.
(2) The differential driver 12A is twice the signal voltage level of the differential driver 11A in response to the 1-bit bit information signal B2 (for example, it may be a natural number multiple of 3 or more). A bipolar binary output signal S12a having a signal voltage level of ± 2 V and its inverted output signal S12b are output.
(3) In response to the 1-bit bit information signal B3, the differential driver 13A, like the differential driver 11A, for example, a bipolar binary output signal S13a having a signal voltage level of ± 1 V and its inverted output signal S13b is output.
(4) In response to the 1-bit bit information signal B4, the differential driver 14A, like the differential driver 12A, for example, a bipolar binary output signal S14a having a signal voltage level of ± 2 V and its inverted output signal S14b is output.
(5) In response to the 1-bit bit information signal B5, the differential driver 15A has a bipolar binary output signal S15a having a signal voltage level of, for example, ± 1.1 V, which is slightly different from the signal voltage level of the differential driver 11A. And its inverted output signal S15b.
(6) The differential driver 16A responds to the 1-bit bit information signal B6, and a bipolar binary output signal S16a having a signal voltage level of, for example, ± 2.2 V, which is slightly different from the signal voltage level of the differential driver 12A. And its inverted output signal S16b.

  In FIG. 9, the output signal S11a, the output signal S12a, the inverted output signal S15b, and the inverted output signal S15b are combined and then transmitted to the signal line 31. The inverted output signal S11b, the inverted output signal S12b, the output signal S13a, and the output signal S14a are combined and then transmitted to the signal line 32. Further, the inverted output signal S13b, the inverted output signal S14b, the output signal S15a, and the output signal S16a are combined and then transmitted to the signal line 33.

  12 and 13 show bit information signals B1-B6 transmitted in the multiple differential transmission system of FIG. 9, and termination voltages V1, V2, V3 generated by the termination resistors 41, 42, 43 of the signal receiver 20A. It is a figure which shows the relationship.

The decoding processor 25 has a built-in table memory 25a in which the information tables of FIGS. 12 and 13 are stored in advance. The decoding processor 25 refers to the table in the table memory 25b and based on the termination voltages V1, V2, and V3 input from the A / D converters 21, 22, and 23, the 6-bit bit information signal B1. -B6 is judged and bit information signals B1-B6 of the judgment result are outputted. In the determination of the bit information in the decoding processor 25, the input termination voltages V1 to V6 are within a range of ± 10% of the termination voltage values in FIGS. 12 and 13, for example (this error range is the differential driver). 11 and 12 and the differential driver 13 is determined in accordance with the difference in signal voltage level.

As described above, according to the present embodiment, when the output signals and the inverted output signals are transmitted by being superimposed on the three signal lines 31, 32, 33 by the differential driver 11A-16A, the adjacent signals are adjacent to each other. The termination voltages V1, V2, and V3 appearing at the termination resistors 41, 42, and 43 connected to the signal line all have different voltage values depending on the ²⁶ states of the 6-bit bit information signal, and combinations of the termination voltage values. Thus, the original bit information signals B1-B6 can be decoded based on the termination voltages V1, V2, V3 detected by the A / D converters 21, 22, 23. In addition, the voltage applied to each signal line 31, 32, 33 of the signal transmission path 30 is 0 in total in any bit information transmission, and noise radiated from each signal line 31, 32, 33 is mutually mutually. Since they cancel each other, transmission with less noise is possible as in the normal differential transmission method.

In the second embodiment, the signal voltage level of each differential driver 11A-16A is not limited to the above value, and may be any of the following conditions.
(1) The signal voltage levels of the differential drivers 12A and 14A may be set to be different from the signal voltage levels of the differential drivers 11A and 13A by a predetermined first differential voltage ΔVd1.
(2) The signal voltage level of the differential driver 15A may be set to differ from the signal voltage levels of the differential drivers 11A and 13A by a predetermined second differential voltage ΔVd2 (where ΔVd2 <ΔVd1).
(3) The signal voltage level of the differential driver 16A may be set so as to differ from the signal voltage level of the differential drivers 12A and 14A by a predetermined third differential voltage ΔVd3 (where ΔVd2 <ΔVd3 <ΔVd1). Good.

Also preferably,
(1) The signal voltage levels of the differential drivers 12A and 14A may be set to be higher than the signal voltage levels of the differential drivers 11A and 13A by a predetermined first differential voltage ΔVd1.
(2) The signal voltage level of the differential driver 15A may be set to be higher than the signal voltage levels of the differential drivers 11A and 13A by a predetermined second differential voltage ΔVd2 (where ΔVd2 <ΔVd1). .
(3) The signal voltage level of the differential driver 16A is set to be higher than the signal voltage level of the differential drivers 12A and 14A by a predetermined third differential voltage ΔVd3 (where ΔVd2 <ΔVd3 <ΔVd1). Also good.

In the second embodiment,
(1) Signal voltage level of differential drivers 11A and 13A = ± 1;
(2) Signal voltage level of differential drivers 12A and 14A = ± 2;
(3) Signal voltage level of the differential driver 15A = ± 1.1;
(4) Signal voltage level of the differential driver 16A = ± 2.2;
For example,
(1) Signal voltage level of differential drivers 11A and 13A = ± 1;
(2) Signal voltage level of differential drivers 12A and 14A = ± 3;
(3) Signal voltage level of the differential driver 15A = ± 1.1;
(4) Signal voltage level of differential driver 16A = ± 3.3;
Or
(1) Signal voltage level of differential drivers 11A and 13A = ± 2;
(2) Signal voltage level of differential drivers 12A and 14A = ± 3;
(3) Signal voltage level of differential driver 15A = ± 2.2;
(4) Signal voltage level of differential driver 16A = ± 3.3;
It may be.

  As described above in detail, according to the multiple differential transmission system according to the present invention, a 6-bit bit information signal can be differentially transmitted using three signal lines, while suppressing an increase in noise, and Thus, differential transmission of a multi-bit bit information signal is possible with fewer wires compared to the prior art. In particular, the multiplex differential transmission system according to the present invention can be used as a multi-bit data transmission for a display for realizing a higher image quality than a conventional technique, and a high-speed transmission system in a device that needs to be downsized. It is.

It is a block diagram which shows the structure of the multiple differential transmission system which concerns on the 1st Embodiment of this invention. FIG. 2 is a waveform diagram showing a relationship between signal waveforms of output signals S11a, S11b, S12a, and S12b of the differential drivers 11 and 12 of FIG. It is a wave form diagram which shows the relationship between the signal waveform of output signal S13a of the differential driver 13 of FIG. 1, and the definition of the polarity of a current direction or a signal voltage, and the bit information allocated. It is a figure which shows the relationship between bit information signal B1, B2 input in the differential driver 13 of FIG. 1, and output signal S11a, S11b. It is a figure which shows the relationship between the bit information signals B3 and B4 input in the differential driver 14 of FIG. 1, and output signal S12a, S12b. It is a figure which shows the relationship between the bit information signals B5 and B6 input in the differential driver 15 of FIG. 1, and output signal S13a, S13b. A first relationship between bit information signals B1-B6 transmitted in the multiple differential transmission system of FIG. 1 and termination voltages V1, V2, V3 generated by termination resistors 41, 42, 43 of the signal receiver 20 is shown. It is a figure which shows a part. A second relationship between the bit information signals B1-B6 transmitted in the multiplex differential transmission system of FIG. 1 and the termination voltages V1, V2, V3 generated by the termination resistors 41, 42, 43 of the signal receiver 20 is shown. It is a figure which shows a part. It is a block diagram which shows the structure of the multiple differential transmission system which concerns on the 2nd Embodiment of this invention. FIG. 10 is a waveform diagram showing the relationship between the signal waveforms of the output signals S11a, S11b, S12a, S12b, S13a, S13b, S14a, and S14b of the differential drivers 11A, 12A, 13A, and 14A of FIG. FIG. 10 is a waveform diagram showing a relationship between signal waveforms of output signals S15a, S15b, S16a, and S16b of the differential drivers 15A and 16A of FIG. 9 and assigned bit information. The first relationship between the bit information signals B1-B6 transmitted in the multiple differential transmission system of FIG. 9 and the termination voltages V1, V2, V3 generated by the termination resistors 41, 42, 43 of the signal receiver 20A. It is a figure which shows a part. The second relationship between the bit information signals B1-B6 transmitted in the multiple differential transmission system of FIG. 9 and the termination voltages V1, V2, V3 generated by the termination resistors 41, 42, 43 of the signal receiver 20A. It is a figure which shows a part.

Explanation of symbols

10, 10A ... Signal transmitter,
11, 12, 13, 14, 15, 16, 11A, 12A, 13A, 14A, 15A, 16A ... differential drivers,
20, 20A ... signal receiver,
21, 22, 23 ... A / D converter,
24. Clock recovery circuit,
25. Decoding processor,
25a, 25b ... Table memory,
30: Signal transmission path,
31, 32, 33 ... signal lines,
41, 42, 43 ... Terminating resistors.

Claims (3)

A multiple differential transmission system comprising: a signal transmitter; a signal receiver; and a signal transmission path including first, second, and third signal lines connecting the signal transmitter and the signal receiver. In the signal transmitter for
Responsive to the 2-bit first bit information signal, a first output signal having a predetermined first signal voltage level and an inverted first output signal that is a phase inverted signal of the first output signal are generated. A first differential driver;
In response to a 2-bit second bit information signal, a second output signal having the first signal voltage level and an inverted second output signal that is a phase inverted signal of the second output signal are generated. Two differential drivers;
A third output signal having a second signal voltage level different from the first signal voltage level in response to a third bit information signal of 2 bits, and an inverted signal that is a phase inverted signal of the third output signal A third differential driver for generating a second output signal;
The first output signal and the inverted third output signal are combined and then transmitted to the first signal line,
The second output signal and the inverted first output signal are combined and then transmitted to the second signal line,
The signal transmitter, wherein the third output signal and the inverted second output signal are combined and then transmitted to the third signal line. A signal receiver for receiving three output signals received from a signal transmitter according to claim 1 via a signal transmission path composed of first, second and third signal lines,
A first termination resistor connected between the first signal line and the second signal line;
A second termination resistor connected between the second signal line and the third signal line;
A third termination resistor connected between the third signal line and the first signal line;
A first termination voltage generated by the first termination resistor, a second termination voltage generated by the second termination resistor, and a third termination voltage generated by the third termination resistor; And a decoding processing means for decoding and outputting the first, second and third bit information signals. A signal transmitter according to claim 1;
A multiple differential transmission system comprising the signal receiver according to claim 2.

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