JP2007317814A - Semiconductor integrated circuit using standard cell and its design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which prevents gate breakdown in the design of the semiconductor integrated circuit using a standard cell, and to provide its design method. <P>SOLUTION: When a vacant area exists in the standard cell, there are prepared two types of the standard cell which comprises a diode not connected to an input terminal and the standard cell which does not comprise the diode. First, the semiconductor integrated circuit is designed by using the standard cell which does not comprise the diode, the standard cell near the standard cell which outputs an antenna error as a result of the verification of the antenna error is replaced with the standard cell which comprises the diode, and the diode is connected to the input terminal of the standard cell which outputs the antenna error. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit formed by arranging and wiring standard cells and a design method thereof.

In the manufacturing process of a semiconductor integrated circuit, electrostatic discharge (ESD: electrostatic)
(discharge) may occur. For example, when a dry etching process using plasma is performed in a metal wiring process, ESD is generated by charging a gate of a transistor or a metal wiring connected to the gate by plasma irradiation. This phenomenon is called the antenna effect. In the case where there is a path connecting the portion where the charge is charged and the drain or source diffusion region, the charge is dissipated into the diffusion region. However, when there is no low resistance path for releasing charge, the charge passes through the gate oxide film which is a dielectric, and there is a possibility that the gate is broken or the oxide film is altered.

  In order to protect the transistor from damage due to such ESD, the antenna rule is applied to the layout pattern so that the magnitude of the electric charge charged to the gate or the metal wiring connected to the gate is within the allowable voltage tolerance of the gate. Is provided. The antenna rule is set using, for example, the ratio of the area of the conductive layer where charges are accumulated and the area of the gate oxide film.

  However, there may be a portion that does not satisfy the antenna rule in the layout design process. This is called an antenna error. In a transistor in which an antenna error has occurred, there is a high possibility of gate breakdown due to ESD. As a countermeasure against such an antenna error, there is a method in which an antenna diode is inserted into the layout, and charges that cause gate breakdown are dissipated to the diffusion region via the diode.

  In designing a semiconductor integrated circuit, a plurality of standard cells that realize various logic functions included in a standard cell library are combined based on a predetermined rule, rather than constructing the entire circuit at once. The method is common.

  Usually, the standard cell has an input terminal of at least one standard cell, and can receive signals from other standard cells or external sources. At the time of designing the standard cell, it is unknown what the input terminal of the standard cell is finally connected to. Therefore, it is impossible to determine in advance in which part of the layout the antenna diode is necessary. Therefore, by connecting an antenna diode to the input terminal of each standard cell, it is ensured that gate breakdown due to ESD does not occur in the manufacturing process of the semiconductor integrated circuit.

  Patent Documents 1 and 2 are listed as prior arts related to the present invention.

  In Patent Document 1, a semiconductor integrated circuit is designed using a standard cell library having a holder for a diode arrangement space related to the standard cell input, and it is determined whether or not there is a possibility that the standard cell is charged. When it is confirmed that there is a possibility that electric charge will be charged, a method for realizing a semiconductor device is proposed in which gate destruction can be avoided by replacing the diode placement space holder related to the standard cell input with a diode. ing.

Patent Document 2 discloses a method for realizing a semiconductor device that includes a protection diode cell for antenna countermeasures as a library and arranges a diode cell in a vacant area of a layout after designing a semiconductor integrated circuit, thereby preventing gate breakdown. Proposed.
Japanese Patent Laid-Open No. 10-144895 JP 2000-106419 A

  Adding a diode to each standard cell input has drawbacks. The first is that the input capacity of the standard cell is increased. As a result of the increase in the input capacitance, the operation speed is reduced and the current consumption is increased. The increase in the current consumption also causes an increase in power consumption. Second, it is not always possible to cope with an antenna error depending on an empty area in the standard cell. If the empty area in the standard cell is so small that a diode cannot be provided, the charge accumulated in the standard cell input (gate electrode) cannot be distributed and the means for avoiding gate breakdown is lost. If the standard cell is expanded to insert a diode, new problems such as an increase in the area of the semiconductor integrated circuit occur.

  In addition, the method of newly providing a space for diode placement at all standard cell inputs that may be damaged by ESD, as proposed in Patent Document 1, may also increase the area of the semiconductor integrated circuit. There is sex.

  Furthermore, the method of providing the antenna countermeasure protection diode cell as a library as proposed in Patent Document 2 also has a drawback. That is, when the spread ratio of standard cells is high, the area of the semiconductor integrated circuit is increased due to the insertion of the diode cells.

  In order to solve the above-described problems, the present invention uses an empty area in a standard cell in the design of a semiconductor integrated circuit using a standard cell, and inserts a standard cell having a diode as necessary. An object of the present invention is to provide a semiconductor integrated circuit capable of preventing gate breakdown without increasing the capacity, without increasing the area of the semiconductor integrated circuit, and when the standard cell coverage is high and the diode cell cannot be inserted. To do.

  In the implementation of the present invention, when there is an empty area in the standard cell, two types are prepared: a standard cell having a diode not connected to an input terminal and a standard cell having no diode. First, a semiconductor integrated circuit is designed with a standard cell that does not include a diode. As a result of antenna error verification, a standard cell near the standard cell that has generated an antenna error is replaced with a standard cell that includes a diode. Connect to the input terminal of the standard cell where the error occurred.

  According to the semiconductor integrated circuit based on the present invention, a diode that is not connected to the input terminal in an empty area in the standard cell, and by connecting the diode to the input terminal of another standard cell in which an antenna error has occurred, Gate breakdown due to ESD can be avoided without an increase in extra input capacitance or area.

  This is also effective when there is not enough free space in the standard cell where an antenna error has occurred and a diode cannot be provided, or when the standard cell has a high coverage ratio and a diode cell cannot be inserted.

  In addition, according to the semiconductor integrated circuit design method based on the present invention, only when an antenna error occurs, a standard cell without a diode is simply replaced with a standard cell with a diode, so that an excess input capacitance and area can be obtained. Gate breakage can be avoided without increasing.

  Embodiments of the present invention will be described below.

(Embodiment 1)
A first embodiment of a semiconductor integrated circuit using a standard cell and an invention of a design method thereof will be described with reference to the drawings. In the drawing, a dotted line (cell frame 8 in FIG. 1) represents a standard cell region. However, the dotted line in the horizontal direction represents the boundary between Pch on the VDD side and Nch on the VSS side.

  First, the configuration of each of a plurality of types of standard cells used in the present embodiment will be described.

  FIG. 1 is a diagram showing the configuration of the standard cell 1A. In the standard cell 1A, the gate electrode 1 and the P-type diffusion region 3 constitute a Pch transistor, and the gate electrode 1 and the N-type diffusion region 5 constitute an Nch transistor. In addition, a diode 7 is arranged in an empty area of the Nch transistor formation area. The gate electrode 1 corresponds to the input terminal of the standard cell 1A.

  FIG. 2 is a diagram showing the configuration of the standard cell 2A. The standard cell 2A differs from the standard cell 1A only in that no diode is provided in the standard cell.

  FIG. 3 is a diagram illustrating the configuration of the standard cell 1B. In the standard cell 1B, a Pch transistor is configured by the gate electrode 2 and the P-type diffusion region 4, and an Nch transistor is configured by the gate electrode 2 and the N-type diffusion region 6. The gate electrode 2 is connected to the wiring 9. The gate electrode 2 corresponds to the input terminal of the standard cell 1B.

  The standard cell 2A has a vacant area in the Nch transistor formation area, but such a cell having a vacant area in one of the channels is common.

  Next, a block layout using the standard cell and a design method thereof will be described.

  FIG. 5 is a diagram showing a design flow of the block layout in the present embodiment.

  Step 1 is a process for designing a standard cell. Here, in addition to the standard cell such as the standard cell 2A shown in FIG. 2, the present invention includes a diode 7 that is not connected to the input terminal in an empty area in the standard cell such as the standard cell 1A shown in FIG. Design characteristic standard cells. In addition to the two types of standard cells, it goes without saying that other standard cells such as the standard cell 1B shown in FIG. These designed standard cells are registered in the standard cell library.

  Step 2 is a process of placing and wiring standard cells. Placement and wiring using standard cells included in the standard cell library, which is necessary for designing a predetermined block layout, is performed. At this stage, the standard cell 1A having a diode therein is not used, and the standard cell 2A having no diode is used. This is because it is not possible to know where the antenna error is detected in the block layout unless the layout is actually performed. A block layout as shown in FIG. 6 is formed using the standard cell 2A and the standard cell 1B. However, in the drawing showing the block layout composed of each standard cell and a plurality of standard cells of the present invention, only the diffusion region and the gate are shown, and the wiring connecting the diffusion region to VDD and VSS, and between each standard cell are shown. The wiring to be connected is omitted for simplicity.

  Step 3 is a process of performing antenna error verification on the block layout configured in Step 2. At this stage, when an antenna error occurs in any of the standard cells included in the block layout, it is detected. If an antenna error is detected in any of the standard cells, the block layout is changed in the next step. If no antenna error is detected, the block layout is not changed. In this example, it is assumed that an antenna error is detected in the standard cell 1B in the block layout shown in FIG.

  Step 4 is a step of replacing a standard cell near the standard cell in which an antenna error is detected. At this stage, in the block layout as shown in FIG. 6, the standard cell 2A in the vicinity of the standard cell 1B in which the antenna error is detected is replaced with a standard cell 1A having an internal diode. Furthermore, the block layout as shown in FIG. 4 is formed by connecting the diode of the standard cell 1A to the gate electrode 2 of the standard cell 1B in which the antenna error is detected.

  Regarding the block layout change by the antenna error detection described in steps 3 and 4 above, the block layout composed of the standard cells 2A and 1B shown in FIG. 6 and the block layout composed of the standard cells 1A and 1B shown in FIG. This will be described in detail below.

  In the block layout shown in FIG. 6, the wiring 9 is formed after the P-type diffusion region 4, the N-type diffusion region 6 and the gate electrode 2 in the manufacturing process. Therefore, charges due to the antenna effect are charged to the wiring 9. If the amount of charge charged in the wiring 9 exceeds the allowable voltage range of the gate electrode 2 connected to the wiring 9, the gate electrode 2 may be destroyed.

  Therefore, antenna error verification is performed on the configured block layout, and when an antenna error is detected in any of the standard cells constituting the block (step 3), the standard cell 2A not including the diode is removed from the layout. The standard cell 1A having the diode 7 is arranged at the same position. Further, the diode 7 provided in the standard cell 1A is connected to the gate electrode 2 (step 4). With this replacement arrangement, the block layout shown in FIG. 4 is formed.

  By dissipating the charge charged in the wiring 9 of the standard cell 1B to the N-type diffusion region 33 of the standard cell 1A via the diode 7, it is possible to avoid the destruction of the gate electrode 2 connected to the wiring 9 become.

  In order to replace the standard cell 1A and the standard cell 2A as described above, the standard cell 2A needs to have the same logic, the same cell height, the same cell width, and the same pin shape as the standard cell 1A. is there. The standard cell 2A shown in FIG. 2 differs from the standard cell 1A only in that no diode is provided therein, and most of the configuration, such as other elements and cell sizes, is the same as the standard cell 1A. Since the sizes are the same, there is no change in the density of the block layout due to the replacement of the standard cell 2A with the standard cell 1A, and other standard cells need not be rearranged. Further, since the logic is the same, the function as the block layout is not altered by the replacement. Therefore, when an antenna error is detected in the standard cell 1B, destruction of the gate electrode 2 can be avoided by an easy means of replacing the standard cell 1A and the standard cell 2A.

  In addition, as in the block layout shown in FIG. 8, the same effect can be obtained by using the standard cell 4A in which the gate electrode and the diode are horizontally reversed as in the standard cell 1A.

  FIG. 8 is a diagram showing a part of a block layout designed using standard cells 1A, 1B, 3B, and 4A in the present embodiment. In the standard cell 3B, a Pch transistor is configured by the gate electrode 16 and the P-type diffusion region 19, and an Nch transistor is configured by the gate electrode 16 and the N-type diffusion region 20. The gate electrode 16 is connected to the wiring 18. The standard cell 4A has the same logic, the same cell height, the same cell width, and the same pin shape as the standard cell 1A of FIG. The condition of the same logic includes a configuration in which the gate electrode and the diode in the standard cell are arranged horizontally reversed. This is because the logic does not change even if the arrangement of the elements is reversed, and the same function can be realized as a standard cell. Further, replacement with the standard cell 2A having the same cell height and the same cell width is easy. The gate electrodes 16 and 17 correspond to the input terminals of the standard cells 3B and 4A, respectively.

  In the block layout shown in FIG. 8, the wiring 18 is formed after the P-type diffusion region 19, the N-type diffusion region 20 and the gate electrode 16 in the manufacturing process. When there is a possibility that the gate electrode 16 is destroyed by the electric charge charged in the wiring 18, the diode 15 provided in the standard cell 4A is connected to the gate electrode 16 of the standard cell 3B, whereby the gate electrode 16 is destroyed. Can be avoided. Similarly, when there is a possibility that the gate electrode 2 is destroyed by the electric charge charged in the wiring 9, the gate electrode 2 is connected by connecting the diode 7 provided in the standard cell 1A to the gate electrode 2 of the standard cell 1B. The destruction of 2 can be avoided.

  As described above, in the design of a semiconductor integrated circuit using standard cells, it is a problem of the prior art by using a free area in the standard cell and inserting a standard cell with a diode as necessary. Increasing the extra input capacity by adding diodes to each standard cell, providing space for placing diodes in the standard cells, and increasing the area by inserting diode cells in the layout, and spreading the standard cells It becomes possible to eliminate the inability to avoid gate destruction due to the high rate.

  In the present invention, when an antenna error is detected, only replacement necessary for avoiding gate destruction of the standard cell in which the antenna error is detected is performed. For example, in FIG. 7, a standard cell 1A with a diode 7 is arranged on the left side of the standard cell 1B, and a standard cell 2A without a diode is arranged on the right side. It is clear from the description of the present embodiment described above that. Here, only one standard cell 2A is replaced with the standard cell 1A because the charge charged in the standard cell 1B can be dissipated to the diffusion region by connecting one diode 7 to the gate electrode 2. It was because it was a large size.

  In this way, the standard cell 1A including the diode is disposed only in a necessary portion in the vicinity of the standard cell 1B, and the standard cell 2A including no other diode is disposed, so that an extra diode is provided as the entire block. Including standard cells can be avoided. Since a standard cell with a diode has an input capacity that is greater than when a diode is not provided, it is possible to prevent an unnecessary increase in input capacity as a whole block as compared with a conventional configuration in which each standard cell has a diode.

(Embodiment 2)
Hereinafter, a second embodiment of the invention of a semiconductor integrated circuit using standard cells will be described with reference to the drawings. The contents described in the first embodiment are omitted.

  FIG. 9 is a diagram showing a block layout of standard cells designed using the standard cells 1A, 1B, 3A, and 2B in the present embodiment. The standard cell 3A has the same logic, the same cell height, the same cell width, and the same pin shape as the standard cell 1A, and most of the configuration is the same as the standard cell 1A, but the standard cell 1A is a diode. 7 and the standard cell 3A differs from the diode 7 only in that a diode 10 having a different diffusion region shape is provided. In the standard cell 2B, a Pch transistor is configured by the gate electrode 11 and the P-type diffusion region 13, and an Nch transistor is configured by the gate electrode 11 and the N-type diffusion region 14. The gate electrode 11 is connected to the wiring 12. The gate electrode 11 corresponds to the input terminal of the standard cell 2B.

  In the block layout shown in FIG. 9, the wiring 12 is formed after the P-type diffusion region 13, the N-type diffusion region 14 and the gate electrode 11 in the manufacturing process. When there is a possibility that the gate electrode 11 is destroyed by the electric charge charged in the wiring 12, the diode 10 provided in the standard cell 3A is connected to the gate electrode 11 of the standard cell 2B, whereby the gate electrode 11 is destroyed. Can be avoided. Similarly, when there is a possibility that the gate electrode 2 is destroyed by the electric charge charged in the wiring 9, the gate electrode 2 is connected by connecting the diode 7 provided in the standard cell 1A to the gate electrode 2 of the standard cell 1B. The destruction of 2 can be avoided.

  In FIG. 9, the diffusion region of the diode 10 is larger than the diffusion region of the diode 7. In this case, the diode 10 can release a larger charge to the diffusion region than the diode 7. That is, in the block layout of FIG. 9, when the amount of charge that can be charged to the electrode 12 of the standard cell 2B exceeds the amount of charge that can be dissipated by the diode 7, not the standard cell 1A but the larger diffusion region. By disposing the standard cell 3A including the diode 10, it is possible to avoid the breakdown of the gate electrode 12.

  In this manner, by disposing standard cells having different diffusion region shapes in accordance with the magnitude of charges charged in the gate electrode, it is possible to appropriately avoid the destruction of the gate electrode due to ESD.

(Embodiment 3)
Hereinafter, a third embodiment of the invention of a semiconductor integrated circuit using standard cells will be described with reference to the drawings. The contents described in the first and second embodiments are omitted.

  FIG. 10 is a diagram showing a part of a block layout designed using standard cells 1A, 4B, and 4A in the present embodiment. In the standard cell 4B, the gate electrode 22 and the P-type diffusion region 24 constitute a Pch transistor, and the gate electrode 22 and the N-type diffusion region 25 constitute an Nch transistor. The gate electrode 22 is connected to the wiring 23. The gate electrode 17 corresponds to the input terminal of the standard cell 4A.

  In the block layout shown in FIG. 10, the wiring 23 is formed after the P-type diffusion region 24, the N-type diffusion region 25 and the gate electrode 22 in the manufacturing process. When there is a possibility that the gate electrode 22 is destroyed by the electric charge charged in the wiring 23, the diode 7 provided in the standard cell 1A and the diode 15 provided in the standard cell 4A are connected to the gate electrode 22. The gate electrode 22 can be prevented from being broken by distributing the electric charge to the diode 7 and the diode 15.

  In FIG. 10, two diodes 7 and 15 are connected to the gate electrode 22. In this case, a larger charge can be released to the diffusion region than when only the diode 7 is connected. That is, in the block layout of FIG. 10, when the amount of charge that can be charged to the electrode 22 of the standard cell 4B exceeds the amount of charge that can be dissipated by the diode 7, the standard cell 4A is added to the standard cell 1A. This arrangement makes it possible to avoid the destruction of the gate electrode 22.

  As described above, by disposing a plurality of standard cells including diodes in accordance with the magnitude of the charge charged in the gate electrode, it is possible to appropriately avoid the destruction of the gate electrode due to ESD.

  Similar effects can be obtained by a configuration in which a new diode 21 is formed by connecting the diode 7 and the diode 15 and connected to the gate electrode 2 as in the block layout shown in FIG. Further, in the block layout shown in FIG. 11, the standard cell 1A not adjacent to the standard cell 1B is connected to the diode 7 provided in the standard cell 1A and the diode 15 provided in the standard cell 4A, so that the charge charged in the gate electrode 2 is reduced. It can be used for dissipation.

(Embodiment 4)
Hereinafter, a fourth embodiment of the invention of a semiconductor integrated circuit using standard cells will be described with reference to the drawings. The contents described in the first to third embodiments will be omitted.

  FIG. 12 is a diagram showing a part of a block layout designed using standard cells 1A, 1B, and 2B in the present embodiment.

  In the block layout shown in FIG. 12, the wiring 9 is formed after the P-type diffusion region 4, the N-type diffusion region 6 and the gate electrode 2 in the manufacturing process. Similarly, the wiring 12 is formed after the P-type diffusion region 13, the N-type diffusion region 14 and the gate electrode 11. In the case where the gate electrode 2 may be destroyed by the electric charge charged in the wiring 9 and the gate electrode 11 may be destroyed by the electric charge charged in the wiring 12, the diode 7 provided in the standard cell 1A is used. By connecting the gate electrode 2 and the gate electrode 11 and distributing the charge to the diode 7, the gate electrode 2 and the gate electrode 11 can be prevented from being broken.

  In FIG. 12, the diode 7 is connected to both the gate electrode 2 and the gate electrode 11. In this case, the diode 7 releases both the charge charged in the gate electrode 2 and the charge charged in the gate electrode 11 to the diffusion region. That is, in the block layout of FIG. 12, when the total amount of charges charged in the gate electrode 2 and the gate electrode 11 is smaller than the amount of charges that can be dissipated by the diode 7, one gate electrode is provided for each gate electrode. By connecting the diode, the gate electrode can be prevented from being destroyed.

  In this way, by connecting one diode to a plurality of standard cells according to the magnitude of the charge charged to the gate electrode, it becomes possible to avoid the destruction of the gate electrodes of the plurality of standard cells.

  Further, the number of standard cells having diodes used in the entire block layout can be reduced as compared with the method of inserting standard cells having diodes for each standard cell in which an antenna error is detected. Since the input capacity of the standard cell increases by the amount of the diode arranged in the standard cell, the input capacity of the standard cell as a whole block layout can be reduced by reducing the number of standard cells with diodes by the configuration of this embodiment. It becomes possible to suppress.

(Embodiment 5)
Hereinafter, a fifth embodiment of the invention of a semiconductor integrated circuit using standard cells will be described with reference to the drawings. The contents described in Embodiments 1 to 4 will be omitted.

  FIG. 13 is a diagram showing a part of a block layout designed using standard cells 1A, 5A, and 1B in the present embodiment. The standard cell 5A has a configuration in which the arrangement of elements is inverted from that of the standard cell 1A on the Pch and Nch sides, and a diode 26 is arranged in a vacant area of the Pch transistor formation area. Similarly to the other standard cells, the gate electrode 28 and the P-type diffusion region 34 constitute a Pch transistor, and the gate electrode 28 and the N-type diffusion region 35 constitute an Nch transistor. The gate electrode 28 corresponds to the input terminal of the standard cell 5A.

  In the block layout shown in FIG. 13, the wiring 9 is formed after the P-type diffusion region 4, the N-type diffusion region 6 and the gate electrode 2 in the manufacturing process. When there is a possibility that the gate electrode 2 is destroyed by the electric charge charged in the wiring 9, the diode 7 provided in the standard cell 1A is connected to the diode 26 provided in the standard cell 5A. By forming a simple diode 27 and connecting it to the gate electrode 2, it is possible to avoid the breakdown of the gate electrode 2 by distributing the charge to the diode 7 and the diode 26.

  In addition, if the process is further miniaturized, a standard cell with a diode on the Nch side and a standard cell with a diode on the Pch side will surely avoid transistor failures due to plasma effects such as dry etching in the manufacturing process. It is more desirable to adopt the configuration of the present embodiment in which both are arranged.

  The above first to fifth embodiments are merely examples, and it is needless to say that the embodiments of the present invention are not limited to the above-described embodiments.

  For example, as shown in FIG. 14, the diode can be arranged not only in the standard cell but also in the memory, and can be widely used. In FIG. 14, when an antenna error is detected in a standard cell constituting the logic unit 32 in the semiconductor integrated circuit 29, the diode 31 provided in the memory unit 30 is replaced with the diode 31 in the logic unit 32 in which the antenna error is detected. By connecting to the gate of the standard cell, gate breakdown in the standard cell is avoided. As described above, it is possible to avoid gate breakdown by connecting diodes not only between standard cells provided in the same block layout but also between different blocks.

  In this embodiment, a standard cell including a diode and a standard cell including a gate electrode that may be destroyed are adjacent to each other, but it is not always necessary to be adjacent.

  The present invention relates to a semiconductor integrated circuit, and is useful for a layout structure of a semiconductor integrated circuit using standard cells and a design method thereof.

Schematic diagram of standard cell 1A layout characteristic of the present invention Schematic diagram of standard cell 2A layout Schematic diagram of layout of standard cell 1B Schematic diagram of block layout in the first embodiment (1) Design flowchart of the first embodiment Schematic diagram of block layout in the middle of design in the first embodiment Schematic diagram of block layout in the first embodiment (2) Schematic diagram of the block layout in the first embodiment of the present invention (3) Schematic diagram of the block layout in the second embodiment of the present invention Schematic diagram of a block layout in the third embodiment of the present invention (1) Schematic diagram (2) of the block layout in the third embodiment of the present invention Schematic diagram of the block layout in the fourth embodiment of the present invention Schematic diagram of the block layout in the fifth embodiment of the present invention Schematic diagram of memory layout in a semiconductor integrated circuit

Explanation of symbols

1, 2, 11, 16, 17, 22, 28 Gate electrode 3, 4, 13, 19, 24, 34 P-type diffusion region 5, 6, 14, 20, 25, 33, 35 N-type diffusion region 7, 10 , 15, 21, 26, 27, 31 Diode 8 Cell frame 9, 12, 18, 23 Wiring 29 Semiconductor integrated circuit 30 Memory 32 Logic unit

Claims (11)

In a semiconductor integrated circuit in which a logic circuit is configured by a plurality of standard cells, the plurality of standard cells include a first standard cell including a first diode, and the first diode is the first standard cell. A semiconductor integrated circuit, wherein the first diode is connected to at least one of the plurality of standard cells other than the first standard cell. 2. The semiconductor integrated circuit according to claim 1, further comprising a standard cell having the same logic, the same cell height, and the same width as the first standard cell, and not including the first diode. The plurality of standard cells further includes a second standard cell including a second diode, and the second diode is not connected to an input terminal of the second standard cell;
2. The semiconductor integrated circuit according to claim 1, wherein the second diode is connected to at least one of the plurality of standard cells other than the second standard cell. 4. The semiconductor integrated circuit according to claim 3, wherein the second diode has a diffusion region shape different from that of the first diode. 4. The semiconductor integrated circuit according to claim 3, wherein the second diode is different from the first diode in an amount of charge that can be dissipated in the diffusion region. The first diode and the second diode are connected to the same standard cell other than the first standard cell and the second standard cell among the plurality of standard cells. The semiconductor integrated circuit according to claim 3. A third diode is configured by connecting the first diode and the second diode, and the third diode is configured such that, among the plurality of standard cells, the first standard cell and the second diode 6. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is connected to at least one other than the standard cell. 8. The semiconductor integrated circuit according to claim 7, wherein the first diode is provided in a Pch transistor formation region, and at least the second diode is provided in an Nch transistor formation region. A semiconductor integrated circuit comprising a memory in a part of a semiconductor integrated circuit, a diode provided in the memory, and the diode connected to other than the memory. A first standard cell having a first diode, and a second standard having the same logic, the same cell height and the same width as the first standard cell, and not having the first diode A method of designing a semiconductor integrated circuit performed using a plurality of standard cells including cells,
Arranging and wiring the plurality of standard cells including the second standard cell;
As a result of the antenna error verification, when an antenna error occurs, the second standard cell in the vicinity of the standard cell where the antenna error is detected is replaced with the first standard cell, and the first diode is A method for designing a semiconductor integrated circuit, comprising: connecting to a standard cell in which the antenna error is detected. A standard cell library comprising a standard cell having a diode, wherein the diode is not connected to an input terminal of the standard cell.

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