JP2007311507A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method capable of raising the yield of a semiconductor integrated circuit by preventing the peeling of a film in the outer periphery of a semiconductor substrate, concerning the semiconductor device manufacturing method for reducing a step between a circuit formation region and a non-circuit formation region by remaining a metallic film, which is deposited in forming wiring in the circuit formation region, in the non-circuit formation region of the semiconductor substrate. <P>SOLUTION: A positive resist film 24 is formed so as to cover the upper part of the metallic film 20, and to expose the metallic film 20 which is positioned in the outer periphery of the semiconductor substrate 11, in the metallic film 20 corresponding to the non-circuit formation region B. Then, a negative resist film 25 is formed on the metallic film 20 corresponding to the non-circuit formation region B so as to be superimposed on the positive resist film 24. Then, the metallic film 20 is etched by defining the exposed and developed positive resist film 24 as a mask. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device, and in particular, a metal film to be formed when wiring is formed in a circuit formation region is left in a non-circuit formation region of a semiconductor substrate, and the circuit formation region and the non-circuit formation region are separated. The present invention relates to a method for manufacturing a semiconductor device with a reduced level difference therebetween.

  In a conventional semiconductor device, a metal film formed when forming a wiring in a circuit formation region is left in the non-circuit formation region of the semiconductor substrate, and a step between the circuit formation region and the non-circuit formation region is formed. There are reduced semiconductor devices (see FIG. 26).

  FIG. 26 is a cross-sectional view of a conventional semiconductor device. In FIG. 26, I is a region where a plurality of semiconductor integrated circuits 104 are formed (hereinafter referred to as “circuit formation region I”), J is arranged so as to surround the circuit formation region I, and the semiconductor integrated circuit 104 is not formed. Regions (hereinafter referred to as “non-circuit formation regions J”) are shown.

  Referring to FIG. 26, a conventional semiconductor device 100 includes a semiconductor substrate 101, insulating films 102 and 103, a plurality of semiconductor integrated circuits 104, and a metal film 105.

  The semiconductor substrate 101 has a circuit formation region I in which a plurality of semiconductor integrated circuits 104 are formed, and a non-circuit formation region J that is disposed so as to surround the circuit formation region I and in which the semiconductor integrated circuit 104 is not formed. The insulating film 102 is provided so as to cover the semiconductor substrate 101 corresponding to the circuit formation region I and the non-circuit formation region J. The insulating film 103 is provided so as to cover the insulating film 102.

  The plurality of semiconductor integrated circuits 104 are provided on the semiconductor substrate 101 corresponding to the circuit formation region I. The semiconductor integrated circuit 104 includes a diffusion layer 106, insulating films 102 and 103, and wiring patterns 108 and 111. The diffusion layer 106 is provided on the semiconductor substrate 101. The insulating film 102 is provided so as to cover the semiconductor substrate 101 and part of the diffusion layer 106. The insulating film 102 has an opening 102 </ b> A that exposes a part of the diffusion layer 106. The wiring pattern 108 fills the opening 102 </ b> A and is provided over the insulating film 102. The wiring pattern 108 is electrically connected to the diffusion layer 106.

  The insulating film 103 is provided so as to cover the insulating film 102 and part of the wiring pattern 108. The insulating film 103 has an opening 103 </ b> A that exposes a part of the wiring pattern 108. The wiring pattern 111 fills the opening 103 </ b> A and is provided over the insulating film 103. The wiring pattern 111 is electrically connected to the wiring pattern 108. The wiring pattern 111 is electrically connected to the diffusion layer 106 through the wiring pattern 108.

  The metal film 105 is provided on the insulating film 102 corresponding to the non-circuit formation region J. The metal film 105 is a metal film formed when the wiring pattern 108 is formed.

  In this way, the metal film 105 is left in the non-circuit formation region J of the semiconductor substrate 101, and the step between the circuit formation region I and the non-circuit formation region J is reduced, thereby forming the circuit formation region I and the non-circuit formation. Film peeling between the region J can be prevented.

  27 to 32 are views showing a manufacturing process of a conventional semiconductor device. 27 to 32, the same components as those of the conventional semiconductor device 100 are denoted by the same reference numerals.

  First, in the step shown in FIG. 27, a diffusion layer 106 is formed on the semiconductor substrate 101, and then an insulating film 102 having an opening 102A is formed so as to cover the semiconductor substrate 101.

  Next, in a step shown in FIG. 28, a metal film 105 is formed so as to cover the insulating film 102 and fill the opening 102A. The metal film 105 is a film that is patterned into a wiring pattern 108 in the step shown in FIG. Next, in a step shown in FIG. 29, a positive resist film 113 having an opening 113A is formed on the metal film 105.

  Next, in the step shown in FIG. 30, the outer peripheral portion of the structure shown in FIG. 29 is fixed by the clamp 115 of the dry etching apparatus, and the metal film 105 is etched using the positive resist film 113 as a mask. As a result, the wiring pattern 108 is formed in the insulating film 102 corresponding to the circuit forming region I, and the metal film 105 remains on the insulating film 102 corresponding to the non-circuit forming region J. When the outer peripheral portion of the structure shown in FIG. 29 is fixed, the clamp 115 of the dry etching apparatus is in contact with the positive resist film 113.

  Next, in the step shown in FIG. 31, the positive resist film 113 is removed. Next, in a step shown in FIG. 32, an insulating film 103 having an opening 103A and a wiring pattern 111 are sequentially formed on the structure shown in FIG. Note that before the insulating film 103 is formed, the structure illustrated in FIG. 31 is cleaned as a pretreatment.

Thereby, a plurality of semiconductor integrated circuits 104 are formed in the circuit formation region I, and the semiconductor device 100 including the plurality of semiconductor integrated circuits 104 is manufactured (for example, refer to Patent Document 1).
JP-A-2-142115

  However, when a positive resist film 113 with low mechanical strength is used as a mask for dry etching, the positive resist film 113 in a portion in contact with the clamp 115 of the dry etching apparatus is peeled off, and the yield of the semiconductor integrated circuit 104 is increased. There was a problem of being lowered. Specifically, for example, the peeled positive resist film 113 adheres to the metal film 105 exposed in the opening 113A, and the metal film 105 remains so as to connect the wiring patterns 108 after etching the metal film 105. In this case, a short circuit occurs between the wiring patterns 108, and the yield of the semiconductor integrated circuit 104 decreases.

  FIG. 33 is a plan view of the structure shown in FIG. In FIG. 33, W1 is the width (hereinafter referred to as “width W1”) of the metal film 105 etched using the normally exposed positive resist film 113 as a mask, and W2 is a positive film exposed in an out-of-focus state. The width (hereinafter referred to as “width W2”) of the metal film 105 etched using the mold resist film 113 as a mask is shown. In FIG. 33, K indicates a region where the metal film 105 having the width W2 is formed (hereinafter referred to as “region K”).

  Further, since the outer peripheral portion of the semiconductor substrate 101 has a round shape, when the positive resist film 113 is exposed, it is difficult to focus on the outer peripheral portion of the semiconductor substrate 101, and the width of the positive resist film 113 after development is small. Narrow. For this reason, as shown in FIG. 33, the width W2 of the metal film 105 corresponding to the region K becomes narrow (width W2 <width W1), and the portion corresponding to the region K in the cleaning process immediately before forming the insulating film 103. The metal film 105 is peeled off, and the yield of the semiconductor integrated circuit 104 is lowered.

  Therefore, the present invention has been made in view of the above points, and provides a method of manufacturing a semiconductor device that can prevent film peeling at the outer peripheral portion of a semiconductor substrate and improve the yield of a semiconductor integrated circuit. With the goal.

  According to one aspect of the present invention, a circuit formation region (A) where a semiconductor integrated circuit (14) is formed, and the semiconductor integrated circuit (14) are formed so as to surround the circuit formation region (A). A method of manufacturing a semiconductor device (40), wherein the semiconductor integrated circuit (14) is formed on a semiconductor substrate (11) having a non-circuit forming region (B) that is not formed, wherein the semiconductor integrated circuit (14) is provided on the semiconductor substrate (11). A positive resist forming step of forming a positive resist film (24) so as to cover the workpiece (20) corresponding to the circuit formation region (A) of the workpiece (20), and the non-circuit A negative resist film forming step of forming a negative resist film (43) on the workpiece (20) corresponding to the formation region (B) so as to overlap the positive resist film (24); Type resist film (24) Light, after development, as the positive resist film mask (24), the method of manufacturing a semiconductor device which comprises an etching step of etching a workpiece (20) (40) is provided.

  According to the present invention, in the etching process for etching the workpiece (20), the clamp (31) of the etching apparatus is in contact with the negative resist film (43) having a high mechanical strength. The mold resist film (24) and the clamp (31) do not come into contact with each other. As a result, it is possible to prevent film peeling of the positive resist film (24), so that the yield of the semiconductor integrated circuit (14) can be improved.

  According to another aspect of the present invention, a circuit forming region (A) in which a semiconductor integrated circuit (14) is formed and a circuit forming region (A) are disposed so as to surround the semiconductor integrated circuit (14). A method of manufacturing a semiconductor device (10), wherein the semiconductor integrated circuit (14) is formed on a semiconductor substrate (11) having a non-circuit formation region (B) that is not formed, and is provided on the semiconductor substrate (11). The work piece (20) which covers the work piece (20) and is located on the outer periphery of the semiconductor substrate (11) among the work piece (20) corresponding to the non-circuit formation region (B). And a positive resist film forming step for exposing the positive resist film on the workpiece (20) located on the outer peripheral portion of the semiconductor substrate (11). Negative so as to overlap (24) A negative resist film forming step for forming a resist film (25), and after exposing and developing the positive resist film (24), the workpiece (20) is formed using the positive resist film (24) as a mask. The manufacturing method of the semiconductor device (10) characterized by including the etching process of etching is provided.

  According to the present invention, in the etching process for etching the workpiece (20), the clamp (31) of the etching apparatus is in contact with the negative resist film (25) having a high mechanical strength. The mold resist film (24) and the clamp (31) do not come into contact with each other. As a result, it is possible to prevent film peeling of the positive resist film (24), so that the yield of the semiconductor integrated circuit (14) can be improved.

  In addition, the said reference code is a reference to the last, and this invention is not limited to the aspect of illustration by this.

  The present invention can prevent the peeling of the outer peripheral portion of the semiconductor substrate and improve the yield of the semiconductor integrated circuit.

  Next, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention. In FIG. 1, A is a region where a plurality of semiconductor integrated circuits 14 are formed (hereinafter referred to as “circuit formation region A”), and B is a region where a semiconductor integrated circuit 14 is not formed (hereinafter referred to as “non-circuit formation region B”). Respectively).

  Referring to FIG. 1, the semiconductor device 10 according to the first embodiment includes a semiconductor substrate 11, insulating films 12 and 13, a plurality of semiconductor integrated circuits 14, and a metal film 15.

  The semiconductor substrate 11 includes a circuit formation region A in which a plurality of semiconductor integrated circuits 14 are formed, and a circuit formation region B that is disposed so as to surround the circuit formation region A and in which the semiconductor integrated circuits 14 are not formed. For example, a silicon wafer can be used as the semiconductor substrate 11.

  The insulating film 12 is provided so as to cover the semiconductor substrate 11 corresponding to the circuit formation region A and the non-circuit formation region B. The insulating film 13 is provided so as to cover the insulating film 12. As the insulating films 12 and 13, for example, an oxide film can be used.

  A plurality of semiconductor integrated circuits 14 are provided on the semiconductor substrate 11 corresponding to the circuit formation region A. The semiconductor integrated circuit 14 includes diffusion layers 16 and 17, insulating films 12 and 13, and wiring patterns 18, 19, 21 and 22. The diffusion layers 16 and 17 are provided on the upper surface side of the semiconductor substrate 11. The insulating film 12 is provided so as to cover the semiconductor substrate 11 and part of the diffusion layers 16 and 17. The insulating film 12 has an opening 12 </ b> A that exposes a part of the diffusion layer 16 and an opening 12 </ b> B that exposes a part of the diffusion layer 17.

  The wiring pattern 18 fills the opening 12 </ b> A and is provided over the insulating film 12. The wiring pattern 18 is in contact with the diffusion layer 16. The wiring pattern 19 fills the opening 12 </ b> B and is provided over the insulating film 12. The wiring pattern 19 is in contact with the diffusion layer 17. As the material of the wiring patterns 18 and 19, a conductive metal can be used. Specifically, for example, Al can be used.

  The insulating film 13 is provided on the insulating film 12 so as to cover part of the wiring patterns 18 and 19. The insulating film 13 has an opening 13A that exposes a part of the wiring pattern 18 and an opening 13B that exposes a part of the wiring pattern 19. The wiring pattern 21 fills the opening 13 </ b> A and is provided over the insulating film 13. The wiring pattern 21 is in contact with the wiring pattern 18. The wiring pattern 21 is electrically connected to the diffusion layer 16 through the wiring pattern 18.

  The wiring pattern 22 fills the opening 13 </ b> B and is provided over the insulating film 13. The wiring pattern 22 is in contact with the wiring pattern 19. The wiring pattern 22 is electrically connected to the diffusion layer 17 via the wiring pattern 19. As a material of the wiring patterns 21 and 22, a conductive metal can be used, and specifically, for example, Al can be used.

  The metal film 15 is provided on the insulating film 12 corresponding to the non-circuit formation region B. The metal film 15 is a part of the metal film formed when the wiring patterns 18 and 19 are formed. The metal film 15 has an annular portion 15A and a plurality of protruding portions 15B (see FIG. 19). The annular portion 15 </ b> A is annular and is provided on the insulating film 12 located on the outer peripheral portion of the semiconductor substrate 11. The plurality of projecting portions 15B are provided integrally with the annular portion 15A. The plurality of projecting portions 15B are provided on the inner wall side of the annular portion 15A.

  According to the semiconductor device of the present embodiment, the metal film 15 having the annular portion 15A is provided on the insulating film 12 corresponding to the non-circuit formation region B, thereby comparing with the conventional metal film 105 (see FIG. 33). As a result, the metal film 15 is not easily peeled off, so that the yield of the semiconductor integrated circuit 14 can be improved. Also, by providing the annular portion 15A on the metal film 15, the step between the circuit formation region A and the non-circuit formation region B after the formation of the insulating film 13 on the metal film 15 can be reduced.

  2 to 14 are views showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. 15 is a plan view of the semiconductor substrate, and FIG. 16 is a plan view of the structure shown in FIG. 17 is a plan view of the structure shown in FIG. 7, FIG. 18 is a plan view of the structure shown in FIG. 11, and FIG. 19 is a plan view of the structure shown in FIG. . 2 to 19, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

  A manufacturing method of the semiconductor device 10 according to the first embodiment will be described with reference to FIGS. Further, in the present embodiment, the following description will be given by taking as an example the case where the metal film 15 is used as a workpiece.

  First, in the process shown in FIG. 2, a circuit formation region A in which a plurality of semiconductor integrated circuits 14 are formed, and a circuit formation region B that is disposed so as to surround the circuit formation region A and in which the semiconductor integrated circuits 14 are not formed. A semiconductor substrate 11 is prepared (see FIG. 15).

  Next, in the process shown in FIG. 3, diffusion layers 16 and 17 are formed on the upper surface side of the semiconductor substrate 11 by a well-known method, and subsequently, the semiconductor substrate 11 and a part of the diffusion layers 16 and 17 are covered. An insulating film 12 having openings 12A and 12B is formed. The opening 12A is formed so as to expose the diffusion layer 16, and the opening 12B is formed so as to expose the diffusion layer 17. As the insulating film 12, for example, an oxide film can be used.

  Next, in the step shown in FIG. 4, the metal film 20 that is a workpiece is formed so as to cover the insulating film 12 and fill the openings 12A and 12B. As the metal film 20, for example, an Al film can be used. The thickness M1 of the metal film 20 (the thickness of the metal film 20 formed on the insulating film 12) can be set to 0.5 μm, for example.

  The metal film 20 is a film that is etched into the metal film 15 and the wiring patterns 18 and 19 in the step shown in FIG.

  Next, in the step shown in FIG. 5, a positive resist film 24 is formed so as to cover the upper surface of the metal film 20. Specifically, for example, a positive resist film is dropped onto the metal film 20 while rotating the structure shown in FIG. 4 using a coater device (for example, the rotational speed is 3000 rpm). 24 is formed. At this time, a positive resist film 24 is also formed on the outer peripheral portion of the semiconductor substrate 11. When the thickness M1 of the metal film 20 is 0.5 μm, the thickness M2 of the positive resist film 24 can be set to 1.0 μm, for example.

  Next, in the step shown in FIG. 6, the positive resist film 24 formed in the non-circuit formation region B so as to expose the outer peripheral edge of the semiconductor substrate 11 and the metal film 20 formed on the outer peripheral portion of the semiconductor substrate 11. Is removed in an annular shape (see FIG. 16). Specifically, while rotating the structure shown in FIG. 5 (for example, the rotation speed is 1000 pm), a positive resist is applied by applying thinner to the outer periphery of the structure shown in FIG. 5 from below the structure shown in FIG. The membrane 24 is removed in an annular shape.

  6 and 16, C represents the removal width of the positive resist film 24 (hereinafter referred to as “removal width C”) when the outer periphery of the semiconductor substrate 11 is used as a reference. When the width of the non-circuit formation region B is 3 mm, the removal width C of the positive resist film 24 can be set to 0.5 mm, for example. 5 and 6 described above corresponds to a positive resist film forming step.

  Next, in the step shown in FIG. 7, a negative resist film 25 is formed in an annular shape on the metal film 20 corresponding to the non-circuit formation region B so as to overlap the positive resist film 24 disposed in the non-circuit formation region B. (Negative resist film forming step). At this time, the negative resist film 25 is formed so as to cover the outer periphery of the structure shown in FIG. 6 (see FIG. 17). Specifically, the negative resist solution is dropped onto the outer periphery of the structure shown in FIG. 6 while rotating the structure shown in FIG. 6 (for example, the rotation speed is 500 to 1000 rpm) using the coater device. Then, an annular negative resist film 25 is formed.

  The negative resist film 25 is a resist film having higher mechanical strength than the positive resist film 24. The thickness M3 of the negative resist film 25 on the positive resist film 24 can be set to 0.5 μm, for example. 7 and 17, D indicates the width of the negative resist film 25 (hereinafter referred to as “width D”) when the outer peripheral edge of the semiconductor substrate 11 is used as a reference. The width D of the negative resist film 25 is set to such a value that the clamp 31 (see FIG. 11) of the dry etching apparatus and the positive resist film 24 do not contact each other. The width D of the negative resist film 25 can be set to 2 mm, for example.

  Thus, by forming the annular negative resist film 25 so as to cover the outer peripheral portion of the structure shown in FIG. 6, in the etching step shown in FIG. Since the positive resist film 24 is not in contact with the weak positive resist film 24, it is possible to prevent the positive resist film 24 from being peeled off due to the contact with the clamp 31, thereby improving the yield of the semiconductor device 10. it can.

  Next, in the step shown in FIG. 8, the positive resist film 24 is exposed through the mask 27 having the opening 27A (exposure step). In FIG. 8, E indicates the exposed positive resist film 24 (hereinafter referred to as “exposure region E”).

  Next, in the process shown in FIG. 9, the negative resist film 25 is polymerized by irradiating light from the optical fiber 28 toward the negative resist film 25 (polymerization process). Thereby, since the negative resist film 25 is cured, the negative resist film 25 does not dissolve in the positive developer. This polymerization step may be performed as necessary and is not necessarily required.

  Next, in the process shown in FIG. 10, the positive resist film 24 is developed using a positive developer (development process). As a result, the portion of the positive resist film 24 corresponding to the exposure region E is dissolved, and an opening 24 A is formed in the positive resist film 24.

  Next, in the step shown in FIG. 11, the clamp 31 of the dry etching apparatus and the negative resist film 25 are brought into contact with each other to fix the outer peripheral portion of the structure shown in FIG. 10 (see FIG. 18), and then have an opening 24A. The metal film 20 is etched using the positive resist film 24 as a mask (etching process). As a result, the wiring patterns 18 and 19 are formed on the insulating film 12 corresponding to the circuit forming region A, and the metal film 15 having the annular portion 15A and the protruding portion 15B is formed on the insulating film 12 corresponding to the non-circuit forming region B. It is formed.

  Thus, the positive resist having a low mechanical strength is obtained by contacting the clamp 31 of the dry etching apparatus and the negative resist film 25 to fix the structure shown in FIG. 10 and etching the metal film 20. Since the film 24 and the clamp 31 are not in contact with each other, it is possible to prevent the positive resist film 24 from being peeled off, so that the yield of the semiconductor device 10 can be improved.

  Next, in the step shown in FIG. 12, the negative resist film 25 is removed, and then the structure shown in FIG. 12 is cleaned as a pretreatment for forming the insulating film 13. At this time, as described above, since the metal film 15 has an annular shape, the metal film 15 is hardly peeled off in the cleaning step shown in FIG. 12, so that the yield of the semiconductor device 10 can be improved.

  Next, in the process shown in FIG. 13, the insulating film 13 having openings 13 </ b> A and 13 </ b> B is formed on the insulating film 12 so as to cover the metal film 15 and part of the wiring patterns 18 and 19. As the insulating film 13, for example, an oxide film can be used.

  Next, in a process shown in FIG. 14, a wiring pattern 21 filling the opening 13A and over the insulating film 13 and a wiring pattern 22 filling the opening 13B and over the insulating film 13 are formed by a known method. Form at the same time. Thereby, a plurality of semiconductor integrated circuits 14 are formed on the semiconductor substrate 11 corresponding to the circuit formation region A, and the semiconductor device 10 having the plurality of semiconductor integrated circuits 14 is manufactured.

  According to the method of manufacturing a semiconductor device of the present embodiment, the metal film 20 that covers the metal film 20 and that is located on the outer periphery of the semiconductor substrate 11 is exposed from the metal film 20 corresponding to the non-circuit formation region B. After the positive resist film 24 is formed, a negative resist film 25 is formed on the metal film 20 corresponding to the non-circuit formation region B so as to overlap the positive resist film 24, and then exposure and development processing are performed. By etching the metal film 20 using the formed positive resist film 24 as a mask, the clamp 31 of the etching apparatus comes into contact with the negative resist film 25 having a high mechanical strength. Therefore, the positive resist film having a low mechanical strength is used. 24 and the clamp 31 will not contact. As a result, it is possible to prevent the positive resist film 24 from being peeled off during the etching process, and thus the yield of the semiconductor integrated circuit 14 can be improved.

  Note that this embodiment can also be applied to a semiconductor device including a semiconductor integrated circuit in which three or more wiring patterns are stacked. A semiconductor device including a semiconductor integrated circuit in which three or more wiring patterns are stacked is formed by a method similar to the steps shown in FIGS. 4 to 12 described above except for the wiring pattern provided in the uppermost layer. The uppermost wiring pattern can be manufactured by a method similar to that shown in FIG. Also in such a manufacturing method, the same effect as the manufacturing method of the semiconductor device 10 of the present embodiment can be obtained.

(Second Embodiment)
FIG. 20 is a sectional view of a semiconductor device according to the second embodiment of the present invention. In FIG. 20, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

  Referring to FIG. 20, the semiconductor device 10 according to the second embodiment is similar to the semiconductor device 10 except that a metal film 41 is provided instead of the metal film 15 provided in the semiconductor device 10 according to the first embodiment. It is configured in the same way.

  FIG. 21 is a diagram for explaining the shape of the metal film. In FIG. 21, the same components as those of the semiconductor device 40 of the present embodiment are denoted by the same reference numerals.

  Referring to FIG. 21, the metal film 41 is provided so as to cover the insulating film 12 corresponding to the non-circuit formation region B. The metal film 41 is a part of a metal film formed when the wiring patterns 18 and 19 are formed. The shape of the metal film 41 is annular.

  According to the semiconductor device of the present embodiment, by providing the annular metal film 41 on the insulating film 12 corresponding to the non-circuit formation region B, the metal film 41 is difficult to peel off. Yield can be improved. Further, by providing the annular metal film 41 on the insulating film 12, a step formed between the circuit forming region A and the non-circuit forming region B after the insulating film 13 is formed on the metal film 41 is formed. Can be small.

  22 to 25 are views showing manufacturing steps of the semiconductor device according to the second embodiment of the present invention. 22 to 25, the same components as those of the semiconductor device 40 according to the second embodiment are denoted by the same reference numerals.

  First, a process similar to the process shown in FIGS. 2 to 5 described in the first embodiment is performed to form the structure shown in FIG. Next, in the step shown in FIG. 22, the positive resist film 24 formed in the non-circuit formation region B so as to expose the outer peripheral edge of the semiconductor substrate 11 and the metal film 20 formed on the outer peripheral portion of the semiconductor substrate 11. Is removed in an annular shape. Specifically, while rotating the structure shown in FIG. 5 (for example, the rotation speed is 1000 pm), a thinner is applied from the upper side of the structure shown in FIG. 5 to the outer periphery of the structure shown in FIG. The resist film 24 is removed in an annular shape. In FIG. 22, F indicates the removal width of the positive resist film 24 (hereinafter referred to as “removal width F”) when the outer peripheral edge of the semiconductor substrate 11 is used as a reference. When the width of the non-circuit formation region B is 3 mm, the removal width F of the positive resist film 24 can be set to 2.5 mm, for example. In the present embodiment, the steps shown in FIGS. 5 and 22 correspond to a positive resist film forming step.

  Next, in a step shown in FIG. 23, an annular negative resist film 43 is formed so as to cover the metal film 20 and the positive resist film 24 corresponding to the non-circuit formation region B (negative resist film forming step). At this time, the negative resist film 43 is formed so as to cover the outer periphery of the structure shown in FIG. Specifically, using the coater apparatus, the negative resist solution is dropped onto the outer periphery of the structure shown in FIG. 22 while rotating the structure shown in FIG. 6 (for example, the rotation speed is 500 to 1000 rpm). An annular negative resist film 43 is formed.

  The negative resist film 43 is a resist film having higher mechanical strength than the positive resist film 24. The thickness M4 of the negative resist film 43 on the positive resist film 24 can be set to 0.5 μm, for example.

  Next, in the process shown in FIG. 24, an opening 24B is formed in the positive resist film 24 by performing the same process as the process shown in FIGS. 8 to 10 described in the first embodiment.

  Next, in the process shown in FIG. 25, the positive resist film having the opening 24B is obtained by bringing the clamp 31 of the dry etching apparatus and the negative resist film 43 into contact with each other and fixing the outer periphery of the structure shown in FIG. The metal film 20 is etched using 24 as a mask (etching process). As a result, the wiring patterns 18 and 19 are formed on the insulating film 12 corresponding to the circuit forming region A, and the metal film 41 is formed on the insulating film 12 corresponding to the non-circuit forming region B.

  In this way, the positive resist film having a low mechanical strength is obtained by contacting the clamp 31 of the dry etching apparatus and the negative resist film 43 to fix the structure shown in FIG. 24 and etching the metal film 20. 24 and the clamp 31 are not brought into contact with each other, so that the positive resist film 24 can be prevented from being peeled off, so that the yield of the semiconductor device 40 can be improved.

  Thereafter, the semiconductor device 40 shown in FIG. 20 is manufactured by performing the same process as the process shown in FIGS. 12 to 14 described in the first embodiment.

  Note that this embodiment can also be applied to a semiconductor device including a semiconductor integrated circuit in which three or more wiring patterns are stacked. In a semiconductor device including a semiconductor integrated circuit in which three or more wiring patterns are stacked, the wiring patterns other than the wiring pattern provided in the uppermost layer are described with reference to FIGS. 2 to 5, 22 to 25, and FIG. The uppermost wiring pattern can be manufactured by a method similar to the step shown in FIG. Also in such a manufacturing method, the same effect as the manufacturing method of the semiconductor device 40 of the present embodiment can be obtained.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

  The present invention provides a semiconductor device in which a metal film to be formed when a wiring is formed in a circuit formation region is left in the non-circuit formation region of the semiconductor substrate to reduce a step between the circuit formation region and the non-circuit formation region. Applicable.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment of the invention; FIG. 8 is a diagram (part 2) for illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention; It is FIG. (The 3) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 4 is a diagram (part 4) illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention; It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (The 8) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (10) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (11) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (12) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (13) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is the figure which planarly viewed the semiconductor substrate. It is the figure which planarly viewed the structure shown in FIG. It is the figure which planarly viewed the structure shown in FIG. It is the figure which planarly viewed the structure shown in FIG. It is the figure which planarly viewed the structure shown in FIG. It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure for demonstrating the shape of a metal film. It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (3) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (4) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing of the conventional semiconductor device. It is FIG. (1) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (2) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (3) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (4) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (5) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (6) which shows the manufacturing process of the conventional semiconductor device. It is the figure which planarly viewed the structure shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,40 Semiconductor device 11 Semiconductor substrate 12, 13 Insulating film 12A, 12B, 13A, 13B, 24A, 24B, 27A Opening 14 Semiconductor integrated circuit 15, 20, 41 Metal film 15A Annular part 15B Protrusion part 16, 17 Diffusion layer 18, 19, 21, 22 Wiring pattern 24 Positive resist film 25, 43 Negative resist film 27 Mask 28 Optical fiber 31 Clamp A Circuit formation area B Non-circuit formation area C, F Removal width D Width E Exposure area M1-M4 Thickness The

Claims (6)

A semiconductor device for forming a semiconductor integrated circuit on a semiconductor substrate having a circuit forming region where a semiconductor integrated circuit is formed and a non-circuit forming region which is disposed so as to surround the circuit forming region and where the semiconductor integrated circuit is not formed A manufacturing method comprising:
A positive resist forming step of forming a positive resist film so as to cover the workpiece corresponding to the circuit formation region among the workpieces provided on the semiconductor substrate;
A negative resist film forming step of forming a negative resist film on the workpiece corresponding to the non-circuit forming region so as to overlap the positive resist film;
And a step of etching the workpiece using the positive resist film as a mask after exposing and developing the positive resist film.   The method of manufacturing a semiconductor device according to claim 1, wherein the negative resist film is formed so as to continuously cover the workpiece corresponding to the non-circuit formation region.   3. A polymerization step for polymerizing the negative resist film is further provided between an exposure step for exposing the positive resist film and a development step for developing the positive resist film. The manufacturing method of the semiconductor device of description. A semiconductor device for forming a semiconductor integrated circuit on a semiconductor substrate having a circuit forming region where a semiconductor integrated circuit is formed and a non-circuit forming region which is disposed so as to surround the circuit forming region and where the semiconductor integrated circuit is not formed A manufacturing method comprising:
A positive type covering the workpiece provided on the semiconductor substrate and exposing the workpiece located on the outer periphery of the semiconductor substrate among the workpiece corresponding to the non-circuit forming region. A positive resist forming step of forming a resist film;
A negative resist film forming step of forming a negative resist film on the workpiece located on the outer periphery of the semiconductor substrate so as to overlap the positive resist film;
And a step of etching the workpiece using the positive resist film as a mask after exposing and developing the positive resist film.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the negative resist film is formed so as to continuously cover the workpiece located on an outer peripheral portion of the semiconductor substrate.   6. A polymerization process for polymerizing the negative resist film is further provided between an exposure process for exposing the positive resist film and a development process for developing the positive resist film. The manufacturing method of the semiconductor device of description.

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