JP2007234993A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which has an extension part made of an epitaxially grown layer and which has a short gate length. <P>SOLUTION: The method of manufacturing the semiconductor device has a process of forming a first gate 22 on a semiconductor substrate 1; a process of nitriding the surface of at least a first gate 22 to form a nitride film 24 for protecting the first gate; a process of selectively removing the nitride film 24 formed on the semiconductor substrate 1 in nitriding; and a process of forming the epitaxially grown layer on the semiconductor substrate 1 on both of the sides of the first gate 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an elevated source / drain extension structure.

High integration and high speed of transistors have been realized by miniaturization of transistors based on scaling rules. In order to suppress the short channel effect which has become a problem with the miniaturization of transistors, it is necessary to form source / drain and source / drain extensions (hereinafter simply referred to as extension portions) shallowly. Therefore, an elevated source / drain and an elevated source / drain extension structure using a selective epitaxial method doped with impurities (In situ doped Epi) have attracted attention (for example, see Patent Documents 1 and 2).
JP 2002-231942 A JP 2004-128314 A

  When the extension portion is formed by the selective epitaxial growth method, a protective film made of a nitride film is formed on the gate sidewall in order to prevent epitaxial growth starting from the polysilicon dummy gate sidewall. Although this nitride film is currently formed of a CVD film, a thickness of 6 nm is required to ensure the selectivity of epitaxial growth. The reason why the thickness of 6 nm is necessary is that, in the CVD process, a few nm at the initial stage of film formation is an unstable film, and thus it is difficult to ensure selectivity when the film is thin. As a result, the gate length becomes 12 nm longer than the original gate length, so there is a limit to miniaturization.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device having an extension portion made of an epitaxial growth layer and having a short gate length.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first gate on a semiconductor substrate, and nitriding at least a surface of the first gate, Forming a protective nitride film; selectively removing the nitride film formed on the semiconductor substrate in the nitriding process; and forming an epitaxial growth layer on the semiconductor substrate on both sides of the first gate. Forming.

  In the present invention, in order to prevent epitaxial growth starting from the first gate, a nitride film that protects the first gate is formed by nitriding treatment. In the nitriding process, a material for the surface of the first gate is consumed to form a nitride film. For this reason, when the first gate is used as a gate electrode, the final gate length is shorter than the original gate length of the first gate. Alternatively, when the second gate is formed later using the first gate as a dummy gate, an increase in the gate length of the second gate with respect to the gate length of the first gate is suppressed.

  According to the present invention, it is possible to manufacture a semiconductor device having an extension portion made of an epitaxially grown layer and having a short gate length.

  Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings. In this embodiment, an n-type MIS transistor will be described as an example with reference to the drawings. For the p-type MIS transistor, the following description is similarly applied by appropriately reversing the conductivity type.

  FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment.

  For example, a semiconductor substrate 1 made of a silicon substrate is formed with an element isolation insulating film 2 made of, for example, STI (Shallow Trench Isolation) that partitions an active region. In addition to Si, the material of the semiconductor substrate 1 may be SiGe or SiC. A p-type well 3 in which a channel inversion layer is formed is formed in an active region where the element isolation insulating film 2 is not formed.

  On the semiconductor substrate 1, two first epitaxial growth layers 6 serving as extension portions are formed with a predetermined distance therebetween. The first epitaxial growth layer 6 is a Si layer containing n-type impurities. When SiGe or SiC is used as the semiconductor substrate 1, the first epitaxial growth layer 6 is composed of a SiGe layer or a SiC layer containing an n-type impurity.

  Each first epitaxial growth layer 6 has an inclined end face on the opposite side. The angle and curvature of the inclined end face of the first epitaxial growth layer 6 affect the performance of the transistor. For this reason, the angle and curvature of the inclined end face of the first epitaxial growth layer 6 are optimized so as to maximize the drive current while suppressing the short channel effect. However, the first epitaxial growth layer 6 may not have an inclined end face.

  A gate electrode 5 is formed on the semiconductor substrate 1 between the two first epitaxial growth layers 6 via a gate insulating film 4. In this example, the gate electrode (second gate) 5 is formed so as to overlap the inclined end face of the first epitaxial growth layer 6. Since the gate electrode 5 overlaps the inclined end face of the first epitaxial growth layer 6, when the transistor is driven, a storage layer is formed in the extension portion constituted by the first epitaxial growth layer 6, and the channel is connected to the channel. The amount of carrier injection is greatly increased. However, a structure in which the gate electrode 5 does not overlap the first epitaxial growth layer 6 may be employed.

The gate insulating film 4 is made of, for example, a silicon oxide film or a high dielectric constant film such as an HfO ₂ film or an HfSiON film having a dielectric constant higher than that of the silicon oxide film. The gate electrode 5 is made of polysilicon or a metal material. As the metal material, for example, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, or W is used. In the case of pMOS, Fe, Co, Ni, Cu, Ru, Rh, Pd, Ag, Os, Ir, Pt, or Au is used as a metal material.

  A side surface of the gate electrode 5 is covered with a sidewall insulating film 7 formed on the first epitaxial growth layer 6. The sidewall insulating film 7 is formed of, for example, a silicon nitride film 7a and a silicon oxide film 7b.

  On the first epitaxial growth layer 6 not covered with the sidewall insulating film 7, a second epitaxial growth layer 8 serving as a source or drain is formed. The second epitaxial growth layer 8 is a Si layer containing n-type impurities. When SiGe or SiC is used as the semiconductor substrate 1, the second epitaxial growth layer 8 is composed of a SiGe layer or SiC layer containing an n-type impurity. However, the source / drain portions may be formed by ion-implanting impurities into the semiconductor substrate 1 without forming the second epitaxial growth layer 8. The sidewall insulating film 7 is provided to ensure a distance between the gate electrode 5 and the second epitaxial growth layer 8.

  A silicide layer 10 is formed on the surface of the second epitaxial growth layer 8. The silicide layer 10 is provided to reduce contact resistance. The silicide layer 10 is made of, for example, cobalt silicide or nickel silicide.

  An interlayer insulating film 12 is formed on the entire surface so as to cover the MIS transistor. Although not shown, a contact connected to the silicide layer 10 is embedded in the interlayer insulating film 12, and a wiring connected to the contact is formed on the interlayer insulating film 12.

  The semiconductor device according to the present embodiment employs a so-called elevated source / drain extension structure in which an extension portion is mainly configured by the first epitaxial growth layer 6 formed on the semiconductor substrate 1.

  Thereby, even when the impurities in the first epitaxial growth layer 6 are diffused in the substrate (in the p-type well 3), the effective junction depth of the extension portion with respect to the substrate surface can be reduced.

  As a result, the junction depth of the extension portion from the semiconductor substrate surface can be reduced in a state where the thickness of the extension portion is ensured, so that the short channel effect can be suppressed.

  Further, the drive current can be improved by controlling the overlap width of the gate electrode 5 with respect to the inclined end face of the first epitaxial growth layer 6 and the curvature and angle of the inclined end face of the first epitaxial growth layer 6.

  Next, a method for manufacturing the semiconductor device will be described with reference to FIGS.

  First, as shown in FIG. 2A, an element isolation insulating film 2 for element isolation is formed on a semiconductor substrate 1 by using, for example, an STI technique.

  Next, as shown in FIG. 2B, a p-type impurity such as boron is ion-implanted into the semiconductor substrate 1, and ion implantation for adjusting a threshold voltage is performed as necessary, and then activation annealing is performed. To form the p-type well 3.

  Next, as shown in FIG. 3A, a silicon oxide film 21a having a thickness of about 10 nm is formed on the semiconductor substrate 1 by, eg, thermal oxidation. The silicon oxide film 21a serves as an etching stopper for later gate processing, and is an example of the etching stopper film of the present invention. Subsequently, a polysilicon layer 22a having a thickness of about 150 nm is formed on the silicon oxide film 21a by, eg, CVD (Chemical Vapor Deposition). In order to prevent the deformation of the polysilicon layer 22a, which will be described later, during the processing, an annealing process is performed as necessary. Instead of the polysilicon layer 22a, an amorphous silicon layer or an amorphous silicon layer into which impurities are introduced may be formed.

  Next, as shown in FIG. 3B, a silicon nitride film is deposited on the polysilicon layer 22a by, for example, a CVD method, and the silicon nitride film is processed by a lithography technique and an etching technique to form a pattern corresponding to the gate electrode. The hard mask 23 is formed. The thickness of the hard mask 23 is, for example, 50 nm.

  Next, as shown in FIG. 4A, the dummy gate 22 is formed by dry etching the polysilicon layer 22a using the hard mask 23 as an etching mask. At that time, the silicon oxide film 21a serving as an etching stopper is left about 5 nm. The dummy gate 22 is an example of the first gate of the present invention.

Next, as shown in FIG. 4B, nitriding is performed. As the nitriding treatment, for example, plasma doping, plasma nitriding, tilt implantation, or the like is used. When plasma doping or plasma nitridation using an N ₂ / He gas system is used, the nitride film 24 is formed isotropically. The conditions for using plasma doping are, for example, RF power: 100 W to 400 W, process pressure: 0.013 to 13.3 Pa (0.1 to 100 mTorr), process gas: N ₂ / He mixed gas, substrate temperature: room temperature ˜500 ° C. If tilt implantation of 50 eV or less is possible by ultra-low energy ion implantation in ultra-high vacuum, nitrogen may be introduced into the gate sidewall by implantation.

For example, assume that a nitride film 24 having a thickness of 3 nm is formed. In this case, from the composition of Si ₃ N ₄ , the consumption of silicon is 1.28 nm, and the increase in the gate side wall is 3-1.28 = 1.72 nm. The gate length increase for both sides is 3.44 nm, which can be 4 nm or less. The composition of the nitride film 24 is SiN on the sidewalls of the dummy gate 22, but the composition of the nitride film 24 is close to that of SiON on the surface of the silicon oxide film 21a.

The introduced nitrogen and the polysilicon of the dummy gate 22 are reacted to perform annealing to form a stable Si ₃ N ₄ film. This annealing treatment is desired to be an extremely short time in order to stabilize the Si ₃ N ₄ film and suppress the diffusion of nitrogen. For this reason, high-temperature short-time annealing such as laser annealing or flash lamp annealing is used. Laser annealing conditions are, for example, laser wavelength: 308 nm to 1064 nm, irradiation energy: 0.5 to 1.5 J / cm ² , and substrate temperature: room temperature to 400 ° C.

  In the nitriding process, a nitride film 24 is also formed on the semiconductor substrate 1. For subsequent epitaxial growth, it is necessary to expose the clean surface of the semiconductor substrate 1, and thus the nitride film 24 on the semiconductor substrate 1 must be removed. For this reason, the nitride film 24 formed on the semiconductor substrate 1 is removed as shown in FIG. The nitride film 24 may be anisotropically etched or the nitride film 24 may be anisotropically oxidized. When the nitride film 24 is oxidized, it is removed together with the dummy gate insulating film 21 later.

For example, in removing the nitride film 24, the nitride film (SiON) on the semiconductor substrate 1 is oxidized by anisotropic RIE (Reactive Ion Etching) using O ₂ as a source gas. As a result, only the silicon oxide film 21 a remains on the semiconductor substrate 1. RIE conditions are, for example, RF power: 100 W to 400 W, process pressure: 0.013 to 13.3 Pa (0.1 to 100 mTorr), O ₂ flow rate: 80 sccm, and substrate temperature: room temperature.

Alternatively, oxidation may be promoted by high-temperature ashing after cutting Si—N bonds by anisotropic RIE using Ar as a source gas. The high temperature ashing is, for example, RF power: 100 W to 1000 W, process pressure: 13.3 to 1333 Pa (0.1 to 10 Torr), O ₂ flow rate: 200 sccm, and substrate temperature: 250 ° C.

  Next, as shown in FIG. 5B, the silicon oxide film 21a is removed using dilute hydrofluoric acid. Thereby, the silicon oxide film 21a becomes the dummy gate insulating film 21 of the gate pattern, and the clean surface of the semiconductor substrate 1 is exposed.

Next, as shown in FIG. 6A, a first epitaxial growth layer 6 made of a silicon-containing layer (Si, SiGe, SiC) mixed with impurities is formed on the semiconductor substrate 1 by an epitaxial growth method. In the case of nMOS, an n-type impurity such as arsenic is doped, and in the case of pMOS, a p-type impurity such as boron is doped. The thickness of the first epitaxial growth layer 6 serving as the extension portion is, for example, 40 to 50 nm. The impurity concentration at this time is, for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ .

  Since this epitaxial growth is performed by a low-temperature process of 800 ° C. or less, impurities introduced during the growth hardly diffuse into the semiconductor substrate 1 (p-type well 3). Therefore, the first epitaxial growth layer 6 and the p-type well 3 Can form a pn junction having a steep concentration gradient. Further, since the impurities are activated, it is not necessary to perform a heat treatment for activation in the subsequent steps, so that impurity diffusion into the semiconductor substrate 1 can be further suppressed. As a result, the short channel effect of the transistor can be suppressed while forming the low-resistance first epitaxial growth layer 6. However, impurities may be ion-implanted after the non-doped first epitaxial growth layer 6 is formed.

  An inclined end face is formed in the first epitaxial growth layer 6 on the dummy gate structure 20 side according to the growth conditions in the epitaxial growth. The angle (facet) formed by the inclined end surface with the substrate surface has a constant value in the range of 20 to 70 °. If this angle is too small, the parasitic resistance of the first epitaxial growth layer 6 will increase. If the angle is too large, the parasitic capacitance between the gate electrode and the first epitaxial growth layer 6 is increased, or the margin for overlapping the gate electrode and the inclined end surface is reduced as described later. For this reason, this angle is preferably controlled within the above range.

  Next, as shown in FIG. 6B, the nitride film 24 on the side walls of the dummy gate 22 is removed using heated phosphoric acid or the like.

  Next, as shown in FIG. 7A, after a silicon oxide film is deposited on the semiconductor substrate 1 by, for example, a CVD method so as to cover the dummy gate 22, anisotropic dry etching (etchback) is performed. By doing so, sidewall spacers 25 are formed on the sidewalls of the dummy gate 22. Since the sidewall spacer 25 is removed later, a material such as a silicon oxide film having a higher etching selectivity than the silicon nitride film 7a of the sidewall insulating film 7 to be formed later is used. The thickness of the sidewall spacer 25 is set to be thicker than that of the nitride film 24 because it defines a width in which the subsequent gate electrode overlaps the inclined end face of the first epitaxial growth layer 6. For example, the film thickness of the sidewall spacer 25 is set in the range of 4 to 6 nm.

  Next, as shown in FIG. 7B, after depositing a silicon nitride film 7a and a silicon oxide film 7b on the first epitaxial growth layer 6 so as to cover the dummy gate 22, abnormal dry etching (etchback) is performed. ), Sidewall insulating films 7 are formed on both side surfaces of the dummy gate 22 via the sidewall spacers 25. The silicon nitride film 7a is deposited with a film thickness of 20 nm, for example, and the silicon oxide film 7b is deposited with a film thickness of 50 nm, for example. The silicon nitride film 7a functions as an etching stopper when the sidewall spacer 25 is etched later.

  Next, as shown in FIG. 8A, a second epitaxial growth layer 8 made of a silicon-containing layer (Si, SiGe, SiC) in which impurities are selectively mixed is formed on the first epitaxial growth layer 6 by an epitaxial growth method. Form. In the case of nMOS, n-type impurities such as arsenic and phosphorus are doped, and in the case of pMOS, p-type impurities such as boron are doped. The thickness of the second epitaxial growth layer 8 serving as a source or drain is, for example, 20 to 40 nm.

  In the formation of the second epitaxial growth layer 8, after the silicon-containing layer not containing impurities is epitaxially grown, impurities may be ion-implanted into the silicon-containing layer. Alternatively, similar to the first epitaxial growth layer 6, impurities may be introduced during the epitaxial growth of the silicon-containing layer. Further, the source / drain may be formed in the semiconductor substrate 1 by ion implantation without forming the second epitaxial growth layer 8.

Next, as shown in FIG. 8B, a silicide layer 10 is formed on the surface of the second epitaxial growth layer 8. The silicide layer 10 is formed to reduce the resistance of the second epitaxial growth layer 8 serving as a source or drain, and is, for example, cobalt silicide (CoSi ₂ ) or nickel silicide (NiSi ₂ ). The silicide layer 10 is formed by forming a metal film made of cobalt or nickel and then heat-treating the second epitaxial growth layer 8 in contact with the metal film to form a silicide, and removing the unnecessary metal film by chemical treatment. To do.

  Next, as illustrated in FIG. 9A, a silicon oxide film is deposited on the silicide layer 10 and the dummy gate 22 by, for example, a plasma CVD method to form an interlayer insulating film 12.

  Next, as shown in FIG. 9B, the interlayer insulating film 12 is etched back until the hard mask 23 is exposed. At this time, the upper portion of the sidewall spacer 25 made of silicon oxide is also slightly etched.

  Next, as shown in FIG. 10A, the hard mask 23 made of silicon nitride which is difficult to be etched and the upper portion of the sidewall insulating film 7 are removed by CMP. After the CMP, the dummy gate 22 is exposed.

  Next, as shown in FIG. 10B, the exposed dummy gate 22 is removed by etching to form a gate opening 26. More specifically, the dummy gate 22 made of polysilicon is removed by wet etching with an alkaline solution such as a TMAH (tetramethylammonium hydroxide) aqueous solution or by dry etching.

  Next, as shown in FIG. 11A, the sidewall spacer 25 and the dummy gate insulating film 21 in the gate opening 26 are removed by wet etching using, for example, a solution containing hydrofluoric acid. As a result, the surface of the p-type well 3 is exposed on the bottom surface of the gate opening 26. Further, the inclined end face of the first epitaxial growth layer 6 is exposed at the bottom of the gate opening 26. At this time, the silicon nitride film 7a constituting the sidewall insulating film 7 functions as an etching stopper, and the exposed width of the inclined end face is controlled to be constant.

Next, as shown in FIG. 11B, the gate insulating film 4 is formed on the interlayer insulating film 12 so as to cover the inner wall of the gate opening 26. Subsequently, a gate electrode layer 5 a is formed on the gate insulating film 4 so as to fill the gate opening 26. In forming the gate insulating film 4, a high dielectric constant film such as an HfO ₂ film or an HfSiON film is formed by an ALD (Atomic Layer Deposition) method. By not using thermal oxidation in forming the gate insulating film 4, it is possible to prevent thermal diffusion of impurities in the first epitaxial growth layer 6. A metal layer containing Ti, V, Cr, Zr, Nb, Mo, Hf, Ta or W is formed as the gate electrode layer 5a. In the case of pMOS, a metal layer containing Fe, Co, Ni, Cu, Ru, Rh, Pd, Ag, Os, Ir, Pt or Au is formed as the gate electrode layer 5a.

  Next, the excess gate electrode layer 5a and the gate insulating film 4 on the interlayer insulating film 12 are removed by, eg, CMP. Thereby, the gate electrode 5 is formed in the gate opening 26 via the gate insulating film 4 (see FIG. 1). The gate electrode 5 is an example of the second gate of the present invention.

  As subsequent steps, after the interlayer insulating film 12 is stacked, contacts connected to the gate electrode 5 and the silicide layer 10 are formed, and an upper layer wiring is formed, thereby completing the semiconductor device.

  Next, the effect of the semiconductor device manufacturing method according to the present embodiment will be described.

  In this embodiment, in order to suppress the epitaxial growth starting from the side wall of the dummy gate 22, the nitride film 24 is formed as a side wall protective film of the dummy gate 22 by nitriding instead of the CVD method. The dummy gate length of the dummy gate 22 is L0 (see FIG. 4A), and the dummy gate length after the nitride film is formed is L1 (see FIG. 4B). Since the final gate length Lg (see FIG. 1) is longer than the dummy gate length L1, shortening the dummy gate L1 is suitable for miniaturization.

  Here, if the nitride film 24 is formed by the CVD method, it is necessary to form the nitride film 24 having a thickness of 6 nm or more in consideration of stability. In this case, the dummy gate length L1 is a dummy gate length. It is at least 12 nm longer than the length L0. For this reason, there is a limit to miniaturization.

  On the other hand, when the nitride film 24 is formed by nitriding, it is sufficient to form the nitride film 24 having a thickness of 3 nm or more even in consideration of stability. Further, as described above, the increase in the dummy gate length L1 with respect to the dummy gate length L0 is 4 nm or less. For this reason, it is suitable for miniaturization of the gate length Lg.

  In the above example, the example in which the dummy gate 22 is temporarily removed and the overlapped gate electrode 5 is formed has been described, but the dummy gate 22 may be used as it is as the gate electrode. In this case, the nitride film 24 is formed as a sidewall protective film of the dummy gate 22 by nitriding, so that the final gate length (corresponding to the gate length L2 in FIG. 6B) is the resolution limit of lithography. There is an advantage that it becomes shorter than the gate length L0 determined by.

  Further, when the nitride film 24 is formed as a sidewall protective film of the dummy gate 22, the nitride film 24 is also formed on the semiconductor substrate 1 due to isotropic nitridation (see FIG. 4B). When the surface of the semiconductor substrate 1 is nitrided, the surface of the semiconductor substrate 1 is damaged due to the introduction of nitrogen. As a result, the crystallinity of the epitaxial layer is deteriorated and transistor characteristics are deteriorated.

  In order to prevent this, in the present embodiment, the surface of the semiconductor substrate 1 is protected in the nitriding process by leaving the silicon oxide film 21a on the semiconductor substrate 1 when the dummy gate 22 is processed. When the silicon oxide film 21a on the semiconductor substrate 1 is removed, a clean surface of the semiconductor substrate 1 appears, so that the first epitaxial growth layer 6 with good crystallinity can be formed. Therefore, a semiconductor device with improved transistor characteristics can be manufactured.

  In order to secure the characteristics of the nitride film 24 as a protective film, it is necessary to form a stable nitride film by combining N and Si introduced in the nitriding process. Further, in order to prevent nitridation of the semiconductor substrate 1, it is necessary to prevent N diffusion. In the present embodiment, these requirements can be satisfied by performing high-temperature and short-time annealing.

The present invention is not limited to the description of the above embodiment. For example, the dummy gate 22 may be used as the gate electrode. Further, the first epitaxial growth layer 6 may not have an inclined surface. Further, the source / drain may be formed by ion implantation into the substrate without forming the source / drain by the second epitaxial growth layer 8.
In addition, various modifications can be made without departing from the scope of the present invention.

It is sectional drawing of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... P-type well, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... 1st epitaxial growth layer, 7 ... Side wall insulating film, 7a ... Silicon nitride film, 7b DESCRIPTION OF SYMBOLS ... Silicon oxide film, 8 ... 2nd epitaxial growth layer, 10 ... Silicide layer, 12 ... Interlayer insulation film, 21 ... Dummy gate insulation film, 21a ... Silicon oxide film, 22 ... Dummy gate, 22a ... Polysilicon layer, 23 ... Hard Mask: 24 ... Nitride film, 25 ... Side wall spacer, 26 ... Gate opening

Claims (4)

Forming a first gate on the semiconductor substrate;
Nitriding at least the surface of the first gate to form a nitride film that protects the first gate;
Selectively removing the nitride film formed on the semiconductor substrate in the nitriding treatment;
And a step of forming an epitaxial growth layer on the semiconductor substrate on both sides of the first gate. Before the step of forming the first gate, further comprising a step of forming an etching stopper film on the semiconductor substrate;
The semiconductor device according to claim 1, further comprising a step of removing the etching stopper film and exposing the semiconductor substrate after the step of selectively removing the nitride film and before the step of forming the epitaxial growth layer. Manufacturing method. The method for manufacturing a semiconductor device according to claim 2, wherein a silicon oxide film is formed as the etching stopper film. After the step of forming the epitaxial growth layer,
Removing the first gate and the nitride film;
The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a second gate overlapping the end of the epitaxial growth layer on the semiconductor substrate.

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