JP2007234223A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of supplying a voltage higher than a voltage supplied from the outside by a low power consumption to semiconductor circuits of a flash memory or the like, and also arranged so that the voltage supplied to the semiconductor circuit does not fluctuate even though the operating condition is changed over. <P>SOLUTION: The semiconductor integrated circuit device is provided with a boosting circuit 1, a level detection circuit 2, an internal voltage generation circuit 3, an address buffer (ADB) 4, an address decoder (RDC) 5, and a memory cell array (MCA) 6. The level detection circuit 2 is provided with a first level detection section 21 performing a level detection at a memory access and a second level detection section 22 performing a level detection at a standby. By generating a reference voltage Vref by utilizing a constant current source section 27 arranged in the second level detection section 22, the circuit can be simplified since individual installation of the contact current source section 27 becomes unnecessary. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device that drives a semiconductor circuit by boosting a power supply voltage supplied from the outside. For example, the present invention is directed to a flash memory that can erase stored data at once.

  Flash memory, a type of nonvolatile semiconductor memory, has a configuration in which EEPROM (Electrically Erasable Programmable Read Only Memory) cells that can electrically write and erase data are arranged in a matrix. .

  FIG. 25 is a diagram for explaining the structure of this type of nonvolatile semiconductor memory. Each memory cell in the chip is composed of a stack gate type transistor having a floating gate FG and a control gate CG. When electrons are injected into the floating gate FG shown in FIG. 25 or electrons are discharged from the floating gate FG, the threshold voltage changes. By using this change in threshold voltage, data writing to each memory cell and Reading is performed.

  More specifically, logic “1” and “0” are determined depending on whether or not a current flows when a power supply voltage is applied to the control gate CG of the memory cell to be read. The threshold voltage of the memory cell is about 2 V when the memory cell is “1” and 5 V or more when it is “0”.

  In the conventional flash memory, the power supply voltage supplied from the outside and the control gate voltage at the time of reading are both set to 5 V. Therefore, even if this power supply voltage is directly applied to the control gate CG at the time of reading, there is no particular problem in operation. There wasn't. On the other hand, recently, with the miniaturization of memory cells and the increase in memory capacity, it has become necessary to lower the power supply voltage supplied from the outside, and the setting of the external power supply voltage to 3 V is now becoming common. .

  When the power supply voltage is set to 5 V as in the prior art, the difference between the voltage VG applied to the control gate CG at the time of reading and the threshold voltage Vth when the memory cell is “1” is VG−Vth = 5 -2 = 3V. On the other hand, when the power supply voltage is 3V, VG−Vth = 3−2 = 1V, which is one third of the voltage when the power supply voltage is 5V. In the following, the cell current is also reduced accordingly. A decrease in cell current causes a decrease in reading speed and a margin for fluctuations in power supply voltage.

  For this reason, a method of generating an internal voltage Vccint by boosting an externally supplied 3V power supply voltage (hereinafter referred to as an external power supply voltage Vccext) inside the chip and applying the internal voltage Vccint to the control gate of the memory cell. Has been proposed. This internal voltage Vccint needs to be set to 5V even in the standby state in which reading and writing to the memory cell are not performed. If a voltage lower than 5V is set during standby, the standby state is switched to the memory access state. The voltage level of the internal voltage Vccint must start to increase from the point in time, and it takes time for the internal voltage Vccint to reach 5 V, during which time reading from the memory cell cannot be performed (see Patent Document 1).

As described above, it is necessary to set the internal voltage Vccint to the same voltage level in the standby state and the memory access state. However, a nonvolatile memory such as a flash memory is used for a portable device driven by a battery or a battery. It is often the case that power consumption during standby is as low as possible.
JP 7-14394 A

  The present invention has been made in view of such a point, and the object thereof can be supplied to a semiconductor circuit such as a flash memory with a lower power consumption than a voltage supplied from the outside. Another object of the present invention is to provide a semiconductor integrated circuit device in which the voltage supplied to the semiconductor circuit does not fluctuate even when the operating state is switched.

  According to one aspect of the present invention, in a semiconductor integrated circuit device including a booster circuit that boosts an externally supplied voltage, and a semiconductor circuit that is driven by a voltage corresponding to the boosted voltage boosted by the booster circuit The booster circuit includes a first charge pump and a second charge pump having a driving force weaker than that of the first charge pump, and the booster circuit has the first and second operating states. The circuit performs voltage control by the first charge pump so that the boosted voltage becomes the first voltage when the semiconductor circuit is in the first operation state, and the semiconductor circuit is in the second operation state. In this case, a semiconductor integrated circuit device is provided in which voltage control is performed by the second charge pump so that the boosted voltage becomes a second voltage different from the first voltage.

  According to the present invention, when the semiconductor circuit such as the flash memory enters the second operation state (for example, the standby state), the circuit for detecting the boosted voltage level is switched to the low power consumption type circuit. Even when a relatively high voltage is sometimes supplied to the semiconductor circuit, power consumption during standby can be reduced. Further, according to the present invention, since the voltage level supplied to the semiconductor circuit is not changed much even when the operation state is switched, the transition time when the operation state is switched can be shortened, and the access speed to the semiconductor circuit is improved. In addition, since the voltage supplied to the semiconductor circuit does not fluctuate temporarily immediately after the operating state is switched, the power consumption can be reduced and a constant voltage can be constantly supplied to the semiconductor circuit regardless of the operating state. Can do.

  Hereinafter, a semiconductor integrated circuit device and a memory device to which the present invention is applied will be specifically described with reference to the drawings.

  The semiconductor integrated circuit device and the storage device described below are intended to reduce the power consumption in the standby state for reading and writing to the memory cell array 6, and the power supply voltage for driving the memory cell array 6 It is characterized in that the power consumption can be suppressed without significantly reducing the level of.

[First Embodiment]
FIG. 1 is a schematic configuration diagram of an embodiment of a semiconductor integrated circuit device to which the present invention is applied, and shows an example including a memory cell array 6 having an EEPROM configuration (hereinafter simply referred to as a memory cell array 6). FIG. 1 shows a configuration from when an address signal is input to when a word line of the memory cell array 6 is selected.

  The semiconductor integrated circuit device according to this embodiment includes a booster circuit 1, a level detection circuit 2, an internal voltage generation circuit 3, an address buffer (ADB) 4, an address decoder (RDC) 5, and a memory cell array (MCA) 6. With.

  Among these, the booster circuit 1 boosts the external power supply voltage Vccext supplied from the outside to generate a boosted voltage Vccint2. The voltage value of the boost voltage Vccint2 is different between the memory access for reading / writing the memory cell array 6 and the standby time for not reading / writing. For example, Vccint2 = 6.5 V for memory access, Vccint2 = 5V is set.

  The level detection circuit 2 detects a fluctuation in the voltage level of the boost voltage Vccint2, and inputs the detection result to the boost circuit 1. The internal voltage generating circuit 3 generates a voltage (hereinafter referred to as an internal voltage) Vccint obtained by stepping down the boosted voltage Vccint2.

  Detailed configurations of the booster circuit 1, the level detection circuit 2, and the internal voltage generation circuit 3 will be described later.

  The address signal ADD input from outside the chip is input to the address decoder 5 via the address buffer 4 and decoded. The address decoder 5 is supplied with the external power supply voltage Vccext and the internal voltage Vccint stepped down by the internal voltage generation circuit 3, and the address decoder 5 performs voltage level conversion in addition to decoding. As a result, the address decoder 5 outputs a decode signal based on the internal voltage Vccint.

  The output of the address decoder 5 is supplied to a word line (not shown) of the memory cell array 6. The address decoder 5 shown in FIG. 1 decodes the row address of the memory cell array 6, and the decoder for decoding the column address is omitted in FIG.

  A stabilizing capacitor 7 of about several hundred pF is connected between the boosted voltage Vccint2 boosted by the booster circuit 1 and the ground terminal, and the address decoder 5 has a parasitic capacitance of about several hundred to several nF.

  Next, before describing each configuration shown in FIG. 1 in detail, the overall operation of the semiconductor integrated circuit device of the present embodiment will be described. In a memory access state in which reading / writing is performed with respect to the memory cell array 6, the booster circuit 1 outputs a boosted voltage Vccint2 of 6.5 V, for example, and the internal voltage generator 3 generates an internal voltage Vccint of 5V, for example, based on the boosted voltage Vccint2. . The internal voltage Vccint is used as a power supply voltage for driving the address decoder 5 and the like. The level detection circuit 2 detects a change in the voltage level of the boosted voltage Vccint2, and based on the detection result, the booster circuit 1 performs feedback control so that the boosted voltage Vccint2 becomes a constant level.

  As described above, the reason why the internal voltage Vccint2 is generated in addition to the boosted voltage Vccint2 is that if the boosted voltage Vccint2 is supplied as it is to all the circuits in the semiconductor integrated circuit, the boosted voltage Vccint2 causes voltage fluctuation because the load is large. This is because if the internal voltage Vccint is supplied to each circuit, the load of the boosted voltage Vccint2 is reduced correspondingly, and fluctuations in the voltage value can be suppressed.

  On the other hand, in a standby state waiting for reading / writing to the memory cell array 6, the booster circuit 1 outputs a boosted voltage Vccint2 of, for example, 5V, and the internal voltage generating circuit 3 has the same level as the boosted voltage Vccint2 (for example, 5V) internal voltage Vccint is output. The level detection circuit 2 is common to the memory access state in that it detects a change in the voltage level of the boosted voltage Vccint2, but it is switched to a circuit with low power consumption to reduce the power consumption during level detection as much as possible. And different. Further, the level detection circuit 2 is operated intermittently so that the voltage level of the boosted voltage Vccint2 does not become too high during the level detection.

  Next, the detailed configuration of the booster circuit 1 shown in FIG. 1 will be described. The booster circuit 1 includes a charge pump 11 whose circuit diagram is shown in FIG. 2, and an oscillator 12 whose circuit diagram is shown in FIG.

  As shown in FIG. 2, the charge pump 11 has diodes D1 to D4, capacitors C1 to C4, and inverters INV1 and INV2. The external power supply voltage Vccext is supplied to the first stage diode D1 and the inverter INV1 of the first stage. The output OSC of the oscillator 12 described later is input, and the boosted voltage Vccint2 is output from the diode D4 at the final stage.

  The charge pump 11 generates and outputs a voltage Vccint2 higher than the external power supply voltage Vccext by sequentially transferring charges corresponding to the output OSC from the oscillator 12 to each of the capacitors C1 to C4.

  As shown in FIG. 3, the oscillator 12 is configured such that a plurality of inverters INV3 to INV7 are connected in series, and the output of the inverter INV6 is fed back to the NAND gate G1 in the first stage. When the signal CPE input to the NAND gate G1 in FIG. 3 becomes high level, an oscillation operation is performed internally, and an oscillation signal is output from the output OSC. On the other hand, when the signal CPE becomes low level, the output OSC is fixed at low level. This signal CPE is output from a level detection circuit 2 described later.

  As described above, when the memory is accessed, the boosted voltage Vccint2 of, for example, 6.5 V is output from the charge pump 11 shown in FIG. From the standpoint of current consumption due to timing variation (address skew) between address signals and potential difference (voltage margin) with the internal voltage Vccint, the boosted voltage Vccint2 should be as high as possible. Considering the current consumption and transition time when transitioning to the state, the breakdown voltage of the semiconductor circuit, etc., the boosted voltage cannot be set too high. Actually, the voltage value of the boosted voltage Vccint2 is set in consideration of the various conditions described above.

  Next, the detailed configuration of the level detection circuit 2 shown in FIG. 1 will be described. FIG. 4 is a circuit diagram showing a detailed configuration of the level detection circuit 2. The level detection circuit 2 is divided into a first level detection unit 21 that performs level detection in the memory access state and a second level detection unit 22 that performs level detection in the standby state. The outputs of the level detectors 21 and 22 are added by the OR gate 23 and output. The output CPE of the OR gate 23 is input to the first stage of the oscillator 12 shown in FIG. That is, if the output CPE of the level detection circuit 2 is at a high level, the oscillator 12 in FIG. 3 performs an oscillation operation and the voltage level of the boosted voltage Vccint2 increases. On the other hand, if the output CPE of the level detection circuit 2 is at a low level, the oscillator 12 stops the oscillation operation, and the voltage level of the boosted voltage Vccint2 decreases. Further, the power consumption of the second level detection unit 22 is set to be less than half that of the first level detection unit 21, for example, less than ¼.

  The second level detection unit 22 shown in FIG. 4 includes a PMOS transistor 24, resistors R21 and R22, a low power consumption type differential amplifier (low power amplifier) 25, and an OR gate G21. The reference voltage Vref is input to the (+) input terminal of the power amplifier 25, and the voltage VG2 at the connection point between the resistors R21 and R22 is input to the (−) input terminal. The PMOS transistor 24 is turned on in the standby state, and when the PMOS transistor 24 is turned on, a voltage VG2 obtained by dividing the boosted voltage Vccint2 by the resistors R21 and R22 is input to the (−) input terminal of the low power amplifier 25. . When the voltage VG2 is lower than the reference voltage Vref, the output of the low power amplifier 25 becomes high level, and the output CPE of the level detection circuit 2 also becomes high level.

  An OR gate G21 is connected to the disable terminal of the low power amplifier 25, and the low power amplifier 25 is in a memory access state or when the output OSC of the oscillator 12 shown in FIG. 3 is at a high level. Becomes disabled and the output is fixed at a low level.

  On the other hand, the first level detection unit 21 is configured in the same manner as the second level detection unit 22 except that a normal differential amplifier 26 is connected instead of the low power amplifier 25, and the boost voltage Vccint2 When the voltage is 6.5 V, level detection is performed such that the divided voltage VG1 and the reference voltage Vref match.

  FIG. 5 is a circuit diagram showing a detailed configuration of a low power amplifier (Low Power AMP) 25 in the second level detector 22. The low power amplifier 25 shown in FIG. 5 is divided into a constant current source unit 27 configured by a Wilson current mirror circuit and a differential amplifier unit 28. The constant current source unit 27 has two stable points. When the power is turned on, the gate terminal of the illustrated PMOS transistor 29 is once set to a low level and then set to a high level. As a result, the voltage Vf at both ends of the diode D21 and the voltage VR at both ends of the resistor R23 coincide, and the current flowing through the diode D21 and the current flowing through the resistor R23 become equal. The voltage Vf across the diode D21 is about 0.6V, a high resistance of about 2400 kΩ is used for the resistor R23, and the current I flowing through the resistor R23 is expressed by I = Vf / R, and I = about 0.25 μA. It becomes.

  Thus, since almost no current flows through the resistor R23, the power consumed by the constant current source unit 27 is reduced, and the power consumption of the entire low power amplifier 25 is also kept low.

  However, if the power consumption of the low power amplifier 25 is kept low, there is a problem that level detection takes time, and the boosted voltage Vccint2 is several V higher than a predetermined voltage before the level detection ends. There is a risk.

  Here, when it takes time to detect the level, it is examined which is larger, that is, the rate at which the boost voltage Vccint2 increases or decreases. Factors that cause the boosted voltage Vccint2 to decrease include the current flowing through the resistors R21 and R22 shown in FIG. 4, the subthreshold current of the address decoder 5 connected to the internal voltage Vccint, and the junction leakage current. The current is less than several μA and is sufficiently small. Further, since the parasitic capacitance of the internal voltage Vccint is several hundred pF to several nF, it takes several microseconds to several hundred microseconds for the boosted voltage Vccint2 to drop by about 0.1V. On the other hand, when the output CPE of the level detection circuit 2 is at a high level, the degree of increase of the boost voltage Vccint2 depends on the power supply voltage and the size of the charge pump 11, but one cycle of the output OSC of the oscillator 12 shown in FIG. About 0.1 V per unit. Note that one cycle of the output OSC is about several tens of nanoseconds.

  As described above, the boosted voltage Vccint2 has a feature that the rise is steep and the drop is gradual, and if it takes time to detect the level, the boosted voltage Vccint2 may become a considerably high voltage. For this reason, when the second level detection unit 22 shown in FIG. 4 detects that the boosted voltage Vccint2 is 5 V or less, it operates the charge pump 11 in the booster circuit 1 for one cycle, and then boosts the voltage. When the pulse OSC is output from the oscillator 12 in the circuit 1, the low power amplifier 25 is reset to stop the operation of the charge pump 11.

  As shown in FIG. 4, when the low power amplifier 25 is reset by the pulse OSC from the oscillator 12 and the output CPE of the level detection circuit 2 is forcibly set to the low level, at least until the output CPE next becomes the high level. It takes a few microseconds. For this reason, as a result, the charge pump 11 operates at a rate of once every several μs to several hundreds of μs as the boosted voltage Vccint2 decreases, thereby preventing the boosted voltage Vccint2 from rising too much. Can do.

  Incidentally, the circuit for resetting the low power amplifier 25 is not limited to the one shown in FIG. For example, FIG. 6 shows an example in which a counter 111 that outputs logic “1” is provided when a predetermined number of pulses OSC are output from the oscillator 12, and the low power amplifier 25 is reset by the output of the counter 111.

  A plurality of charge pumps 11 may be connected in parallel so that only some of the charge pumps 11 are driven during standby, and the degree of increase in the boost voltage Vccint2 may be changed between standby and memory access.

  For example, FIG. 7 shows an example in which the booster circuit 1 is configured by connecting two charge pumps 11a and 11b in parallel. Each of the charge pumps 11a and 11b is configured by a circuit similar to that shown in FIG. 2, and the signals OSC 1 and OSC 2 that are out of phase with each other for noise reduction are input to the charge pumps 11a and 11b, respectively. An AND gate G22 is provided in the preceding stage of the charge pump 11b, and a signal OSC2 and a signal that goes to a high level during memory access are input to the input terminal of the AND gate G22.

  In the circuit of FIG. 7, the charge pump 11a operates during both memory access and standby, whereas the charge pump 11b operates only during memory access and does not operate during standby. As a result, the power (capacity) of the entire charge pump is lower than that of the memory access bus during standby, and the boosted voltage Vccint2 gradually increases.

  Next, the detailed configuration of the internal voltage generation circuit 3 shown in FIG. 1 will be described. FIG. 8 is a circuit diagram showing a detailed configuration of the internal voltage generation circuit 3. The internal voltage generation circuit 3 includes differential amplifiers 31 and 32, PMOS transistors Q31 to Q35, NMOS transistors Q36 to Q39, and resistors R31 and R32, and generates an internal voltage Vccint based on the boosted voltage Vccint2. To do.

  Each of the differential amplifiers 31 and 32 compares the voltage VG obtained by resistance-dividing the internal voltage Vccint with the reference voltage Vref, and outputs the comparison result. More specifically, the differential amplifier 31 performs control to increase the internal voltage Vccint when the internal voltage Vccint is lower than 5V, and the differential amplifier 32 decreases the internal voltage Vccint when the internal voltage Vccint is higher than 5V. Take control.

  The differential amplifiers 31 and 32 are both configured by the circuit of FIG. The PLUS terminal in FIG. 9 corresponds to the (+) input terminal shown in FIG. 8, and the MINUS terminal corresponds to the (−) input terminal. When the disable terminal in FIG. 9 is at a high level, the NMOS transistor Q301 is turned on and the output is fixed at a low level. On the other hand, when the disable terminal is at a low level, the PMOS transistor Q302 is turned on. When the PLUS terminal becomes higher than the MINUS terminal in this state, the current from the external power supply voltage Vccext flows into the PMOS transistor Q303 and the output is high. Become a level. Conversely, if the MINUS pin is at a higher potential than the PLUS pin when the disable pin is high, the output goes low.

  A PMOS transistor Q34 is connected to the output stage of the internal voltage generating circuit 3 shown in FIG. 8, and in the standby state, the transistor Q34 is turned on and the internal voltage Vccint is forcibly set to the boosted voltage Vccint2. That is, the PMOS transistor Q34 operates to short-circuit the internal voltage Vccint and the boosted voltage Vccint2 during standby.

  By such control, the internal voltage Vccint is set to about 5 V and the boosted voltage Vccint2 is set to about 6.5 V during memory access, and the internal voltage Vccint is set to the same potential (5 V) as the boosted voltage Vccint2 during standby.

  In the internal voltage generation circuit 3 and the level detection circuit 2 shown in FIG. 1, the signal STANDBYH obtained by level shifting the signal STANDBY indicating the standby state and the signal ENABLEH synchronized with the signal STANDBY are used. The signal is generated by a control signal generation circuit shown in FIG.

  In FIG. 10, the signal STANDBY that becomes high level in the standby state is input to the level shifter circuit 101 and subjected to level conversion, and the signal STANDBYH is output from the level shifter circuit 101. The signal STANDBY and the signal obtained by delaying the signal STANDBY by the delay circuit 102 are integrated by the AND gate G101, and then input to the level shifter circuit 103 to generate the signal ENABLEH.

  FIG. 11 is a circuit diagram showing a detailed configuration of the level shifter circuits 101 and 103 shown in FIG. When a high level signal is input to the input IN, the NMOS transistor Q101 is turned on, the point a shown in the figure becomes low level, the PMOS transistor Q102 is also turned on, and the output OUT becomes the same level as the power supply voltage Vhigh. When a low level signal is input to the input IN, the NMOS transistor Q103 is turned on and the output OUT becomes the ground level. Therefore, the input signal can be level-converted by setting a desired voltage value for the power supply voltage Vhigh.

  FIG. 12 is a circuit diagram showing a detailed configuration of the delay circuit 102 shown in FIG. The delay circuit 102 has a configuration in which a plurality of inverters INV11 to INV14 are connected in series, and capacitors C11 to C13 are connected between the output of each inverter and a ground terminal. A desired delay time can be obtained by changing the capacitance of the capacitor and the number of connection stages of the inverter.

  FIG. 13 is a waveform diagram showing the operation timing of the semiconductor integrated circuit device shown in FIG. 1. The signal STANDBY which goes high in the standby state, the signal ENABLE synchronized with the signal STANDBY, the boost voltage Vccint2 and the level The signal waveform with the output signal CPE of the detection circuit 2 is shown. The control signal ENABLE changes to high level at the time of transition to the memory access state, and changes to low level for a while after transitioning to the standby state. Thus, after a while from time T2 when the memory access state is switched to the standby state (time T3), the reason for setting the signal ENABLE to the low level is that the boost voltage Vccint2 is changed from 6.5 V to 5 V in the internal voltage generation circuit 3. This is because the time required for lowering is taken into consideration.

  That is, during the standby state, the boost voltage Vccint2 and the internal voltage Vccint are set to the same voltage (for example, 5V), and the signal CPE is intermittently set to the high level so that this voltage does not fluctuate. It is driven at a rate of once per microsecond to several hundred microseconds.

  On the other hand, when the memory access state is changed from the standby state, the boosted voltage Vccint2 needs to be raised from 5 V to 6.5 V. Therefore, as shown in FIG. 13, the oscillator 12 for a while after the memory access state (time T1) is reached. The output CPE is maintained at a high level and the charge pump 11 is continuously driven. When the boosted voltage Vccint2 becomes 6.5 V, the output CPE thereafter controls the output voltage Vccint2 so that the boosted voltage Vccint2 does not fluctuate from 6.5 V by outputting a pulse as the boosted voltage Vccint2 decreases.

  Incidentally, in the internal voltage generation circuit 3 shown in FIG. 8, the reference voltage Vref is used, and this reference voltage Vref is generated by the reference voltage generation circuit 30 whose detailed configuration is shown in FIG. 14 includes a differential amplifier 41, resistors R1, R2, and R3, diodes D11 and D12, and a PMOS transistor Q11. The differential amplifier 41 includes a constant current source. A constant current is supplied. The differential amplifier 41 controls the voltage VA at the connection point between the resistor R1 and the diode D11 to be equal to the voltage VB at the connection point between the resistors R2 and R3.

Therefore, the relationship of the formula (1) is established between the current I1 flowing through the resistor R1 and the current I2 flowing through the resistor R2.
I1 / I2 = R1 / R2 (1)

In general, when the current flowing through the diode is I, the (reverse direction) saturation current is Is, the forward voltage is VF, and the temperature is T, the relationship of equation (2) is established.
I = Is {eq.VF ^{/ kT-} 1} (2)

Since VF >> q / kT = 26 mV, (-1) in the equation (2) can be ignored, and the equation (3) is established.
I = Is · eq · ^{VF / kT} (3)

When formula (3) is transformed, formula (4) is obtained. However, VT = kT / q.
VF = (kT / q) · 1n (I / Is) (4)

If the forward voltages of the diodes D11 and D12 in FIG. 14 are VF1 and VF2, respectively, and the voltage across the resistor R3 is ΔV, the relationship of equation (5) is established.
ΔVF = VF1-VF2 = VT.1n (I1 / I2)
= VT · 1n (R2 / R1) (5)

From the equation (5), the reference voltage Vref is expressed by the equation (6).
Vref = VF1 + (R2 / R3) .DELTA.VF (6)

  Here, since the voltage VT has a positive temperature coefficient of 0.086 mV / ° C. and the forward voltage VF1 of the diode has a negative temperature coefficient of about −2 mV / ° C., the resistors R2, R3 If the resistance value is set, the reference voltage Vref is always a constant voltage value regardless of the temperature.

  In order to suppress the power consumption of the reference voltage generation circuit 30 of FIG. 14, the current may be narrowed down by a constant current source that supplies current to the reference voltage generation circuit 30. Although this constant current source may be provided exclusively for the reference voltage generating circuit, the constant current source unit 27 in the low power amplifier 25 of FIG. 5 can be used.

  For example, FIG. 15 is a diagram showing an example in which the low power consumption type constant current source unit 27 in the low power amplifier 25 shown in FIG. The one-dot chain line portion in FIG. 15 shows the configuration of the constant current source portion 27. The current output from the constant current source unit 27 is input to the differential amplifying unit 28 constituting the low power amplifier 25 and also input to the reference voltage generating circuit 30. The reference voltage generating circuit 30 outputs the reference voltage Vref. Is output.

  Thus, if the reference voltage Vref is generated using the constant current source unit 27 in the second level detection unit 22 shown in FIG. 4, it is not necessary to provide the constant current source unit 27 separately, and the circuit is simplified. Can be Further, since the constant current source unit 27 in the second level detection unit 22 has low power consumption, the power consumption of the entire reference voltage generation circuit 30 can be suppressed.

[Second Embodiment]
In the first embodiment, as shown in FIG. 8 during standby, the transistor Q34 in the internal voltage generation circuit 3 is turned on to forcibly short-circuit the internal voltage Vccint and the boosted voltage Vccint2.

  FIG. 16 is a block diagram showing a schematic configuration of output stages of the booster circuit 1 and the internal voltage generation circuit 3. The internal voltage generation circuit 3 includes an internal voltage generation unit 121 that reduces the boosted voltage Vccint2 to generate the internal voltage Vccint, and a switch circuit 122. The switch circuit 122 includes a PMOS transistor 123 and an inverter 124, and the PMOS transistor 123 is turned on / off according to the logic of a signal STANDBYH that becomes a high level during standby. More specifically, when the standby state is entered, the PMOS transistor 123 is turned on, the output terminals of the booster circuit 1 and the internal voltage generator 121 are short-circuited, and the boosted voltage Vccint2 and the internal voltage Vccint become equal.

  The internal voltage Vccint is a substantially constant voltage (about 5 V) regardless of the operation state of the memory, whereas the boosted voltage Vccint2 is about 6.5 V in the memory access state and about 5 V in the standby state. For this reason, as shown in FIGS. 8 and 16, when the output terminals of the booster circuit 101 and the internal voltage generator 103 are forcibly short-circuited at the time when the standby state is entered, immediately after the standby state is entered. The internal voltage Vccint is temporarily increased by being pulled by the boost voltage Vccint2. For this reason, it is necessary to control the internal voltage Vccint to be raised by a differential amplifier or the like in the internal voltage generation circuit 3 for a while after the standby state is set, that is, until the boosted voltage Vccint2 decreases. Overall, power consumption may increase.

  Some flash memories have a CE short cycle mode for switching between a memory access state and a standby state in accordance with the logic of the chip enable signal. In the CE short cycle mode, the memory access state and the standby state are periodically switched. Therefore, the operation of switching to the standby state and increasing the internal voltage Vccint before the internal voltage Vccint decreases to 5 V during memory access is repeated. As a result, the internal voltage Vccint may eventually rise to a maximum of 6.5V. Since the internal voltage Vccint is the word line potential in the memory chip, the read potential is also a maximum of 6.5 V, and there is a possibility that data written in the memory cannot be read correctly due to variations in the threshold value of the memory cell transistor.

  On the other hand, the semiconductor integrated circuit device schematically shown in FIG. 17 is configured such that the internal voltage Vccint does not fluctuate immediately after entering the standby state. FIG. 17 shows a part of the internal configuration of the EEPROM, that is, a circuit block that boosts the external power supply voltage Vccext to generate the boosted voltage Vccint2, and a circuit block that generates the internal voltage Vccint from the boosted voltage Vccint2. The EEPROM of FIG. 17 is configured in substantially the same manner as the first embodiment except that the configuration of the internal voltage generation circuit 3a is different from that of the first embodiment. Therefore, the configuration of the internal voltage generation circuit 3a will be described below. The explanation is centered.

  The internal voltage generation circuit 3a of FIG. 17 includes a memory access voltage control circuit 51, a low power consumption internal voltage detection circuit 52, a level shifter 53, and a switch circuit 54. The memory access voltage control circuit 51 generates the internal voltage Vccint at the time of memory access and performs voltage control so that the internal voltage Vccint does not fluctuate. The low power consumption internal voltage detection circuit 52 outputs a signal corresponding to the voltage level of the internal voltage Vccint. More specifically, if the internal voltage Vccint is higher than a predetermined voltage, a high level signal is output. If the internal voltage Vccint is lower than the predetermined voltage, a low level signal is output. After this signal is input to the level shifter 53 and level-converted, Input to the switch circuit 54. The switch circuit 54 is always in an off state during memory access, and is turned on when the internal voltage Vccint becomes equal to or lower than a predetermined voltage during standby to short-circuit the boosted voltage Vccint2 and the internal voltage Vccint.

  FIG. 18 is a circuit diagram showing a detailed configuration of the voltage control circuit 51 during memory access. As shown in FIG. 18, the memory access voltage control circuit 51 includes a differential amplifier 61, PMOS transistors Q51 and Q52, and resistors R51 and R52. The boosted voltage Vccint2 is applied to the source terminal of the PMOS transistor Q51, and the internal voltage Vccint is output from the connection point between the drain terminal and the source terminal of the PMOS transistor Q52. Resistors R51 and R52 are connected in series between the drain terminal and the ground terminal of the PMOS transistor Q52, the signal STANDBYH is applied to the gate terminal of the PMOS transistor Q52, and the output terminal of the differential amplifier 61 is connected to the gate terminal of the PMOS transistor Q51. Is connected. The differential amplifier 61 operates only at the time of memory access, and the voltage between the resistors R51 and R52 is applied to its positive input terminal, and the reference voltage Vref is applied to its negative input terminal.

  During memory access, the PMOS transistor Q52 is turned on, and a voltage obtained by dividing the internal voltage Vccint by resistors R51 and R52 is input to the positive input terminal of the differential amplifier 61. For example, when the internal voltage Vccint becomes higher than a predetermined voltage, the positive input terminal of the differential amplifier 61 becomes higher than the negative input terminal, and the output voltage of the differential amplifier 61 becomes higher and the PMOS becomes higher. Transistor Q51 operates in the direction to turn off, and the internal voltage Vccint decreases. On the contrary, when the internal voltage Vccint becomes lower than a predetermined voltage, the positive input terminal of the differential amplifier 61 becomes lower than the negative input terminal, and the output voltage of the differential amplifier 61 becomes lower. The PMOS transistor Q51 operates in the ON direction, and the internal voltage Vccint increases. By such control, the internal voltage Vccint is controlled to a predetermined voltage during memory access.

  On the other hand, during standby, the PMOS transistor Q52 is turned off and the differential amplifier 61 does not operate, so that the internal voltage Vccint gradually decreases due to wiring resistance or the like. Further, the voltage level of the internal voltage Vccint during standby is detected by a low power consumption internal voltage detection circuit 52 shown in FIG.

  FIG. 19 is a circuit diagram showing a detailed configuration of the low power consumption internal voltage detection circuit 52. As shown in FIG. 19, the low power consumption internal voltage detection circuit 52 includes a low power amplifier 62 having the same configuration as that of FIG. 4 and resistors R53 and R54. An internal voltage Vccint is applied to one end of the resistors R53 and R54 connected in series, and the other end is grounded. The voltage between the resistors R53 and R54 is applied to the positive input terminal of the low power amplifier 62, and the reference voltage Vref is applied to the negative input terminal. The output of the low power amplifier 62 is supplied to the level shifter 53 shown in FIG.

  For example, when the internal voltage Vccint becomes higher than a predetermined voltage during standby, the output of the low power amplifier 62 becomes low level. Conversely, when the internal voltage Vccint becomes equal to or lower than a predetermined voltage during standby, the output of the low power amplifier 62 becomes high level. Since the low power amplifier 62 consumes less current than a normal differential amplifier, power consumption during standby can be reduced.

  The level shifter 53 shown in FIG. 17 is configured by a circuit similar to that shown in FIG. 11, and converts the level of the output voltage of the low power amplifier 62. The voltage after level conversion is input to a NAND gate G51 in the switch circuit 54. The output of the NAND gate G51 is always at the high level when the memory is accessed, and the PMOS transistor Q53 maintains the off state. Even during standby, when the output of the level shifter 53 is at a low level, that is, when the internal voltage Vccint is higher than a predetermined voltage, the output of the NAND gate G51 is at a high level. On the other hand, when the internal voltage Vccint becomes equal to or lower than a predetermined voltage during standby, the output of the NAND gate G51 becomes low level, the PMOS transistor Q53 is turned on, and the boosted voltage Vccint2 and the internal voltage Vccint are short-circuited.

  FIG. 20 is a timing diagram showing how the boost voltage Vccint2 and the internal voltage Vccint change when the memory access state transitions to the standby state. The CE bar in FIG. 20 is an EEPROM chip enable signal.

  The operation of the second embodiment shown in FIG. 17 will be described below using the timing chart of FIG. The operation of the booster circuit 1 is the same as that of the first embodiment. For example, based on the external power supply voltage Vccext of 3V, a boosted voltage Vccint2 of about 6.5V is generated during memory access and about 5V during standby. The operation of the internal voltage generation circuit 3a is the same as that of the first embodiment at the time of memory access, and an internal voltage Vccint of about 5V is generated based on the boosted voltage Vccint2 of about 6.5V.

  On the other hand, when the memory access state transitions to the standby state (time T1 in FIG. 20), the memory access voltage control circuit 51 shown in FIG. 17 stops its operation, and the low power consumption internal voltage detection circuit 52 operates instead. To start. The low power consumption internal voltage detection circuit 52 detects whether or not the voltage value of the internal voltage Vccint has become a predetermined voltage. While internal voltage Vccint is higher than a predetermined voltage, PMOS transistor Q53 in switch circuit 54 is in an off state. In standby mode, the booster circuit 1 controls the boosted voltage Vccint2 to be lowered from 6.5 V to 5 V, so that the boosted voltage Vccint2 gradually decreases. Also, the internal voltage Vccint gradually decreases due to wiring resistance or the like.

  Eventually, when the internal voltage Vccint becomes equal to or lower than a predetermined voltage (time T2 in FIG. 20), the PMOS transistor Q53 is turned on and the boosted voltage Vccint2 and the internal voltage Vccint are short-circuited. If the boosted voltage Vccint2 and the internal voltage Vccint are short-circuited, the internal voltage Vccint may be excessively increased due to the boosted voltage Vccint2, but here, when the internal voltage Vccint rises to a predetermined voltage, the PMOS again Transistor Q53 is turned off to suppress further increase in internal voltage Vccint.

  FIG. 21 is an enlarged timing diagram in the vicinity of time T2 in FIG. 20, showing the internal voltage Vccint and the output waveform of the PMOS transistor. As shown in FIG. 21, when the PMOS transistor Q53 is turned on at time T2, the boosted voltage Vccint2 and the internal voltage Vccint are short-circuited to increase the internal voltage Vccint, and the PMOS transistor Q53 is turned off again at time T3. When the PMOS transistor Q53 is turned off, the internal voltage Vccint decreases, and at time T4, the PMOS transistor Q53 is turned on again, so that the boosted voltage Vccint2 and the internal voltage Vccint are short-circuited. By repeating such control, the internal voltage Vccint converges to a predetermined voltage (for example, 5V).

  FIG. 20 shows an internal voltage waveform in the second embodiment and an internal voltage waveform in the example of FIG. 16 for comparison. In the example of FIG. 16, the internal voltage immediately after the standby state is entered. It can be seen that while Vccint temporarily rises, the internal voltage Vccint hardly changes in the second embodiment.

[Third Embodiment]
The third embodiment is characterized in that a circuit for detecting the voltage level of the boosted voltage Vccint2 and a circuit for detecting the voltage level of the internal voltage Vccint are shared.

  FIG. 22 is a schematic configuration diagram of a third embodiment of the semiconductor integrated circuit device. FIG. 22 is substantially the same as FIG. 17 except that the configuration of the level detection circuit 2a for detecting the voltage level of the boosted voltage Vccint2 is different from that of FIG. 17, so the following mainly focuses on the configuration of the level detection circuit 2a. Explained.

  The level detection circuit 2a shown in FIG. 22 includes the first level detection unit 21 shown in FIG. 4, AND gates G52 and G53, and an inverter INV51. The booster circuit 1 performs voltage control of the boosted voltage Vccint2 according to the output of the AND gate G52 during memory access, and performs voltage control of the boosted voltage Vccint2 according to the output of the AND gate G53 during standby. The AND gate G52 outputs the output of the first level detector 21 as it is when the memory is accessed. Further, the AND gate G53 outputs the output of the low power consumption internal voltage detection circuit 52 as it is during standby.

  Next, the operation of the third embodiment will be described. The booster circuit 1 controls the level of the boosted voltage Vccint2 based on the detection result of the first level detector 21 during memory access. Further, since the boost voltage Vccint2 and the internal voltage Vccint are short-circuited during standby, the level control of the boost voltage Vccint2 is performed based on the detection result of the low power consumption internal voltage detection circuit 52 that detects the voltage level of the internal voltage Vccint. I do. As a result, it is not necessary to provide the level detection circuit 22 for exclusive use in standby mode as shown in FIG. 4 in the level detection circuit 2a, so that the circuit configuration can be simplified and the power consumption can be reduced.

[Fourth Embodiment]
The fourth embodiment is characterized in that the driving power of the booster circuit is switched between memory access and standby.

  FIG. 23 is a schematic configuration diagram of a fourth embodiment of a semiconductor integrated circuit device. The fourth embodiment is substantially the same as the second embodiment except that the configuration of the booster circuit 1a is different from that of the second embodiment shown in FIG. The explanation will be focused on.

  The booster circuit 1a of FIG. 23 includes a first charge pump 11a that generates a boosted voltage Vccint2 during memory access, and a second charge pump 11b that generates a boosted voltage Vccint2 during standby. Each of these charge pumps is configured by a circuit similar to that in FIG. 2, but the charge supply capability of the first charge pump 11a is higher than that of the second charge pump 11b. Thus, in order to give a difference in charge supply capability, for example, the capacitance of the capacitor in the charge pump may be changed.

  During memory access, the output of the AND gate G54 is fixed at a low level, so the second charge pump 11b does not operate. On the other hand, the output of the level detection circuit 2 is output as it is from the AND gate G55, and the first charge pump 11a controls the level of the boost voltage Vccint2 according to the output of the level detection circuit 2.

  Conversely, during standby, the output of the AND gate G55 is fixed at a low level, so the first charge pump 11a does not operate. On the other hand, the output of the level detection circuit 2 is output as it is from the AND gate G54, and the second charge pump 11b controls the level of the boost voltage Vccint2 according to the output of the level detection circuit 2.

  Thus, in the fourth embodiment, when the standby state is entered, the boosted voltage Vccint2 is generated by the charge pump 11b having a weak charge supply capability (driving capability), so that the peak current during standby can be suppressed and the power consumption is reduced. Can be reduced.

  Note that the booster circuit 1 in the circuit of FIG. 22 may be changed to the booster circuit 1a of FIG. A schematic configuration diagram in this case is as shown in FIG. In the case of FIG. 24, the same effect as in FIG. 23 can be obtained. Similarly, the booster circuit 1 of the first embodiment shown in FIG. 1 may be changed to the booster circuit 1a of FIG.

  In the embodiment described above, the voltage Vccext supplied from the outside is once boosted and then lowered by the internal voltage generation circuit 3. However, without providing the internal voltage generation circuit 3, the boosted voltage is directly applied to the memory cell array 6 or You may supply to the address decoder 5 grade | etc.,. However, if the internal voltage generation circuit 3 is not provided, there is an advantage that the circuit configuration can be simplified, but the voltage control accuracy is deteriorated.

  In the above-described embodiment, the semiconductor integrated circuit device having the memory cell array 6 having the EEPROM configuration has been described. However, the present invention can also be applied to a case having the memory cell array 6 having a DRAM or SRAM other than the EEPROM configuration. The present invention can also be applied to voltage control of other semiconductor circuits other than the memory cell array 6. In this case, the state where the semiconductor circuit is operating normally corresponds to the memory access state, and the state where the semiconductor circuit is waiting corresponds to the standby state.

1 is a schematic configuration diagram of an embodiment of a semiconductor integrated circuit device. The circuit diagram which shows the detailed structure of a charge pump. The circuit diagram which shows the detailed structure of an oscillator. The circuit diagram which shows the detailed structure of a level detection circuit. The circuit diagram which shows the detailed structure of the low power amplifier in a 2nd level detection part. The circuit diagram which shows the modification of the circuit which resets low power amplifier. The figure which shows the example which comprised the booster circuit by connecting two charge pumps in parallel. The circuit diagram which shows the detailed structure of an internal voltage generation circuit. The circuit diagram which shows the detailed structure of the differential amplifier in an internal voltage generation circuit. The circuit diagram which shows the detailed structure of a control signal generation circuit. The figure which shows the detailed structure of the level shifter circuit shown in FIG. FIG. 10 is a circuit diagram showing a detailed configuration of the delay circuit shown in FIG. 9. FIG. 2 is a waveform diagram showing operation timings of the semiconductor integrated circuit device shown in FIG. 1. The circuit diagram which shows the detailed structure of a reference voltage generation circuit. The figure which shows the example which diverts the constant current source part in a 2nd level detection part by a reference voltage generation circuit. The schematic block diagram of the semiconductor integrated circuit device for comparing with 2nd Embodiment of a semiconductor integrated circuit device. The schematic block diagram of 2nd Embodiment of a semiconductor integrated circuit device. The circuit diagram which shows the detailed structure of the voltage control circuit at the time of memory access. The circuit diagram which shows the detailed structure of a low power consumption internal voltage detection circuit. FIG. 6 is a timing diagram showing how the boost voltage Vccint2 and the internal voltage Vccint change when a transition is made from the memory access state to the standby state. The timing diagram which expanded the vicinity of the time T2 of FIG. The schematic block diagram of 3rd Embodiment of a semiconductor integrated circuit device. The schematic block diagram of 4th Embodiment of a semiconductor integrated circuit device. FIG. 24 is a diagram in which the booster circuit 1 in the circuit of FIG. The figure explaining the structure of the conventional non-volatile semiconductor memory.

Explanation of symbols

1 Booster 2 Level detector 3 Internal voltage generator 4 Address buffer (ADB)
5 Address decoder (RDC)
6 Memory cell array (MCA)
7 Stabilizing Capacitor 11 Charge Pump 12 Oscillator 21 First Level Detection Circuit 22 Second Level Detection Circuit 25 Low Power Amplifier 27 Constant Current Source Unit 28 Differential Amplification Unit

Claims (6)

In a semiconductor integrated circuit device comprising a booster circuit for boosting a voltage supplied from the outside, and a semiconductor circuit driven by a voltage corresponding to the boosted voltage boosted by the booster circuit,
Having first and second operating states;
The booster circuit includes:
A first charge pump;
A second charge pump having a driving force weaker than that of the first charge pump,
The booster circuit performs voltage control by the first charge pump so that the boosted voltage becomes the first voltage when the semiconductor circuit is in the first operation state, and the semiconductor circuit A semiconductor integrated circuit device, wherein in the operating state, voltage control is performed by the second charge pump so that the boosted voltage becomes a second voltage different from the first voltage. An internal voltage generating circuit for generating an internal voltage from the boosted voltage;
The internal voltage generation circuit includes:
A first internal voltage detection circuit that detects voltage fluctuation of the internal voltage when the semiconductor circuit is in the first operating state;
A second internal voltage detection circuit configured with a circuit that consumes less power than the first internal voltage detection circuit, and that detects voltage fluctuations of the internal voltage when the semiconductor circuit is in the second operating state; With
The internal voltage generation circuit sets the internal voltage to a voltage level lower than the boosted voltage when the semiconductor circuit is in the first operation state, and the internal voltage when the semiconductor circuit is in the second operation state. Is set to a voltage level substantially equal to the boosted voltage. A level detection circuit for detecting voltage fluctuations of the boosted voltage when the semiconductor circuit is in the first operating state;
The booster circuit performs voltage control so that the boosted voltage becomes the first voltage based on a detection result of the level detection circuit when the semiconductor circuit is in the first operation state, and the semiconductor circuit 3. The semiconductor according to claim 2, wherein in the second operation state, voltage control is performed so that the boosted voltage becomes the second voltage based on a detection result by the second internal voltage detection circuit. Integrated circuit device. The internal voltage generation circuit includes:
Switch means for switching whether to short-circuit each output terminal of the booster circuit and the internal voltage generation circuit;
After the semiconductor circuit transitions from the first operation state to the second operation state, a switch that switches the switch means to make the internal voltage substantially equal to the boost voltage when the internal voltage falls below a predetermined voltage A control circuit,
The internal voltage generation circuit sets the internal voltage to a voltage level lower than the boosted voltage when the semiconductor circuit is in the first operation state, and the internal voltage when the semiconductor circuit is in the second operation state. 4. The semiconductor integrated circuit device according to claim 1, wherein a voltage level substantially equal to the boosted voltage is set. At least a part of the semiconductor circuit is an EEPROM configured memory cell array,
The first operation state is a memory access state in which reading and writing are performed on the memory cell array,
5. The storage device according to claim 1, wherein the second operation state is a standby state waiting for reading or writing to the memory cell array. 6. At least a part of the semiconductor circuit is an EEPROM configured memory cell array,
5. The memory device having a semiconductor integrated circuit device according to claim 1, wherein the memory cell array is driven based on the boosted voltage.

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