JP2007233202A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device which can suppress flicker when starting while suppressing extension of a start time. <P>SOLUTION: The liquid crystal display device includes a liquid crystal display panel 1 having TFTs 11 to xy, a gate driver, a source driver, a charge pump circuit 5 for supplying a voltage GVDD to the gate driver 4, a liquid crystal controller 10 for outputting a signal VIDEO, and a counter electrode drive circuit 9 for driving a counter electrode. The liquid crystal display device further includes a limiting circuit 11 and a boosted voltage detection circuit 12. When a voltage value of the voltage GVDD reaches a reference value, a signal PREDY informing that it has reached the reference value is output to the limiting circuit 11 by the boosted voltage detection circuit 12. Output of the signal VIDEO and driving the counter electrode by the counter electrode drive circuit are stopped by the limiting circuit 11 and the stoppage are released when the boosted voltage detection circuit 12 outputs the signal PREDY. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device.

  2. Description of the Related Art Conventionally, a so-called active matrix type liquid crystal display device using a TFT (Thin Film Transistor) is known as a liquid crystal display device. An active matrix liquid crystal display device is a liquid crystal display in which liquid crystal is sandwiched between an active matrix substrate in which a plurality of TFTs are arranged in a matrix and a counter substrate in which a plurality of color filters are arranged in a matrix. Has a panel. The configuration and signal processing of a conventional active matrix liquid crystal display panel will be described with reference to FIGS.

  First, a basic configuration of a conventional active matrix liquid crystal display device will be described with reference to FIG. FIG. 4 is a configuration diagram showing a configuration of a conventional active matrix liquid crystal display device. In FIG. 4, the liquid crystal display device is shown by an equivalent circuit.

  As shown in FIG. 4, the liquid crystal display device includes a liquid crystal controller (control circuit) 30, a liquid crystal display panel 31, a source driver 33, a gate driver 34, and a charge pump circuit 35. The source driver 33, the gate driver 34, and the charge pump circuit 35 are mounted in a region (peripheral region) outside the display region 32 of the liquid crystal display panel 31.

  In the display area 32 of the liquid crystal display panel 31, a plurality of TFTs (active elements) 11 to TFTxy, a plurality of pixel electrodes (not shown) corresponding to each TFT, a liquid crystal layer (not shown), and a counter substrate are formed. A plurality of color filters (not shown) and a counter electrode (not shown) are provided.

  In FIG. 4, VCOM indicates a voltage (counter electrode drive voltage) applied to the counter electrode. The common electrode voltage VCOM is generated by the common electrode drive circuit 39 based on the power supply voltage VDD supplied from the power supply circuit 38. C11 to Cxy indicate pixel capacitances constituted by the respective pixel electrodes, the counter electrode, and the liquid crystal layer existing therebetween. The TFTs 11 to TFTxy, the pixel electrodes, and the pixel capacitors C11 to Cxy are arranged in a matrix.

  The display area 32 is also provided with a plurality of data lines DL1-DLx and a plurality of gate lines GL1-GLy. The gate lines GL <b> 1 to GLy are signal lines for turning on / off the TFTs 11 to TFTxy, and are driven by the gate driver 34. The gate lines GL1 to GLy are provided for the TFTs arranged on the same horizontal line, and the gates of the TFTs arranged on the same horizontal line are connected to the same gate line. Of the gate lines GL1 to GLy, the line selected by the gate driver 34 turns on all the TFTs arranged on the line. At this time, all TFTs arranged on the unselected line are turned off.

  The data lines DL1 to DLx are signal lines for applying a voltage to the pixel capacitors C11 to Cxy via the TFTs 11 to TFTxy, and are driven by the source driver 33. The data lines DL1 to DLx are provided for the TFTs arranged on the same vertical line, and are connected to the drains of the TFTs arranged on the same vertical line. Note that the sources of the TFTs 11 to TFTxy are connected to the corresponding pixel electrodes.

  Further, auxiliary capacitances Cs11 to Csxy corresponding to the TFTs 11 to TFTxy are also provided in the display area 32 in order to hold data. The auxiliary capacitors Cs11 to Csxy are configured by Cs wiring (not shown), pixel electrodes, and an interlayer insulating film formed therebetween. Each of the auxiliary capacitors Cs11 to Csxy is connected to the corresponding pixel capacitors C11 to Cxy via pixel electrodes. In the example of FIG. 4, the voltage GVDD boosted by the charge pump circuit 35 is applied to the auxiliary capacitors Cs11 to Csxy via the Cs wiring in order to use the auxiliary capacitors near the maximum capacity (for example, , See Patent Document 1).

  The charge pump circuit 35 boosts the power supply voltage VDD (for example, 12 [V]) input from the power supply circuit 38 in accordance with the input timing of the source clock (SCK) signal from the liquid crystal controller 30, and the voltage GVDD (for example, 16 V). [V]) is generated (see, for example, Patent Document 2). The voltage GVDD is applied to the above-described Cs wiring and the gate driver 34 in accordance with a clock timing of a gate clock (GCK) signal described later. The gate driver 34 uses the voltage GVDD as a switching voltage for turning on the TFTs 11 to TFTxy.

  In addition to the gate driver 34, a capacitor 36 and a Zener diode 37 are also connected to the charge pump circuit 35. The capacitor 36 is intended to reduce noise when the voltage GVDD is output. The Zener diode 37 is intended to maintain a constant voltage and prevent excessive voltage.

  The liquid crystal controller 30 generates various signals for driving the liquid crystal display panel 31 and inputs them to the source driver 33, the gate driver 34, and the charge pump circuit 35. Specifically, the liquid crystal controller 30 inputs a gate clock (GCK) signal for causing the gate driver 34 to perform a shift operation to the charge pump circuit 35 and instructs the gate driver 34 to start the shift operation. (GSP) signal is input.

  In addition, when the liquid crystal display device is powered on, the liquid crystal controller 30 inputs an initialization (INI) signal to the gate driver 34 to initialize the gate driver 34. Further, the liquid crystal controller 30 inputs the SCK signal to the charge pump circuit 35 and the source driver 33. The liquid crystal controller 30 also inputs a video (VIDEO) signal for image display to the source driver 33.

  Next, signals input to the liquid crystal display panel by the liquid crystal controller 30 shown in FIG. 4 and input timing thereof will be described with reference to FIG. FIG. 5 is a diagram showing signals input from the outside to the liquid crystal display panel shown in FIG. FIG. 5 shows only when the liquid crystal display device is turned on, that is, until the power supply voltage VDD rises from the GND level to the reference value and the liquid crystal display device starts liquid crystal display.

  As shown in FIG. 5, first, when the power supply voltage VDD from the power supply circuit 38 rises from GND to a predetermined voltage value, the liquid crystal controller 30 raises the INI signal. The INI signal is used for initialization of the gate driver 34 and the like. In FIG. 5, a period during which the INI signal is at a high level is defined as an initialization period a. In the initialization period a, since the source driver 33 and the gate driver 34 do not operate, the liquid crystal display panel 31 does not operate and liquid crystal display is not performed.

Next, the liquid crystal controller 30 inputs the SCK signal while the initialization period “a” continues, and starts driving the charge pump circuit 35. When the charge pump circuit 35 is driven, the voltage GVDD rises and reaches a stable level (reference value) after a predetermined time has elapsed. Voltage GV
A period from the rise of DD to the reference value is defined as a rise period c. In the initialization period a, a period from the rising edge of the INI signal until the voltage GVDD reaches the reference value is a1, and a period from the voltage GVDD reaching the reference value to the end of the initialization period a is a2. .

  When the voltage GVDD reaches the reference value and the level is stabilized, the liquid crystal controller 30 lowers INI and ends the initialization period a. A period in which the INI signal falls and is at a low level is a period b. Next, when the initialization period a ends, the liquid crystal controller 30 outputs a GSP signal to the gate driver 34 to start a shift operation, and further switches the level of the VIDEO signal input to the source driver 33 to a high level. At this time, the common electrode drive circuit 39 switches the level of the common electrode voltage VCOM to a high level and drives the common electrode. As a result, display of a desired image is started in the display area 2.

  Note that the input timing of the SCK signal is set so that the period (corresponding to the rising period c) from when the input of the SCK signal starts until the voltage GVDD reaches a stable level falls within the initialization period a. The length of the initialization period a is set in consideration of the length of the rising period c, that is, the characteristics of the church pump circuit 35.

  Here, operations of the TFT, the pixel capacitor C, and the auxiliary capacitor Cs in the initialization period a will be described with reference to FIG. FIG. 6 is an enlarged view showing one of the unit pixels of the liquid crystal display device shown in FIG. As shown in FIG. 6, a charge Q1 is accumulated by the pixel capacitor C between the drain electrode and the counter electrode of the TFT connected to the pixel capacitor C. Further, the charge Q2 is accumulated between the drain electrode of the TFT and the Cs wiring by the auxiliary capacitor Cs.

  In the initial period a, the TFT is in the OFF state, and the level of the counter electrode voltage VCOM is GND. Therefore, the charge amount of the charge Q1 is 0 (zero). On the other hand, the charge Q2 is generated as the voltage GVDD increases. Therefore, when the charge amount of the charge Q2 is Q, the capacitance of the pixel capacitor C is Clc, and the auxiliary capacitor Cs is Ccs, the following equation (1) is established. Further, when the potential difference between the drain electrode and the counter electrode of the TFT at this time is V, the following formula (2) is also established.

  Further, when the TFT is in the OFF state, the pixel capacitor C and the auxiliary capacitor Cs are connected in series. Therefore, the charge amount of the charge Q1 is equal to the charge amount of the charge Q2. Further, assuming that the capacitance Clc of the pixel capacitance C and the capacitance Ccs of the auxiliary capacitance Cs are equal, V = GVDD / 2 from the above equation (2). Therefore, when the TFT is in the OFF state, a voltage half the voltage GVDD is applied between the drain electrode and the counter electrode of the TFT.

At this time, when a normally white TN liquid crystal is used as the liquid crystal layer constituting the liquid crystal display panel, voltage is applied to the liquid crystal layer, so the display in the display area 32 is black. The higher the voltage GVDD is, the larger the capacity Ccs of the auxiliary capacity Cs is.
Japanese Patent Laid-Open No. 3-149520 JP 2001-183702 A

  However, the charge pump circuit 35 has a problem that variations tend to occur for each liquid crystal module (liquid crystal display device). Therefore, depending on the liquid crystal module, as shown by the broken line in FIG. 5, the rising period c may not be within the set initial period a (“rise period c ′” shown in FIG. 5). As a result, a situation occurs in which the level of the counter electrode voltage VCOM becomes higher than the level of the voltage GVDD, which causes a problem that the display area 32 flickers even though the liquid crystal display is not performed.

  On the other hand, when the liquid crystal display panel is fully transmissive, the backlight lighting timing may be shifted backward and the flickering masked by black display may be considered, but this is the case when the liquid crystal display panel is reflective. It is difficult to take corrective measures. Further, when the liquid crystal display device is a transflective type, flicker is visually recognized even if such a countermeasure is taken.

  The flicker described above is caused by the fact that the level of the counter electrode voltage VCOM is higher than the level of the voltage GVDD. Therefore, the length of the initialization period a is estimated after the degree of variation of the charge pump circuit 35 is predicted. It is also conceivable to set the value sufficiently long in advance. However, it is difficult to predict the degree of variation, and when such measures are taken, a new problem arises that the startup time of the liquid crystal display device becomes longer than necessary.

  The objective of this invention is providing the liquid crystal display device which can suppress the flicker at the time of starting, solving the said problem and suppressing the prolongation of starting time.

  In order to achieve the above object, a liquid crystal display device according to the present invention includes a liquid crystal display panel having a plurality of active elements arranged in a matrix, a gate driver, a source driver, a power supply voltage, and a boosted voltage. A limiting circuit, comprising: a booster circuit for supplying to the gate driver; a control circuit for outputting a video signal to the source driver; and a counter electrode driving circuit for driving a counter electrode of the liquid crystal display panel. And a boosted voltage detection circuit, and when the voltage value of the voltage boosted by the booster circuit reaches a reference value, the boosted voltage detection circuit limits the notification signal for notifying that the reference value has been reached. Output to the circuit, and when the boosted voltage detection circuit does not output the notification signal, the limiting circuit outputs the video signal by the control circuit. When the output and the driving of the counter electrode by the counter electrode driving circuit are stopped and the boosted voltage detection circuit outputs the notification signal, the stop of the output of the video signal and the driving of the counter electrode is canceled. Features.

  As described above, in the liquid crystal display device according to the present invention, whether or not the voltage GVDD has reached the reference value is detected, and before the voltage GVDD reaches the reference value, the output of the video signal to the source driver and the opposite The electrode is not driven. For this reason, according to the liquid crystal display device of the present invention, occurrence of flicker at the time of startup is suppressed. In addition, according to the liquid crystal display device of the present invention, it is not necessary to set the initialization time longer than necessary as in the prior art, so that it is possible to suppress a long startup time.

The liquid crystal display device according to the present invention includes a liquid crystal display panel having a plurality of active elements arranged in a matrix, a gate driver, a source driver, and a booster that boosts a power supply voltage and supplies the boosted voltage to the gate driver. A liquid crystal display device comprising: a circuit; a control circuit that outputs a video signal to the source driver; and a counter electrode drive circuit that drives a counter electrode of the liquid crystal display panel, wherein the limiting circuit, the boost voltage detection circuit, When the voltage value of the voltage boosted by the boost circuit reaches a reference value, the boost voltage detection circuit outputs a notification signal notifying that the reference value has been reached to the limit circuit, and The limiting circuit outputs the video signal by the control circuit and drives the counter electrode when the boost voltage detection circuit does not output the notification signal. And driving of the counter electrode by road is stopped, when the boosted voltage detecting circuit outputs the notification signal, and cancels the stop of the driving of the counter electrode and the output of the video signal.

  In the liquid crystal display device according to the present invention, the limiting circuit includes a transistor element provided on a wiring for outputting the video signal to the source driver, and a counter electrode formed on the counter electrode by the counter electrode driving circuit. A transistor element provided on a wiring for outputting an electrode drive voltage, wherein the boosted voltage detection circuit drops a voltage boosted by the booster circuit to generate a voltage signal, and the voltage A resistance divider circuit for applying a signal to the gates of the two transistor elements, the resistor divider circuit having a voltage value of the voltage signal when the voltage value of the voltage boosted by the booster circuit reaches a reference value; The voltage signal can be generated so that becomes the threshold voltage of the transistor element. According to this aspect, with a simple circuit configuration, the output of the video signal and the driving of the counter electrode can be stopped until the voltage boosted by the booster circuit reaches the reference value, and the voltage boosted by the booster circuit becomes the reference value. When it reaches, the stop can be released.

  In the liquid crystal display device according to the present invention, each of the plurality of active elements is formed of silicon having faster charge mobility than amorphous silicon on an active matrix substrate constituting the liquid crystal display panel, and the gate driver, the source The driver and the booster circuit are preferably formed monolithically on the active matrix substrate. In this case, the liquid crystal display device can be thinned and the frame portion can be narrowed. The liquid crystal display device according to the present invention is useful when the liquid crystal display panel is a reflective liquid crystal display panel.

(Embodiment)
Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to FIGS. First, the overall structure of the liquid crystal display device in this embodiment will be described with reference to FIG. FIG. 1 is a configuration diagram showing the overall configuration of a liquid crystal display device according to an embodiment of the present invention.

  As shown in FIG. 1, the liquid crystal display device includes a liquid crystal display panel 1, a gate driver 4, a source driver 3, a booster circuit (charge pump circuit) 5, a liquid crystal, as in the conventional example (see FIG. 4). And a controller (control circuit) 10. The liquid crystal display device also includes a power supply circuit 8 that supplies a power supply voltage VDD and a counter electrode drive circuit 9 that generates a counter electrode drive voltage VCOM based on the power supply voltage VDD.

  The liquid crystal display panel 1 actually includes an active matrix substrate (not shown) in which a plurality of active elements are arranged in a matrix and a counter substrate (not shown) in which a plurality of color filters are arranged in a matrix. ) With a liquid crystal layer (not shown) interposed therebetween. In the present embodiment, the active element is a TFT.

In the display area 2 of the liquid crystal display panel 1, as in the conventional example, TFTs 11 to TFTxy, a plurality of pixel electrodes (not shown) corresponding to each TFT, a liquid crystal layer (not shown), and a counter substrate are formed. A plurality of color filters (not shown) and a counter electrode (not shown) are provided. Also in FIG. 1, similarly to the example of FIG. 4, C <b> 11 to Cxy indicate pixel capacitances constituted by each pixel electrode, a counter electrode, and a liquid crystal layer existing therebetween. The TFTs 11 to TFTxy, the pixel electrodes, and the pixel capacitors C11 to Cxy are arranged in a matrix.

  The display area 2 is also provided with a plurality of data lines DL1 to DLx and a plurality of gate lines GL1 to GLY, as in the conventional example. The gate lines GL1 to GLy are signal lines for turning on / off the TFTs 11 to TFTxy and are driven by the gate driver 4. The data lines DL1 to DLx are signal lines for applying a voltage to the pixel capacitors C11 to Cxy via the TFTs 11 to TFTxy, and are driven by the source driver 3.

  Further, as in the conventional example, auxiliary capacitances Cs11 to Csxy corresponding to the TFTs 11 to TFTxy are also provided in the display area 2 in order to hold data. The auxiliary capacitors Cs11 to Csxy are configured by Cs wiring (not shown), pixel electrodes, and an interlayer insulating film formed therebetween. Also in the example of FIG. 1, as in the conventional example, the voltage GVDD boosted by the charge pump circuit 5 is applied to the auxiliary capacitors Cs11 to Csxy via the Cs wiring.

  Similarly to the conventional example, the charge pump circuit 5 boosts the power supply voltage VDD (for example, 12 [V]) supplied from the power supply circuit 8 and the boosted voltage (voltage GVDD (for example, 16 [V])) as a gate driver. 4 is supplied. The gate driver 4 uses the voltage GVDD as a switching voltage for turning on the TFTs 11 to TFTxy. Similarly to the conventional example, the charge pump circuit 5 performs voltage boosting in accordance with the input timing of the source clock (SCK) signal from the liquid crystal controller 10 to generate the voltage GVDD. Further, the charge pump circuit 5 supplies the voltage GVDD to the Cs wiring as described above.

  In addition to the gate driver 4, a capacitor 6 and a Zener diode 7 are connected to the charge pump circuit 5 as in the conventional example. The capacitor 6 is intended to reduce noise when the voltage GVDD is output, like the capacitor 36 shown in FIG. The Zener diode 37 is also intended to maintain a constant voltage and prevent an excessive voltage, like the Zener diode 37 shown in FIG.

  Further, the gate driver 4, the source driver 3, and the booster circuit (charge pump circuit) 5 are arranged on the periphery of the display area 2 of the liquid crystal display panel 1, specifically on the active matrix substrate constituting the liquid crystal display panel 1. Are arranged around the display area. Further, the capacitor 6 and the Zener diode are also arranged in the area around the display area 2 as in the conventional case.

  The liquid crystal controller 10 generates various signals for driving the liquid crystal display panel 1 and inputs them to the source driver 3, the gate driver 4, and the charge pump circuit 5 as in the conventional example. Specifically, the liquid crystal controller 10 inputs a gate clock (GCK) signal to the charge pump circuit 35 and inputs a gate start pulse (GSP) signal to the gate driver 34. The liquid crystal controller 10 initializes the gate driver 4 by inputting an initialization (INI) signal to the gate driver 4 when the power of the liquid crystal display device is turned on. Further, the liquid crystal controller 10 inputs an SCK signal to the charge pump circuit 5 and the source driver 3.

As described above, the liquid crystal display device according to the present embodiment has the same configuration as the conventional liquid crystal display device shown in FIG. 4, but differs from the conventional example in the following points. As shown in FIG. 1, in the present embodiment, the liquid crystal display device includes a limiting circuit 11 and a boosted voltage detection circuit 12, unlike the conventional example.

  When the voltage value of the voltage GVDD boosted by the charge pump circuit 5 reaches a reference value (for example, 16 [V]) as shown in FIG. 4, the boost voltage detection circuit 12 sends the voltage GVDD to the limiting circuit 11. A notification signal (PREDY signal) for notifying that the voltage value has reached the reference value is output.

  The limiting circuit 11 stops the output of the video (VIDEO) signal by the liquid crystal controller 10 and the driving of the counter electrode by the counter electrode driving circuit 9 when the boosted voltage detection circuit 12 does not output the PREDY signal. . On the other hand, when the boosted voltage detection circuit 12 outputs the PREDY signal, the limiting circuit 11 cancels the stop of the output of the VIDEO signal and the stop of the driving of the counter electrode.

  In the present embodiment, the boosted voltage detection circuit 12 is connected to the charge pump circuit 5 by wiring, and the charge pump circuit 5 inputs the voltage GVDD to the boosted voltage detection circuit 12. Further, the voltage VCOM generated by the counter electrode drive circuit 9 is input to the limit circuit 11 and is input to the counter electrode via the limit circuit 11.

  In the present embodiment, the limiting circuit 11 is provided in the liquid crystal controller 10 and constitutes a part of the liquid crystal controller 10. When the driving of the counter electrode is stopped, in this embodiment, the level of the counter electrode driving voltage VCOM is continuously at the GND level. When the stop of the driving of the counter electrode is released, a high level counter electrode driving voltage VCOM is applied to the counter electrode.

  Here, specific examples of the limiting circuit 11 and the boosted voltage detection circuit 12 will be described with reference to FIGS. 2 and 3. FIG. 2 is a circuit diagram showing an example of the limiting circuit shown in FIG. FIG. 3 is a circuit diagram showing an example of the boosted voltage detection circuit shown in FIG.

  As shown in FIG. 2, in this example, the limiting circuit 11 includes a switching element 21 provided on the output wiring 24 for the VIDEO signal, a switching element 22 provided on the output wiring 25 for the voltage VCOM, and the PREDY signal. And an input terminal 23 for inputting.

  In this example, as the switching elements 21 and 22, for example, transistor elements can be used. When the switching elements 21 and 22 are transistor elements, the input terminal 23 is connected to the gate of each transistor.

  As shown in FIG. 3, in this example, the boosted voltage detection circuit 12 includes a resistance dividing circuit configured by connecting a resistor 24 and a resistor 25 in series. The resistor divider circuit lowers the voltage level of the voltage GVDD supplied from the charge pump 5 to a voltage level that can be input to the switching elements 21 and 22 (see FIG. 2), thereby generating a voltage signal.

  A branch wiring 26 is provided between the resistor 24 and the resistor 25. The branch wiring 26 is connected to the input terminal 23 (see FIG. 2) of the limiting circuit. Therefore, the voltage signal obtained by the resistance dividing circuit is input to the input terminal 23 of the limiting circuit via the branch wiring 26. The resistance values of the resistors 24 and 25 are the threshold values of the transistor elements that constitute the switching elements 21 and 22 when the voltage GVDD that has reached the reference value is input. It is set so as to be a Schold voltage.

For this reason, when the voltage GVDD reaches the reference value, the boosted voltage detection circuit 12 outputs a voltage signal whose voltage value matches the threshold voltage of the transistor elements constituting the switching elements 21 and 22. In this case, the switching elements 21 and 22 shown in FIG. 2 are closed. In this example, a voltage signal whose voltage value matches the threshold voltage of the transistor element is the PREDY signal.

  Thus, according to the limiting circuit 11 shown in FIG. 2 and the boosted voltage detecting circuit 12 shown in FIG. 3, when the boosted voltage detecting circuit 12 is not outputting the PREDY signal, the channel of the transistor element is not opened. , The VIDEO signal and the voltage VCOM are not output, and are stopped. On the other hand, when the boosted voltage detection circuit 12 outputs the PREDY signal, the channel of the transistor element is opened, the output stop of the VIDEO signal and the voltage VCOM is released, and these are output. According to the example shown in FIG. 2 and FIG. 3, with a simple circuit configuration, the output of the VIDO signal and the driving of the counter electrode can be stopped until the voltage GVDD reaches the reference value, and when the voltage GVDD reaches the reference value, The stop can be released.

  As described above, in the liquid crystal display device in this embodiment, the output of the VIDEO signal to the source driver 3 and the driving of the counter electrode are stopped before the voltage GVDD reaches the reference value. Therefore, when the liquid crystal display device is activated, the occurrence of flickering in the display area 2 (see FIG. 1) is suppressed. Further, unlike the conventional case, it is not necessary to set the initialization time a longer than necessary, and an image can be displayed immediately on the display area 2 when the voltage GVDD reaches the reference value, so that the start-up time is also prolonged. it can.

  In the present embodiment, the boosted voltage detection circuit 12 is not limited to the example shown in FIG. For example, the boosted voltage detection circuit 12 may include a transistor element and output a signal to the limiting circuit 11 by turning on / off the transistor element only when the voltage GVDD reaches a reference value.

  In this embodiment, when the PREDY signal is output, the limiting circuit 11 not only outputs the VIDEO signal and the voltage VCOM, but also causes the INI signal to fall and start outputting the GSP signal. You can also. According to this aspect, the startup time of the liquid crystal display device can be reliably shortened. Further, it is possible to save time and effort for setting the length of the initialization period a in advance.

  In the present embodiment, the source driver 3, the gate driver 4 and the charge pump circuit 5 can be formed monolithically on the active matrix substrate constituting the liquid crystal display panel 1. In this case, the silicon film formed on the base substrate (glass substrate) of the active matrix substrate is silicon having faster charge mobility than amorphous silicon, for example, polysilicon, low-temperature polysilicon, or CG (continuous grain boundary crystal) silicon. Etc. are preferred. Furthermore, in this case, the capacitor 6 and the Zener diode 7 can also be formed monolithically on the active matrix substrate.

  When the silicon film formed on the base substrate (glass substrate) of the active matrix substrate is formed of amorphous silicon, the source driver 3, the gate driver 4 and the charge pump circuit 5 are preferably provided by an IC chip. . In this case, these IC chips may be directly mounted on the active matrix substrate, or may be mounted on the FPC or an external substrate connected via the FPC.

  The liquid crystal controller 10 can also be provided by an IC chip. In this case, the IC chip constituting the liquid crystal controller 10 may be directly mounted on the active matrix substrate, or may be mounted on the FPC or an external substrate connected through the FPC.

In the present embodiment, the limiting circuit 11 can be arranged separately from the liquid crystal controller 10. In this case, the limiting circuit 11 can be formed monolithically on the active matrix substrate, like the source driver 3 and the like. The boosted voltage detection circuit 12 can also be formed monolithically on the active matrix substrate.

  In the present invention, the liquid crystal display panel may be any of a transmissive type, a transflective type, and a reflective type. However, as described in the background art, in the case of a reflective or transflective liquid crystal display panel, it is difficult to suppress flicker due to the lighting timing of the backlight. It is particularly useful when it is a semi-transmissive type.

  As described above, according to the present invention, since flickering at the time of starting the liquid crystal display device can be suppressed, the present invention is useful for a liquid crystal display device. The liquid crystal display device in the present invention has industrial applicability.

It is a block diagram which shows the whole structure of the liquid crystal display device in embodiment of this invention. FIG. 2 is a circuit diagram illustrating an example of a limiting circuit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a boosted voltage detection circuit illustrated in FIG. 1. It is a block diagram which shows the structure of the liquid crystal display device of the conventional active matrix system. It is a figure which shows the signal input into the liquid crystal display panel shown in FIG. 4 from the outside. It is a figure which expands and shows one of the unit pixels of the liquid crystal display device shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Display area 3 Source driver 4 Gate driver 5 Charge pump circuit (boost circuit)
6 Capacitance 7 Zener diode 8 Power supply circuit 9 Counter electrode drive circuit 10 Liquid crystal controller (control circuit)
DESCRIPTION OF SYMBOLS 11 Limit circuit 12 Boosting voltage detection circuit TFT11-TFTxy Active element C11-Cxy Pixel capacity Cs11-Csxy Auxiliary capacity DL1-DLx Data line GL1-GLy Gate line

Claims (4)

A liquid crystal display panel having a plurality of active elements arranged in a matrix, a gate driver, a source driver, a booster circuit that boosts a power supply voltage and supplies the boosted voltage to the gate driver, and an image on the source driver A liquid crystal display device comprising: a control circuit that outputs a signal; and a counter electrode drive circuit that drives a counter electrode of the liquid crystal display panel,
A limiting circuit and a boost voltage detection circuit;
When the voltage value of the voltage boosted by the booster circuit reaches a reference value, the boosted voltage detection circuit outputs a notification signal notifying that the reference value has been reached to the limit circuit,
The limiting circuit stops the output of the video signal by the control circuit and the driving of the counter electrode by the counter electrode drive circuit when the boost voltage detection circuit does not output the notification signal, and the boost circuit When the voltage detection circuit outputs the notification signal, the liquid crystal display device releases the stop of the output of the video signal and the driving of the counter electrode. Transistor circuit provided on the wiring for outputting the video signal to the source driver by the limiting circuit, and wiring for outputting the common electrode driving voltage generated by the common electrode driving circuit to the common electrode A transistor element provided on the top,
The boosted voltage detection circuit includes a resistance dividing circuit that drops the voltage boosted by the boosting circuit to generate a voltage signal and applies the voltage signal to the gates of the two transistor elements;
The resistance dividing circuit is configured to output the voltage signal so that a voltage value of the voltage signal becomes a threshold voltage of the transistor element when a voltage value of the voltage boosted by the boosting circuit reaches a reference value. The liquid crystal display device according to claim 1 to be generated. Each of the plurality of active elements is formed of silicon having a faster charge mobility than amorphous silicon on an active matrix substrate constituting the liquid crystal display panel.
The liquid crystal display device according to claim 1, wherein the gate driver, the source driver, and the booster circuit are monolithically formed on the active matrix substrate.   The liquid crystal display device according to claim 1, wherein the liquid crystal display panel is a reflective or transflective liquid crystal display panel.

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