JP2007228095A - Power-on reset circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power-on reset circuit capable of outputting a stable reset pulse independently of a rising speed or a trailing speed of a power supply voltage. <P>SOLUTION: The power-on reset circuit 1 is provided with a start time adjustment section 2, a comparison voltage generating section 3, a comparator 4, a constant current source 5, and an Nch MOS transistor NT5. The start time adjustment section 2 adjusts a comparison start time between a reference voltage Vref and an input voltage Vin received by the comparator 4, and the comparison voltage generating section 3 generates a voltage subjected to resistance division in response to a leading or a change in a power supply voltage. The comparator 4 receives the input voltage Vin and the reference voltage Vref and outputs a compared and amplified output signal Out. Thus, the comparator 4 outputs the stable reset pulse independently of the leading speed and the trailing speed of the power supply voltage. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power-on reset circuit that outputs a predetermined reset signal when power is turned on or when power is turned off.

  The power-on reset circuit is mounted on a CMOS (Complementary Metal-Oxide Semiconductor) type semiconductor integrated circuit (IC or LSI) or the like, and when power is turned on, the power is turned off, or the power supply voltage is lowered, the semiconductor integrated circuit The semiconductor integrated circuit (IC or LSI) is initialized (reset) in order to prevent the circuit (IC or LSI) from malfunctioning or not operating (see, for example, Patent Document 1).

  In the power-on reset circuit described in Patent Document 1 or the like, when the power supply voltage rises, the voltage at the voltage dividing point obtained by resistance-dividing the power supply voltage changes in the same manner as the power supply voltage according to the resistance voltage dividing ratio × power supply voltage. When the power supply rises to a voltage at which the reference voltage generation circuit can operate, the reference voltage is output from the reference voltage generation circuit, and the voltage is detected during the period in which the relationship of reference voltage> voltage at the voltage dividing point is established. A reset pulse is output from the on-reset circuit to the semiconductor integrated circuit (IC or LSI). However, it takes time for the reference voltage output from the reference voltage generation circuit to stabilize when the power is turned on, and when the rise of the power supply voltage is fast, the relationship of the reference voltage> the voltage at the voltage dividing point is already present when the reference voltage is stabilized. There is a possibility that the power supply voltage exceeds the established period and a reset pulse is not generated. In this case, if the current supplied to the reference voltage generation circuit is increased in order to advance the stabilization time of the reference voltage, it cannot be applied to a semiconductor integrated circuit (IC or LSI) such as a microcomputer that requires low power consumption. There is a point.

In a power-on reset circuit in which a resistor and a capacitor are connected in cascade between the high-potential side power supply and the low-potential side power supply, and the voltage change between the resistor and the capacitor is input to the inverter, the rise of the power supply voltage is If the time constant is sufficiently slower than the RC time constant calculated from the above, the voltage change between the resistor and the capacitor almost follows the change in the power supply voltage, and there is a possibility that no reset pulse is generated.
JP-A-8-186484 (page 8, FIG. 1)

  An object of the present invention is to provide a power-on reset circuit that can output a stable reset pulse without depending on the rising or falling speed of a power supply voltage.

  In order to achieve the above object, a power-on reset circuit according to one embodiment of the present invention outputs a voltage signal that follows the power supply voltage when the power supply voltage rises, and the power supply voltage becomes equal to or higher than a predetermined voltage. From the start-up time adjustment unit that outputs a voltage signal that is gradually stepped down and becomes a ground voltage after a predetermined time, and the power supply voltage that is divided at a predetermined ratio based on the voltage signal output from the start-up time adjustment unit A comparison voltage generator for outputting a reference voltage and the input voltage, and amplifying and outputting a reset pulse signal when the reference voltage is greater than the input voltage. Comparing and amplifying means for stopping the output of the reset pulse signal when the input voltage is smaller than the input voltage is provided.

  Furthermore, in order to achieve the above object, a power-on reset circuit according to another aspect of the present invention outputs a voltage signal higher than a ground voltage when a bias start signal for speeding up an operation at power-on is input, When the voltage rises, a voltage signal that follows the power supply voltage is output, and after the power supply voltage becomes equal to or higher than a predetermined voltage, a voltage signal that is gradually stepped down and outputs the ground voltage after a predetermined time is output. A time adjustment unit; a comparison voltage generation unit that outputs the power supply voltage divided at a predetermined ratio as an input voltage based on a voltage signal output from the start-up time adjustment unit; and a reference voltage and the input voltage are input. The comparison amplification means for performing comparison amplification and the voltage signal output from the start-up time adjustment unit are input, and the signal inversion at the rise and fall of the voltage signal is different. A Schmitt circuit having a teresis characteristic, an output signal output from the comparison amplifying means and an output signal output from the Schmitt circuit are input, and an output signal output from the comparison amplifying means by performing a logical operation and the Schmitt circuit A reset pulse signal is output when any of the output signals output from the comparator is at “High” level, and both the output signal output from the comparison amplification means and the output signal output from the Schmitt circuit are at “Low” level. And a logic operation means for stopping the output of the reset pulse signal.

  According to the present invention, it is possible to provide a power-on reset circuit capable of outputting a stable reset pulse without depending on the rising or falling speed of the power supply voltage.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a power-on reset circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a power-on reset circuit. In this embodiment, a start-up time adjustment unit is provided so that a reset pulse can be output even when the power-on reset circuit has a fast rise in power supply voltage.

  As shown in FIG. 1, the power-on reset circuit 1 is provided with a startup time adjustment unit 2, a comparison voltage generation unit 3, a comparator 4, a constant current source 5, and an Nch MOS transistor NT5. The MOS transistor is also called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  The start-up time adjusting unit 2 is provided with a capacitor C1 and an Nch MOS transistor NT1. One end of the capacitor C1 is connected to the high potential side power source Vdd, and the other end is connected to the node N1. The activation time adjustment unit 2 has a function of adjusting the comparison start time of the input voltage Vin input to the comparator 4 and the reference voltage Vref. The Nch MOS transistor NT1 has a drain connected to the node N1, a source connected to the low potential side power source Vss which is the ground voltage, and a gate connected to the node N4.

  The comparison voltage generator 3 is provided with a Pch MOS transistor PT1, a resistor R1, and a resistor R2. The source of the Pch MOS transistor PT1 is connected to the high potential side power supply Vdd, and the signal of the node N1 is input to the gate. The comparison voltage generator 3 generates a resistance-divided voltage in response to the rise or change of the power supply voltage. The resistor R1 has one end connected to the drain of the Pch MOS transistor PT1 and the other end connected to the node N2. The resistor R2 has one end connected to the node N2 and the other end connected to the low potential side power supply Vss. The voltage obtained by resistance division from the node N1 is input to the comparator 4 as the input voltage Vin.

  The comparator 4 includes a resistor R3, a resistor R4, and Nch MOS transistors NT2 to NT4. The comparator 4 is an inverting type comparator (inverting comparator) that receives the reference voltage Vref on the (+) side and the input voltage Vin on the (−) side and performs comparison amplification.

  The resistor R3 has one end connected to the high potential side power source Vdd and the other end connected to the node N3. The resistor R4 has one end connected to the high potential side power supply Vdd and the other end connected to the drain of the Nch MOS transistor NT3. Here, the resistors R3 and R4 function as a load of the comparator 4. Instead of the resistors R3 and R4, for example, a current mirror circuit composed of a Pch MOS transistor may be used.

  N-channel MOS transistor NT2 has a drain connected to node N3, and input voltage Vin is input to the gate ((−) side of comparator 4). In Nch MOS transistor NT3, reference voltage Vref is input to the gate (the (+) side of comparator 4). Here, the Nch MOS transistors NT2 and NT3 form a differential pair. In the Nch MOS transistor NT4, the drain is connected to the sources of the Nch MOS transistors NT2 and NT3, the source is connected to the low potential power source Vss, and the signal of the node N4 is input to the gate. When the signal at the node N4 is at “High” level, the Nch MOS transistor NT4 is turned “ON” as a current source, the comparator 4 operates and the output signal Out of the comparator 4 is output from the node N3.

  The constant current source 5 has one end connected to the high potential side power supply Vdd, the other end connected to the drain of the Nch MOS transistor NT5, and supplies the bias current Ib to the Nch MOS transistor NT5. The Nch MOS transistor NT5 has a gate connected to the node N4, a drain and the gate of the Nch MOS transistor NT4, and a source connected to the low potential side power supply Vss. The Nch MOS transistors NT4 and NT5 constitute a current mirror circuit, and the bias current flowing to the low potential side power supply Vss side of the Nch MOS transistor NT5 and the bias current flowing to the low potential side power supply Vss side of the Nch MOS transistor NT4 have the same value. (Bias current Ib). Then, the signal of the node N4 as the bias voltage Vb is input to the gate of the Nch MOS transistor NT1.

  Next, the operation of the power-on reset circuit will be described with reference to the drawings. FIG. 2 is a timing chart showing the operation of the power-on reset circuit. Here, the operation of the power-on reset circuit when the rise of the power supply voltage is relatively fast will be described, and the operation when the rise of the power supply voltage is slow is the same as the conventional operation, and the description thereof will be omitted.

  As shown in FIG. 2, first, when the power supply voltage rises from 0V, the voltage at the node N1 rises following the power supply voltage due to the coupling effect of the capacitance of the capacitor C1 provided in the start-up time adjusting unit 2. . At this time, since the gate-source voltage (Vgs) of the Pch MOS transistor PT1 is equal to or lower than the threshold voltage (Vth), the Pch MOS transistor PT1 is “OFF”. Therefore, the input voltage Vin input to (−) of the comparator 4 is the low potential side power supply Vss voltage that is the ground voltage.

  Next, since the rise of the power supply voltage is relatively fast, the reference voltage Vref output from a reference voltage generation unit (not shown) (details will be described later with reference to FIG. 4) rises with a delay from the rise of the power supply voltage. The voltage becomes constant after t1. The constant current source 5 is generated based on a constant current generator (not shown) (details will be described later with reference to FIG. 4), and starts to output the bias current Ib when the power supply voltage reaches a certain voltage value. A constant current is output when becomes more than a predetermined value. The comparator 4 starts operation by supplying the bias current Ib (from time t1). Since the reference voltage Vref> the input voltage Vin at time t1, the output signal Out output from the comparator 4 becomes “High” level, and a reset pulse is output from the power-on reset circuit 1.

  Subsequently, the bias voltage Vb is supplied to the gate of the Nch MOS transistor NT1 in accordance with the operation of the constant current source 5, and the operation starts in the same manner as the comparator 4. At this time, since the power supply voltage is rising, the voltage change at the node N1 is determined by the relationship between the coupling effect due to the capacitor C1 and the voltage drop due to the current flowing through the Nch MOS transistor NT1, and changes gently.

When the voltage difference between the power supply voltage and the node N1 increases and the gate-source voltage (Vgs) of the Pch MOS transistor PT1 becomes larger than the threshold voltage (Vth), the Pch MOS transistor PT1 is turned “ON”. The input voltage Vin is
Vin = {r2 / (r1 + r2)} x Vdd ... (1)
As shown, the voltage starts to be boosted from the low potential side power supply Vss voltage which is the ground voltage. Here, r1 is the resistance value of the resistor R1, and r2 is the resistance value of the resistor R2.

  Next, at time t2, since the reference voltage Vref <the input voltage Vin, the output signal Out output from the comparator 4 becomes “Low” level, and the reset pulse is not output from the power-on reset circuit 1 after the time t2. (Reset pulse release). As a result, the period during which the reset pulse is output is (t2-t1).

  As described above, in the power-on reset circuit of this embodiment, the start-up time adjustment unit 2, the comparison voltage generation unit 3, the comparator 4, the constant current source 5, and the Nch MOS transistor NT5 are provided. When the power supply voltage starts up and rises from 0V, the start-up time adjusting unit 2 supplies a voltage that follows the power supply voltage to the comparison voltage generating unit 3 so that the input voltage Vin and the reference voltage Vref input to the comparator 4 are supplied. Adjust the comparison start time. The comparison voltage generator 3 generates a resistance-divided voltage in response to the rise or change of the power supply voltage. The comparator 4 receives the input voltage Vin and the reference voltage Vref, and outputs an output signal Out that has been compared and amplified.

  Therefore, the reset pulse can be stably output even when the power supply voltage rises quickly and it takes time until the reference voltage output from the reference voltage generation circuit is stabilized when the power is turned on. Further, the reset pulse can be stably output even when the power supply voltage falls. Therefore, a stable reset pulse is output from the comparator 4 without depending on the rising or falling speed of the power supply voltage. Also, since it is not necessary to increase the current supplied to the reference voltage generation circuit in order to accelerate the stabilization time of the reference voltage, it is applied to a semiconductor integrated circuit (IC or LSI) such as a microcomputer that requires low power consumption. it can.

In this embodiment, a MOS transistor in which the gate insulating film is made of a silicon oxide film is used. However, a SiNxOy film obtained by thermally nitriding a silicon oxide film, a laminated film of a silicon nitride film (Si ₃ N ₄ ) / silicon oxide film Alternatively, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which a high dielectric film (High-K gate insulating film) or the like serves as a gate insulating film may be used.

  Next, a power-on reset circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram showing a power-on reset circuit, and FIG. 4 is a circuit diagram showing a constant current generator and a reference voltage generator. In this embodiment, the reset pulse output period is lengthened using the bias start signal.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 3, the power-on reset circuit 1a is provided with a startup time adjustment unit 2a, a comparison voltage generation unit 3a, a comparator 4, a constant current source 5, and an Nch MOS transistor NT5.

  The start-up time adjusting unit 2a is provided with a capacitor C1, an Nch MOS transistor NT1, and a Pch MOS transistor PT2. In the Pch MOS transistor PT2, the source is connected to the high potential side power supply Vdd, the drain is connected to the node N1, and the bias start signal IBS is input to the gate.

  The comparison voltage generator 3a is provided with a Pch MOS transistor PT1, a resistor R1, a resistor R2, a resistor R5, and a capacitor C2. The resistor R5 has one end connected to the high potential side power supply Vdd and the other end connected to the source of the Pch MOS transistor PT1. In the Pch MOS transistor PT1, the drain is connected to the node N5, and the signal of the node N1 is input to the gate. The capacitor C2 has one end connected to the node N5 and the other end connected to the low potential side power source Vss. The resistor R1 has one end connected to the node N5 and the other end connected to the node N2. The resistor R2 has one end connected to the node N2 and the other end connected to the low potential side power supply Vss. The voltage obtained by resistance division from the node N1 is input to the comparator 4 as the input voltage Vin.

  Next, as shown in FIG. 4, the constant current generator 6 includes a startup circuit 8 and a constant current circuit 9, and a bias start signal IBS is output from the startup circuit 8. The reference voltage generator 7 outputs a reference voltage Vref and a bias current Ib.

  The start-up circuit 8 is provided with a Pch MOS transistor PT11, Nch MOS transistors NT11 to NT14, and a resistor R11. The startup circuit 8 causes a current to flow through the startup resistor R11 at the time of circuit startup, lowers the voltage at the node N13 via the Nch MOS transistors NT13 and NT14, and the Pch MOS transistors PT12 and PT13 of the constant current circuit 9 do not pass current. To prevent it from stabilizing. When the power supply voltage becomes equal to or lower than the constant current circuit stable operation limit voltage, a bias start signal IBS (here, “Low” level signal) is output to the power-on reset circuit 1a.

  The resistor R11 has one end connected to the high potential side power supply Vdd and the other end connected to the drain of the Nch MOS transistor NT11. Nch MOS transistor NT11 has a gate connected to node N11 and the drain, and a source connected to the drain of Nch MOS transistor NT12. The Nch MOS transistor NT12 has a gate connected to the node N11 and a source connected to the low potential side power supply Vss.

  In the Pch MOS transistor PT11, the source is connected to the high potential side power supply Vdd, the drain is connected to the node N12, and the gate is connected to the node N13. N-channel MOS transistor NT13 has a drain connected to node N13, a source connected to node N12, and a gate connected to node N11. The Nch MOS transistor NT14 has a drain connected to the node N12 and the source of the Nch MOS transistor NT13, a source connected to the low potential power source Vss, and a gate connected to the node N11. Nch MOS transistors NT11 and NT13 constitute a current mirror circuit.

  The constant current circuit 9 is provided with a Pch MOS transistor PT12, a Pch MOS transistor PT13, an Nch MOS transistor NT15, an Nch MOS transistor NT16, and a resistor R12. The constant current circuit 9 starts to supply current to the reference voltage generation unit 7 and the startup circuit 8 when the power supply voltage reaches a certain voltage value. As the current flowing through the Pch MOS transistor PT13 increases, the Pch MOS transistor of the startup circuit 8 The current of PT11 also increases. When the current capability of the Pch MOS transistor PT11 of the start-up circuit 8 exceeds the current capability of the Nch MOS transistor NT14, the voltage at the node N12 rises, and the Nch MOS transistor NT13 is turned “OFF”. The constant current circuit 9 is in a stable state where the startup circuit does not affect the node N13, and supplies a constant current to the reference voltage generation unit 7.

  In the Pch MOS transistor PT12, the source is connected to the high potential side power supply Vdd, the gate is connected to the gate of the Pch MOS transistor PT13, and the drain is connected to the node N16. The Pch MOS transistor PT13 has a source connected to the high potential side power supply Vdd and a gate connected to the drain and the node N15. Here, the Pch MOS transistor PT13 and the Pch MOS transistor PT12, and the Pch MOS transistor PT13 and the Pch MOS transistor PT11 of the start-up circuit 8 each constitute a current mirror circuit.

  The resistor R12 has one end connected to the node N16 and the other end connected to the node N17. The Nch MOS transistor NT15 has a drain connected to the node N17, a source connected to the low potential power source Vss, and a gate connected to the node N16. The Nch MOS transistor NT16 has a drain connected to the node N15, a source connected to the low potential power source Vss, and a gate connected to the node N17.

  The reference voltage generation unit 7 includes a comparator 10, a Pch MOS transistor PT14, a Pch MOS transistor PT15, resistors R13 to R15, a diode D1, and a diode D2.

  The Pch MOS transistor PT14 has a source connected to the high potential side power supply Vdd, a gate connected to the node N15 of the constant current circuit 9, and a source connected to the comparator 10. The Pch MOS transistor PT13 and the Pch MOS transistor PT14 of the constant current circuit 9 constitute a current mirror circuit, and a bias current is supplied to the comparator 10 from the source side of the Pch MOS transistor PT14 when the constant current circuit 9 operates.

  The Pch MOS transistor PT15 has a source connected to the high potential side power supply Vdd and a gate connected to the node N15 of the constant current circuit 9. The Pch MOS transistor PT13 and the Pch MOS transistor PT15 of the constant current circuit 9 constitute a current mirror circuit, and a bias current Ib is output from the source side of the Pch MOS transistor PT15 when the constant current circuit 9 operates.

  The resistor R13 has one end connected to the node N19 on the output side of the comparator 10 and the other end connected to the node N17. The resistor R15 has one end connected to the node N17 and the other end connected to the anode of the diode D1. The diode D1 has a cathode connected to the low potential side power source Vss. A voltage obtained by resistance division is input from the node N17 to the (−) side of the comparator 10. Here, the potential at the other end of the resistor R15 is set higher than the low-potential-side power supply Vss, which is the ground voltage, by Vf (forward voltage) of the diode D1.

  The resistor R14 has one end connected to the node N19 on the output side of the comparator 10 and the other end connected to the node N18. The diode D2 has an anode connected to the node N18 and a cathode connected to the low potential power source Vss. The signal of the node N18 is input to the (+) side of the comparator 10. Here, the potential of the other end of the resistor R14 is set higher than the low-potential-side power source Vss, which is the ground voltage, by Vf (forward voltage) of the diode D2.

  The comparator 10 inputs the signal of the node N17 on the (−) side, inputs the signal of the node 18 on the (+) side, and outputs a signal amplified by comparison as a reference voltage Vref from the node N19.

  Here, in the constant current circuit 9, when the high-potential-side power supply Vdd voltage is equal to or higher than the stable operation limit voltage of the constant current circuit 9, a constant current flows through the Pch MOS transistor PT13, and the node N13 of the startup circuit 8 and the reference voltage generation A “High” level signal as a bias voltage is output to the unit 7.

  When the high-potential-side power supply Vdd voltage is equal to or lower than the stable operation limit voltage of the constant current circuit 9, the start-up circuit 8 flows only a small amount of current through the Pch MOS transistor PT13, and the signal at the node N13 becomes “Low” level. The bias start signal IBS output from the node N12 of “1” becomes “Low” level. On the other hand, when the high-potential-side power supply Vdd voltage is equal to or higher than the stable operation limit voltage of the constant current circuit 9, a constant current flows, so that the current supply capability of the Pch MOS transistor PT11 using the node N13 as a gate input increases. The bias start signal IBS output from the node N12 of the start-up circuit 8 becomes “High” level.

  Similarly, when the high-potential-side power supply Vdd voltage is equal to or lower than the stable operation limit voltage of the constant current circuit 9, the reference voltage generation unit 7 flows only a small current through the Pch MOS transistor PT13, and passes through the source of the Pch MOS transistor PT14. Since the bias current supplied to the comparator 10 is small, the reference voltage Vref output from the comparator 10 is at the “Low” level. On the other hand, when the high-potential-side power supply Vdd voltage is equal to or higher than the stable operation limit voltage of the constant current circuit 9, the constant current circuit 9 operates stably, so that a constant bias current flows through the Pch MOS transistor PT13 and the source of the Pch MOS transistor PT14. Since a constant bias current is supplied to the comparator 10 via the reference voltage Vref, the reference voltage Vref output from the comparator 10 is at the “High” level.

  Next, the operation of the power-on reset circuit will be described with reference to the drawings. FIG. 5 is a timing chart showing the operation of the power-on reset circuit. Here, the operation of the power-on reset circuit when the power supply voltage falls below the constant current circuit stable operation limit voltage from the high-potential-side power supply Vdd voltage and rises again to the high-potential-side power supply Vdd voltage is shown.

  As shown in FIG. 5, when the power source voltage is the high potential side power source Vdd voltage, the low potential side power source Vss level at which the node N1 is the ground voltage, the bias start signal IBS is “High” level, and the reference voltage Vref is “ Since the “High” level and the input voltage Vin are higher than the reference voltage Vref, the output signal of the comparator 4 is at the “Low” level (at this time, the IC or LSI which is a semiconductor integrated circuit operates normally).

  Next, when the power supply voltage starts to decrease and the input voltage decreases to Vin <Vref, the output signal of the comparator 4 becomes “High” level, and a reset pulse is output from the power-on reset circuit 1a.

  Subsequently, when the power supply voltage becomes equal to or lower than the constant current circuit stable operation limit voltage, the reference voltage Vref becomes “Low” level, the bias start signal IBS becomes “Low” level, and the Pch MOS transistor PT2 of the activation time adjustment unit 2a becomes “ON”. “Yes. For this reason, the voltage at the node N1 rises above the low potential side power supply Vss level which is the ground voltage. When the bias start signal IBS is not supplied as indicated by the broken line, the signal at the node N1 remains at the low potential side power supply Vss level which is the ground voltage.

  Then, the power supply voltage reaches a voltage V1 that is equal to or lower than the constant current circuit stable operation limit voltage. When the power supply voltage is the voltage V1, the comparator 4, the comparator 10, the reference voltage generation unit 7, and the like are operating.

  Next, when the power supply voltage starts to rise from the voltage V1, the voltage at the node N1 also starts to rise. When the bias start signal IBS is not supplied as shown by the broken line, the signal at the node N1 rises from the low potential side power supply Vss level which is the ground voltage.

  Subsequently, when the power supply voltage returns to the constant current circuit stable operation limit voltage or higher, the reference voltage Vref becomes “High” level, the bias start signal IBS becomes “High” level, and the Nch MOS transistor NT1 of the start-up time adjusting unit 2a becomes constant. In accordance with the operation of the current source 5, the bias voltage Vb is supplied to the gate, and the operation is started. On the other hand, the Pch MOS transistor PT12 stops operating. At this time, since the power supply voltage is rising, the voltage change at the node N1 is determined by the relationship between the coupling effect of the capacitance of the capacitor C1 and the voltage drop due to the current flowing through the Nch MOS transistor NT1, and changes gently.

  When the voltage difference between the power supply voltage and the node N1 increases and the gate-source voltage (Vgs) of the Pch MOS transistor PT1 becomes larger than the threshold voltage (Vth) (the signal at the node N1 decreases by ΔV from the maximum value). The Pch MOS transistor PT1 is turned “ON”. When the bias start signal IBS is not supplied, the time when the Pch MOS transistor PT1 is “ON” is earlier.

  Next, when the input voltage Vin becomes larger than the reference voltage Vref, the output signal Out output from the comparator 4 becomes “Low” level, and the reset pulse is not output from the power-on reset circuit 1a (release of the reset pulse). As a result, the period during which the reset pulse is output is T2. When the bias start signal IBS is not supplied, the period during which the reset pulse is output is shortened by Δt and becomes T1.

  Here, the power supply voltage is the high potential side power supply Vdd voltage at the time when the signal at the node N1 is the maximum voltage, but the power supply voltage is still at the time when the signal at the node N1 is at the maximum voltage as in the first embodiment. It may be rising. Even in this case, the reset pulse is output as in this embodiment.

  Note that the Pch MOS transistor PT2 serves to hold the signal level of the node N1 at a level higher than the low potential side power supply Vss level, which is the ground voltage, until the constant current circuit starts to operate. For this reason, the influence of the initial signal level of the node N1 and the initial state of the power supply voltage can be reduced. The capacitor C2 and the resistor R3 serve to adjust the gate-source voltage (Vgs) when the Pch MOS transistor PT1 is “ON”. Therefore, it is possible to delay the voltage change of the input voltage Vin, to secure a time for the comparator 4 to determine that the input voltage Vin <the reference voltage Vref more reliably, and to reliably output the reset pulse.

  As described above, in the power-on reset circuit of this embodiment, the start-up time adjusting unit 2a, the comparison voltage generating unit 3a, the comparator 4, the constant current source 5, and the Nch MOS transistor NT5 are provided. When the power supply voltage starts up and rises from 0V, the start-up time adjusting unit 2a supplies a voltage that follows the power supply voltage to the comparison voltage generating unit 3 so that the input voltage Vin and the reference voltage Vref input to the comparator 4 are supplied. Adjust the comparison start time. When the power supply voltage becomes equal to or lower than the constant current circuit stable operation limit voltage, a bias start signal is input to raise the voltage at the node N1 above the low potential side power supply Vss voltage which is the ground voltage. The comparison voltage generator 3 generates a resistance-divided voltage in response to the rise or change of the power supply voltage. The comparator 4 receives the input voltage Vin and the reference voltage Vref, and outputs an output signal Out that has been compared and amplified.

  Therefore, the reset pulse can be stably output even when the power supply voltage rises quickly and it takes time until the reference voltage output from the reference voltage generation circuit is stabilized when the power is turned on. Further, the reset pulse can be stably output even when the power supply voltage falls when the power supply voltage falls below the constant current circuit stable operation limit voltage. Therefore, a stable reset pulse is output from the comparator 4 without depending on the rising or falling speed of the power supply voltage. Also, since it is not necessary to increase the current supplied to the reference voltage generation circuit in order to accelerate the stabilization time of the reference voltage, it is applied to a semiconductor integrated circuit (IC or LSI) such as a microcomputer that requires low power consumption. it can.

  In the present embodiment, the constant current generating unit 6 and the reference voltage generating unit 7 constituted by the start-up circuit 8 and the constant current circuit 9 are provided outside the power-on reset circuit 1a. The voltage generator 7 may be provided inside the power-on reset circuit 1a.

  Next, a power-on reset circuit according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 6 is a circuit diagram showing a power-on reset circuit. In this embodiment, a Schmitt inverter is provided in the power-on reset circuit so that a reset pulse can be output from a low voltage when the power supply voltage rises.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 6, the power-on reset circuit 1b includes a startup time adjustment unit 2a, a comparison voltage generation unit 3a, a comparator 4, a constant current source 5, an Nch MOS transistor NT5, a Schmitt inverter 11, and a 2-input OR circuit 12. Is provided.

  The Schmitt inverter 11 receives the signal of the node N1 and outputs a hysteresis output signal from the node N20. Here, the hysteresis output signal means that when the signal at the node N1 that is the input voltage changes, the input voltage rises from 0V and the input voltage is at the “High” level (the signal at the node N20 that is the output voltage is at the “Low” level). And the voltage that drops from “High” and the input voltage is regarded as “Low” level (the signal at the node N20 as the output voltage is “High” level) are different.

  The 2-input OR circuit 12 receives the output signal Out output from the node N3 of the comparator 4 and the signal output from the node N20 of the Schmitt inverter 11, and outputs a logically operated signal as the output signal Outor.

  Next, the operation of the power-on reset circuit will be described with reference to the drawings. FIG. 7 is a timing chart showing the operation of the power-on reset circuit.

  As shown in FIG. 7, when the power supply voltage rises from 0V, the voltage at the node N1 rises following the power supply voltage due to the capacitance of the capacitor C1 provided in the start-up time adjusting unit 2a. When the power supply voltage is relatively low, the Schmitt inverter 11 starts to operate, and at time ta, the signal at the node N20 on the output side changes from “Low” level to “High” level, and the output of the 2-input OR circuit 12 The signal Outor changes from “Low” level to “High” level. For this reason, the reset pulse is output from the power-on reset circuit 1b after the time ta. Since the gate-source voltage (Vgs) of the Pch MOS transistor PT1 is equal to or lower than the threshold voltage (Vth), the Pch MOS transistor PT1 is “OFF”. Therefore, the input voltage Vin input to (−) of the comparator 4 is the low potential side power supply Vss voltage that is the ground voltage.

  Next, since the rise of the power supply voltage is relatively fast, the reference voltage Vref output from the reference voltage generator rises with a delay from the rise of the power supply voltage, and becomes a constant voltage after time t1. The constant current source 5 is generated based on the constant current generator, and starts to output the bias current Ib after the power supply voltage reaches a certain voltage value. The comparator 4 starts operation by supplying the bias current Ib (from time t1). Since the reference voltage Vref> the input voltage Vin at time t1, the output signal Out output from the comparator 4 is at “High” level, and the signal at the node N20 on the output side of the Schmitt inverter 11 is at “High” level. The output signal Outor of the 2-input OR circuit 12 maintains the “High” level. Since the output signal Outor of the 2-input OR circuit 12 is at “High” level, the reset pulse continues to be output from the power-on reset circuit 1b.

  Subsequently, the bias voltage Vb is supplied to the gate of the Nch MOS transistor NT1 in accordance with the operation of the constant current source 5, and the operation starts in the same manner as the comparator 4. At this time, since the power supply voltage is rising, the voltage change at the node N1 is determined by the relationship between the coupling effect due to the capacitor C1 and the voltage drop due to the current flowing through the Nch MOS transistor NT1, and changes gently. When the voltage difference between the power supply voltage and the node N1 increases and the gate-source voltage (Vgs) of the Pch MOS transistor PT1 becomes larger than the threshold voltage (Vth), the Pch MOS transistor PT1 is turned “ON”. When the Pch MOS transistor PT1 is “ON”, the input voltage Vin starts to rise from the low potential side power supply Vss voltage which is the ground voltage.

  Then, at time tb when the voltage level of N1 rises to some extent together with the power supply voltage, the signal at the output side node N20 of the Schmitt inverter 11 changes from “High” level to “Low” level. Since the signal at the node N20 on the output side of the Schmitt inverter 11 is at the “Low” level and the output signal Out output from the comparator 4 is maintained at the “High” level, the output signal Outor of the 2-input OR circuit 12 is “ At the “High” level, the reset pulse continues to be output from the power-on reset circuit 1b.

  Next, at time t2, since the reference voltage Vref <the input voltage Vin, the output signal Out output from the comparator 4 is at the “Low” level. Since the signal of the node N20 on the output side of the Schmitt inverter 11 is “Low” level and the output signal Out output from the comparator 4 is “Low”, the output signal Out of the 2-input OR circuit 12 becomes “Low” level. The reset pulse output from the power-on reset circuit 1b is stopped. As a result, the period between time ta and time t2 becomes the reset pulse output period (T3).

  As described above, in the power-on reset circuit of this embodiment, the start-up time adjustment unit 2a, the comparison voltage generation unit 3a, the comparator 4, the constant current source 5, the Nch MOS transistor NT5, the Schmitt inverter 11, and the 2-input OR circuit 12 Is provided. When the power supply voltage starts up and rises from 0V, the start-up time adjusting unit 2a supplies a voltage that follows the power supply voltage to the comparison voltage generating unit 3 so that the input voltage Vin and the reference voltage Vref input to the comparator 4 are supplied. Adjust the comparison start time. When the power supply voltage becomes equal to or lower than the constant current circuit stable operation limit voltage, a bias start signal is input to raise the voltage at the node N1 above the low-potential-side power supply Vss voltage that is the ground voltage. The comparison voltage generator 3 generates a resistance-divided voltage in response to the rise or change of the power supply voltage. The comparator 4 receives the input voltage Vin and the reference voltage Vref, and outputs an output signal Out that has been compared and amplified. The Schmitt inverter 11 inputs the signal of the node N1 of the activation time adjustment unit 2a and outputs a hysteresis signal. The 2-input OR circuit 12 inputs the output signal Out of the comparator 4 and the output signal of the Schmitt inverter 11, and outputs a logically operated signal as an output signal of the power-on reset circuit 1b.

  For this reason, when the power supply voltage rises at a relatively low voltage, a “High” level signal is output from the smit inverter 11, and a reset pulse is output.

  Therefore, since the power supply voltage is lower than that in the first embodiment, a stable reset pulse is output without depending on the rising or falling speed of the power supply voltage. Also, since it is not necessary to increase the current supplied to the reference voltage generation circuit in order to accelerate the stabilization time of the reference voltage, it is applied to a semiconductor integrated circuit (IC or LSI) such as a microcomputer that requires low power consumption. it can.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the power-on reset circuit, the constant current generation unit, and the reference voltage generation unit have a CMOS configuration, but the circuit may be configured by BiCMOS or a bipolar transistor. Further, although an inverting comparator (inverting comparator) is used for the power-on reset circuit and the reference voltage generation unit, a non-inverting comparator may be used.

The present invention can be configured as described in the following supplementary notes.
(Supplementary note 1) When a bias start signal for accelerating the operation at power-on is input, a voltage signal higher than the ground voltage is output, and when the power supply voltage rises, a voltage signal that follows the power supply voltage is output, After the power supply voltage becomes equal to or higher than a predetermined voltage, the start time adjustment unit outputs a voltage signal that is gradually stepped down and becomes the ground voltage after a predetermined time, and a voltage signal output from the start time adjustment unit. A comparison voltage generator for outputting the power supply voltage divided at a predetermined ratio as an input voltage, a comparator for inputting a reference voltage and the input voltage for comparison amplification, and a voltage output from the start-up time adjustment unit A Schmitt inverter having a hysteresis characteristic in which signal inversion at the time of rising and falling of the voltage signal is different, and the comparator The output signal output from the Schmitt inverter and the output signal output from the Schmitt inverter are input, and the logical operation is performed and either the output signal output from the comparator or the output signal output from the Schmitt inverter is “High” level. A two-input OR circuit that outputs a reset pulse signal at the time of stopping the reset pulse signal when the output signal output from the comparator and the output signal output from the Schmitt inverter are both at the “Low” level; A power-on reset circuit comprising:

1 is a circuit diagram showing a power-on reset circuit according to Embodiment 1 of the present invention. 3 is a timing chart showing the operation of the power-on reset circuit according to the first embodiment of the present invention. The circuit diagram which shows the power-on reset circuit which concerns on Example 2 of this invention. The circuit diagram which shows the constant current production | generation part and reference voltage production | generation part which concern on Example 2 of this invention. 9 is a timing chart showing the operation of the power-on reset circuit according to the second embodiment of the present invention. FIG. 6 is a circuit diagram showing a power-on reset circuit according to Embodiment 3 of the present invention. 9 is a timing chart showing an operation of a power-on reset circuit according to Embodiment 3 of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1a, 1b Power-on reset circuit 2, 2a Startup time adjustment part 3, 3a Comparison voltage generation part 4, 10 Comparator 5 Constant current source 6 Constant current generation part 7 Reference voltage generation part 8 Startup circuit 9 Constant current circuit 11 Schmidt Inverter 12 Two-input OR circuit C1, C2 Capacitor D1, D2 Diode Ib Bias current IBS Bias start signal N1-5, N11-20 Node NT1-5, NT11-16 Nch MOS transistor Out, Outor output signals PT1, PT2, PT11 15 Pch MOS transistors R 1 to 5, R 11 to 14 Resistor Vb Bias voltage Vdd High potential side power source Vin Input voltage Vref Reference voltage Vss Low potential side power source

Claims (5)

When the power supply voltage rises, a voltage signal that follows the power supply voltage is output, and after the power supply voltage becomes equal to or higher than a predetermined voltage, a voltage signal that is gradually reduced and becomes a ground voltage after a predetermined time is output. A time adjustment unit;
Based on the voltage signal output from the start-up time adjustment unit, a comparison voltage generation unit that outputs the power supply voltage divided at a predetermined ratio as an input voltage;
Input a reference voltage and the input voltage, compare and amplify to output a reset pulse signal when the reference voltage is larger than the input voltage, and output a reset pulse signal when the reference voltage is smaller than the input voltage A comparison amplification means for stopping
A power-on reset circuit comprising: When a bias start signal that accelerates the operation at power-on is input, a voltage signal higher than the ground voltage is output, and when the power supply voltage rises, a voltage signal that follows the power supply voltage is output. A starting time adjusting unit that outputs a voltage signal that is gradually stepped down and becomes the ground voltage after a predetermined time after becoming a predetermined voltage or higher;
Based on the voltage signal output from the start-up time adjustment unit, a comparison voltage generation unit that outputs the power supply voltage divided at a predetermined ratio as an input voltage;
Input a reference voltage and the input voltage, compare and amplify to output a reset pulse signal when the reference voltage is larger than the input voltage, and output a reset pulse signal when the reference voltage is smaller than the input voltage A comparison amplification means for stopping
A power-on reset circuit comprising: When a bias start signal that accelerates the operation at power-on is input, a voltage signal higher than the ground voltage is output, and when the power supply voltage rises, a voltage signal that follows the power supply voltage is output. A starting time adjusting unit that outputs a voltage signal that is gradually stepped down and becomes the ground voltage after a predetermined time after becoming a predetermined voltage or higher;
Based on the voltage signal output from the start-up time adjustment unit, a comparison voltage generation unit that outputs the power supply voltage divided at a predetermined ratio as an input voltage;
A comparison amplification means for inputting a reference voltage and the input voltage and performing comparison amplification;
A Schmitt circuit having a hysteresis characteristic that receives a voltage signal output from the start-up time adjustment unit and has different signal inversion when the voltage signal rises and falls;
The output signal output from the comparison amplification means and the output signal output from the Schmitt circuit are input, and the output signal output from the comparison amplification means and the output signal output from the Schmitt circuit are logically calculated. A reset pulse signal is output when the signal is at “High” level, and a reset pulse signal is output when both the output signal output from the comparison amplification means and the output signal output from the Schmitt circuit are at “Low” level. Logical operation means for stopping
A power-on reset circuit comprising:   4. The comparator according to claim 1, wherein the comparison amplification unit is a comparator that inputs the reference voltage to a (+) side and inputs the input voltage to a (−) side. 5. Power-on reset circuit. A constant current circuit that starts outputting current as the power supply voltage rises and outputs a constant current when the power supply voltage exceeds a predetermined value;
A signal input from the constant current circuit is input, and when the constant current circuit falls below the stable operation limit, a startup circuit that outputs a bias start signal;
A reference voltage generator that operates based on a signal output from the constant current circuit and generates a reference voltage;
When a bias start signal that accelerates the operation at power-on is input, a voltage signal higher than the ground voltage is output, and when the power supply voltage rises, a voltage signal that follows the power supply voltage is output. A starting time adjusting unit that outputs a voltage signal that is gradually stepped down and becomes the ground voltage after a predetermined time after becoming a predetermined voltage or higher;
Based on the voltage signal output from the start time adjustment unit, a comparison voltage generation unit that outputs the power supply voltage divided at a predetermined ratio as an input voltage;
The reference voltage and the input voltage are input, compared and amplified to output a reset pulse signal when the reference voltage is larger than the input voltage, and when the reference voltage is smaller than the input voltage, the reset pulse signal Comparative amplification means for stopping output;
A power-on reset circuit comprising:

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