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JP2007220820A - Thin film transistor array and its manufacturing method - Google Patents

Thin film transistor array and its manufacturing method Download PDF

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JP2007220820A
JP2007220820A JP2006038429A JP2006038429A JP2007220820A JP 2007220820 A JP2007220820 A JP 2007220820A JP 2006038429 A JP2006038429 A JP 2006038429A JP 2006038429 A JP2006038429 A JP 2006038429A JP 2007220820 A JP2007220820 A JP 2007220820A
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thin film
zinc oxide
oxide semiconductor
semiconductor thin
film layer
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JP5015473B2 (en
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Mamoru Furuta
守 古田
Takashi Hirao
孝 平尾
Hiroshi Furuta
寛 古田
Tokiyoshi Matsuda
時宜 松田
Takahiro Hiramatsu
孝浩 平松
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Casio Computer Co Ltd
Kochi Prefecture Sangyo Shinko Center
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Casio Computer Co Ltd
Kochi Prefecture Sangyo Shinko Center
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Abstract

<P>PROBLEM TO BE SOLVED: To change an orientation of zinc oxide whereby an oxide semiconductor thin film layer excels in a heat resistance and surface smoothness, it is intended to suppress a leakage current and enhance a current drive capability, and a pixel electrode excels in a micro processability, thereby highly micronizing pixels. <P>SOLUTION: A thin film transistor array has at least the oxide semiconductor thin film layer having zinc oxide as a main component, formed as a channel on a substrate, and the pixel electrode having zinc oxide as the main component. The orientation of zinc oxide of the oxide semiconductor thin film layer differs from that of the zinc oxide of the pixel electrode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、画素の駆動装置として薄膜トランジスタが機能する薄膜トランジスタアレイに係り、より詳しくは、薄膜トランジスタの構成半導体(活性層)である酸化物半導体薄膜層と画素電極の主成分に酸化亜鉛を用いた薄膜トランジスタアレイに関する。   The present invention relates to a thin film transistor array in which a thin film transistor functions as a pixel driving device, and more specifically, an oxide semiconductor thin film layer that is a constituent semiconductor (active layer) of the thin film transistor and a thin film transistor that uses zinc oxide as a main component of a pixel electrode. For arrays.

酸化亜鉛は優れた半導体(活性層)の性質を示すことから、近年薄膜トランジスタ（以下TFTと略）の半導体薄膜層や画素電極に多く用いられている。
酸化亜鉛を主成分とする半導体薄膜層である酸化物半導体薄膜層を用いたTFT(酸化亜鉛TFT)としては、ボトムゲート型とトップゲート型の構造が考えられる。 Zinc oxide has been widely used in recent years for semiconductor thin film layers and pixel electrodes of thin film transistors (hereinafter abbreviated as TFTs) because it exhibits excellent semiconductor (active layer) properties.
As a TFT (zinc oxide TFT) using an oxide semiconductor thin film layer which is a semiconductor thin film layer containing zinc oxide as a main component, a bottom gate type structure and a top gate type structure are conceivable.

また、従来、酸化物半導体薄膜層の主成分である酸化亜鉛の結晶構造は、基板と垂直方向に結晶粒のＣ軸が揃うこと、換言すれば、Ｃ軸配向性が高いことが望ましいとされていた。その理由は、酸化物半導体薄膜層に用いた場合、電子移動度の優れた薄膜トランジスタ(TFT)を得ることが期待できるからである。
酸化亜鉛に関しては、スパッタリング法にて成膜すると、Ｃ軸配向性の高い膜が得られることはよく知られている。また、従来より、TFTにおいて半導体薄膜層のＣ軸配向性を向上させるための研究は種々なされており、例えば下記特許文献１の開示技術はその一例である。しかしながら、Ｃ軸以外の配向制御やアモルファス状態の形成に関する報告はほとんどされておらず、そのため画素電極もＣ軸配向性の高いものが用いられていた。
しかしながら、Ｃ軸配向性の高い酸化亜鉛を用いた酸化物半導体薄膜層と画素電極には夫々、以下のような問題がある。 Conventionally, the crystal structure of zinc oxide, which is the main component of the oxide semiconductor thin film layer, is desirably aligned with the C axis of crystal grains in the direction perpendicular to the substrate, in other words, having a high C axis orientation. It was. The reason is that when used for an oxide semiconductor thin film layer, a thin film transistor (TFT) having excellent electron mobility can be expected.
Regarding zinc oxide, it is well known that a film having a high C-axis orientation can be obtained by forming a film by sputtering. Conventionally, various studies have been made to improve the C-axis orientation of a semiconductor thin film layer in a TFT. For example, the technology disclosed in Patent Document 1 below is an example. However, there have been few reports on orientation control other than the C axis and formation of an amorphous state, and therefore, pixel electrodes having high C axis orientation have been used.
However, the oxide semiconductor thin film layer and the pixel electrode using zinc oxide having high C-axis orientation have the following problems.

酸化物半導体薄膜層に関しては、酸化亜鉛のＣ軸配向性が高いと、膜厚方向に対して特定の結晶粒径を有する柱状構造をとるため、多くの結晶粒界を有する。結晶粒界には格子欠陥や結晶の歪み、未結合手（ダングリングボンド）等を多く含むため、熱的に不安定な状態にある。そのため、酸化物半導体薄膜層の形成後、ゲート絶縁膜の被覆等のための加熱プロセスを経ることにより、酸化物半導体薄膜層結晶粒界における酸素や亜鉛が脱離し、格子欠陥を形成するという問題が生じる。当該格子欠陥は、電気的に浅い不純物準位を形成し、酸化物半導体薄膜層の低抵抗化を引き起こす。そのため、当該酸化物半導体薄膜層を薄膜トランジスタの活性層に用いた場合、ゲート電圧を印加しなくてもドレイン電流が流れるノーマリーオン型すなわちデプレッション型の動作となり、欠陥準位の増大とともに、しきい電圧が減少し、リーク電流が増大する。また、チャネルの電子に対して結晶粒界はエネルギー障壁として働くため、移動度の低下を引き起こす。
この問題は、ボトムゲート型の薄膜トランジスタより、酸化物半導体薄膜層の上にゲート絶縁膜を被覆するトップゲート型の薄膜トランジスタに顕著に現れる。
また、柱状構造を有することで、酸化物半導体薄膜層の表面の凹凸が大きくなり、ゲート絶縁膜の薄膜化を阻害する。そのため、耐圧不良や電界集中による電流駆動能力の低下といった問題も生じる。 With respect to the oxide semiconductor thin film layer, when the C-axis orientation of zinc oxide is high, the oxide semiconductor thin film layer has a columnar structure having a specific crystal grain size in the film thickness direction, and thus has many crystal grain boundaries. Since the crystal grain boundary contains many lattice defects, crystal distortion, dangling bonds, etc., it is in a thermally unstable state. For this reason, after forming the oxide semiconductor thin film layer, a heating process for covering the gate insulating film, etc. is performed, so that oxygen and zinc at the crystal grain boundary of the oxide semiconductor thin film layer are desorbed and lattice defects are formed. Occurs. The lattice defect forms an electrically shallow impurity level and causes a reduction in resistance of the oxide semiconductor thin film layer. Therefore, when the oxide semiconductor thin film layer is used as an active layer of a thin film transistor, the drain current flows without applying a gate voltage, that is, a normally-on operation, that is, a depletion type operation. The voltage decreases and the leakage current increases. In addition, the crystal grain boundary acts as an energy barrier with respect to the electrons in the channel, which causes a decrease in mobility.
This problem is more apparent in a top gate type thin film transistor in which a gate insulating film is coated on an oxide semiconductor thin film layer than in a bottom gate type thin film transistor.
In addition, by having a columnar structure, unevenness on the surface of the oxide semiconductor thin film layer is increased, which hinders thinning of the gate insulating film. Therefore, problems such as a breakdown voltage failure and a decrease in current driving capability due to electric field concentration also occur.

一方、画素電極に関しては、近年の液晶ディスプレイの画素の高精細化に伴い、高い微細加工性が求められている。しかしながら、酸化亜鉛のＣ軸配向性が高いと、柱状構造を有するため、微細加工時に柱状構造に沿ってエッチングされ、均一な加工形状が得にくいといった問題が生じる。
このように、酸化物半導体薄膜層と画素電極に求められる特性は同じわけではない。 On the other hand, with respect to the pixel electrode, high fine workability is required with the recent high definition of pixels of liquid crystal displays. However, if the C-axis orientation of zinc oxide is high, it has a columnar structure, so that it is difficult to obtain a uniform processed shape because it is etched along the columnar structure during microfabrication.
Thus, the characteristics required for the oxide semiconductor thin film layer and the pixel electrode are not the same.

特許第２７８７１９８号公報Japanese Patent No. 2787198

本発明は、酸化物半導体薄膜層と画素電極の夫々に適した酸化亜鉛を提供することを解決課題とする。具体的には、酸化亜鉛の配向を変化させることで、酸化物半導体薄膜層は、耐熱性、表面平滑性に優れたものとし、リーク電流の抑制、電流駆動能力の向上を図る。一方、画素電極は微細加工性に優れ、画素の高精細化の実現できるものが要求され、しかも、画素電極の抵抗を低いものにすることも要求されているので、これらの要求を解決することを課題とする。   An object of the present invention is to provide zinc oxide suitable for each of an oxide semiconductor thin film layer and a pixel electrode. Specifically, by changing the orientation of zinc oxide, the oxide semiconductor thin film layer has excellent heat resistance and surface smoothness, thereby suppressing leakage current and improving current driving capability. On the other hand, the pixel electrode is required to have excellent microfabrication and to realize high definition of the pixel, and further, it is required to reduce the resistance of the pixel electrode. Is an issue.

請求項１に係る発明は、基板上にチャネルとして形成される酸化亜鉛を主成分とする酸化物半導体薄膜層と、酸化亜鉛を主成分とする画素電極を少なくとも有し、前記酸化物半導体薄膜層の酸化亜鉛の配向と前記画素電極の酸化亜鉛の配向が異なることを特徴とする薄膜トランジスタアレイに関する。   The invention according to claim 1 includes at least an oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on a substrate and a pixel electrode mainly composed of zinc oxide, and the oxide semiconductor thin film layer The present invention relates to a thin film transistor array in which the orientation of zinc oxide is different from the orientation of zinc oxide of the pixel electrode.

請求項２に係る発明は、前記画素電極の主成分である酸化亜鉛が（１００）配向と（１０１）配向からなることを特徴とする請求項１記載の薄膜トランジスタアレイに関する。   The invention according to claim 2 relates to the thin film transistor array according to claim 1, wherein zinc oxide which is a main component of the pixel electrode is composed of (100) orientation and (101) orientation.

請求項３に係る発明は、前記画素電極が酸化亜鉛に対してドナーとなる不純物がドーピングされていることを特徴とする請求項１又は２記載の薄膜トランジスタアレイに関する。   A third aspect of the present invention relates to the thin film transistor array according to the first or second aspect, wherein the pixel electrode is doped with an impurity serving as a donor to zinc oxide.

請求項４に係る発明は、前記酸化物半導体薄膜層の主成分である酸化亜鉛が（００２）配向からなることを特徴とする請求項１乃至３いずれか記載の薄膜トランジスタアレイに関する。   The invention according to claim 4 relates to the thin film transistor array according to any one of claims 1 to 3, wherein zinc oxide which is a main component of the oxide semiconductor thin film layer has a (002) orientation.

請求項５に係る発明は、前記酸化物半導体薄膜層の主成分である酸化亜鉛が（００２）配向と（１０１）配向からなることを特徴とする請求項１乃至３いずれか記載の薄膜トランジスタアレイに関する。   The invention according to claim 5 relates to the thin film transistor array according to any one of claims 1 to 3, wherein zinc oxide which is a main component of the oxide semiconductor thin film layer has (002) orientation and (101) orientation. .

請求項６に係る発明は、基板上に酸化亜鉛を主成分とする酸化物ターゲットを用いて酸化物半導体薄膜層をチャネルとして形成する工程と、該酸化物半導体薄膜層の上表面及び側面を被覆してゲート絶縁膜を形成する工程と、該ゲート絶縁膜の上にゲート電極を積載する工程と、酸化亜鉛を主成分とする酸化物ターゲットを用いて画素電極を形成する工程を有する薄膜トランジスタアレイの製法であって、前記画素電極、或いは該画素電極と前記酸化物半導体薄膜層を成膜する際、前記基板に高周波電力を印加しながら行うことで、該画素電極と該酸化物半導体薄膜層の主成分である酸化亜鉛の配向を制御し、異なるものとすることを特徴とする薄膜トランジスタアレイの製法に関する。   According to a sixth aspect of the present invention, there is provided a step of forming an oxide semiconductor thin film layer as a channel on a substrate using an oxide target composed mainly of zinc oxide, and covering an upper surface and side surfaces of the oxide semiconductor thin film layer A thin film transistor array including a step of forming a gate insulating film, a step of loading a gate electrode on the gate insulating film, and a step of forming a pixel electrode using an oxide target mainly composed of zinc oxide In the manufacturing method, when forming the pixel electrode or the pixel electrode and the oxide semiconductor thin film layer while applying high frequency power to the substrate, the pixel electrode and the oxide semiconductor thin film layer are formed. The present invention relates to a method for manufacturing a thin film transistor array, wherein the orientation of zinc oxide as a main component is controlled to be different.

請求項７に係る発明は、前記画素電極の成膜、或いは該画素電極と前記酸化物半導体薄膜層の成膜をマグネトロンスパッタリング法を用いて行い、前記基板への高周波電力の印加を基板ステージを介して行うことを特徴とする請求項６記載の薄膜トランジスタアレイの製法に関する。   According to a seventh aspect of the present invention, film formation of the pixel electrode or film formation of the pixel electrode and the oxide semiconductor thin film layer is performed using a magnetron sputtering method, and application of high-frequency power to the substrate is performed on a substrate stage. 7. The method of manufacturing a thin film transistor array according to claim 6, wherein

請求項１に係る発明によれば、酸化物半導体薄膜層の主成分である酸化亜鉛の配向と画素電極の主成分である酸化亜鉛の配向が異なるため、夫々に適した酸化亜鉛を提供することができ、高性能の薄膜トランジスタを提供できる。   According to the first aspect of the present invention, since the orientation of zinc oxide, which is the main component of the oxide semiconductor thin film layer, is different from the orientation of zinc oxide, which is the main component of the pixel electrode, zinc oxide suitable for each is provided. And a high-performance thin film transistor can be provided.

請求項２に係る発明によれば、画素電極の主成分である酸化亜鉛が（１００）配向と（１０１）配向を有することで、画素電極の微細加工性が向上し、画素の高精細化が図れる。   According to the invention of claim 2, since the zinc oxide which is the main component of the pixel electrode has the (100) orientation and the (101) orientation, the fine workability of the pixel electrode is improved and the high definition of the pixel is achieved. I can plan.

請求項３に係る発明によれば、画素電極が酸化亜鉛に対してドナーとなる不純物がドーピングされていることにより、画素電極が低抵抗化され、電圧降下を抑制することができる。   According to the third aspect of the present invention, the pixel electrode is doped with an impurity serving as a donor with respect to zinc oxide, so that the resistance of the pixel electrode is reduced and a voltage drop can be suppressed.

請求項４に係る発明によれば、酸化物半導体薄膜層の主成分である酸化亜鉛が（００２）配向からなることで、Ｃ軸配向性が高い酸化亜鉛が得られ、電子移動度の優れた薄膜トランジスタを提供することができる。   According to the invention of claim 4, zinc oxide that is a main component of the oxide semiconductor thin film layer has (002) orientation, so that zinc oxide with high C-axis orientation is obtained, and electron mobility is excellent. A thin film transistor can be provided.

請求項５に係る発明は、酸化物半導体薄膜層の主成分である酸化亜鉛が（００２）配向と（１０１）配向からなることにより、Ｃ軸配向性を崩すことによる電子移動度の低下といった影響が少ない状態で、酸化物半導体薄膜層の表面を平滑化することができるので、ゲート絶縁膜の薄膜化が実現でき、電流駆動能力の優れた薄膜トランジスタとなる。
また、酸化物半導体薄膜層の耐熱性も向上する。そのため、熱処理による酸化亜鉛の成分の脱離に起因する酸化物半導体薄膜層の低抵抗化を防ぐことができ、リーク電流が抑制された薄膜トランジスタとなる。 According to the fifth aspect of the present invention, the zinc oxide, which is the main component of the oxide semiconductor thin film layer, is composed of (002) and (101) orientations. Since the surface of the oxide semiconductor thin film layer can be smoothed in a small amount, the gate insulating film can be thinned and a thin film transistor having excellent current driving capability can be obtained.
In addition, the heat resistance of the oxide semiconductor thin film layer is improved. Therefore, resistance reduction of the oxide semiconductor thin film layer due to desorption of the zinc oxide component due to heat treatment can be prevented, and a thin film transistor in which leakage current is suppressed is obtained.

請求項６に係る発明によれば、高周波電力を印加しながら画素電極の成膜、或いは画素電極と酸化物半導体薄膜層の両方の成膜を行うことで、配向性の制御された、微結晶或いは非晶質の酸化亜鉛を主成分とする画素電極、或いは画素電極と酸化物半導体薄膜層を成膜することができる。そのため、夫々に適した酸化亜鉛を画素電極及び酸化物半導体薄膜層に用いた高性能の薄膜トランジスタアレイを提供できる。   According to the invention of claim 6, the orientation of the microcrystal is controlled by forming the pixel electrode while applying high-frequency power or by forming both the pixel electrode and the oxide semiconductor thin film layer. Alternatively, a pixel electrode containing amorphous zinc oxide as a main component, or a pixel electrode and an oxide semiconductor thin film layer can be formed. Therefore, a high-performance thin film transistor array using zinc oxide suitable for each of the pixel electrode and the oxide semiconductor thin film layer can be provided.

請求項７に係る発明によれば、画素電極、或いは画素電極と酸化物半導体薄膜層の成膜を、マグネトロンスパッタリング法を用いて行い、基板を設置した基板ステージに対して高周波電力を印加することで、配向性の制御された、微結晶或いは非晶質の酸化亜鉛を主成分とする酸化物半導体薄膜層を低電力で成膜することができ、成膜速度を向上させることができる。そのため、夫々に適した酸化亜鉛を主成分とする画素電極及び酸化物半導体薄膜層を、低電力で、且つ速い成膜速度で形成することができる。   According to the seventh aspect of the present invention, the pixel electrode or the pixel electrode and the oxide semiconductor thin film layer are formed using the magnetron sputtering method, and high frequency power is applied to the substrate stage on which the substrate is installed. Thus, the orientation-controlled oxide semiconductor thin film layer mainly composed of microcrystalline or amorphous zinc oxide can be deposited with low power, and the deposition rate can be improved. Therefore, a pixel electrode and an oxide semiconductor thin film layer mainly composed of zinc oxide, which are suitable for each, can be formed with low power and a high film formation rate.

本発明の一実施例に係る薄膜トランジスタについて、図１に基づいて以下に説明する。
なお、本発明に係る薄膜トランジスタアレイは該実施例の構造によって、何ら限定されるものではない。該実施例に係る薄膜トランジスタアレイは、TFTがトップゲート型構造であるが、ボトムゲート型構造のTFTも当然含まれるし、トップゲート型のその他の構造も当然含まれる。
また、明細書中では、酸化亜鉛の配向性を（００２）配向、（１００）配向、（１０１）配向というようにミラー指数で表している。なお、これを六方晶用指数で表すと以下のようになる。 A thin film transistor according to an embodiment of the present invention will be described below with reference to FIG.
The thin film transistor array according to the present invention is not limited by the structure of the embodiment. In the thin film transistor array according to the embodiment, the TFT has a top gate type structure, but a bottom gate type TFT is naturally included, and other top gate type structures are naturally included.
In the specification, the orientation of zinc oxide is expressed by the Miller index such as (002) orientation, (100) orientation, and (101) orientation. This can be expressed as the hexagonal index as follows.

Figure 2007220820
Figure 2007220820

本発明の一実施例に係る薄膜トランジスタ１００は、基板１、一対のソース・ドレイン電極２、酸化物半導体薄膜層３、第一ゲート絶縁膜４、コンタクト部５ａ、第二ゲート絶縁膜６、ゲート電極７、一対のソース・ドレイン外部電極２ａ、画素電極８を有しており、図１に示すように、これら各構成を積層して形成されている。   A thin film transistor 100 according to an embodiment of the present invention includes a substrate 1, a pair of source / drain electrodes 2, an oxide semiconductor thin film layer 3, a first gate insulating film 4, a contact portion 5a, a second gate insulating film 6, and a gate electrode. 7, a pair of source / drain external electrodes 2a and a pixel electrode 8 are formed, and these components are laminated as shown in FIG.

薄膜トランジスタ１００は、図１に示す通り、ガラス（SiO2とAl2O3を主成分とする無アルカリガラス）からなる基板１上に形成される。
基板１の材料は、ガラスに限定されず、プラスチックや金属箔に絶縁体をコーティングしたもの等、絶縁体であれば使用可能である。 As shown in FIG. 1, the thin film transistor 100 is formed on a substrate 1 made of glass (non-alkali glass containing SiO 2 and Al 2 O 3 as main components).
The material of the substrate 1 is not limited to glass, and any material can be used as long as it is an insulator such as a plastic or metal foil coated with an insulator.

基板１上には、一対のソース・ドレイン電極２が積層されている。この一対のソース・ドレイン電極２は、基板１上面に間隙を有して配置されている。
ソース・ドレイン電極２は、例えば、インジウムスズ酸化物(ITO)、n＋ZnO等の導電性酸化物、金属、もしくは前記導電性酸化物により少なくとも一部を被覆された金属により形成される。 A pair of source / drain electrodes 2 are stacked on the substrate 1. The pair of source / drain electrodes 2 are disposed on the upper surface of the substrate 1 with a gap.
The source / drain electrode 2 is formed of, for example, a conductive oxide such as indium tin oxide (ITO) or n + ZnO, a metal, or a metal at least partially covered with the conductive oxide.

酸化物半導体薄膜層３は、基板１と一対のソース・ドレイン電極２上に積層されている。
酸化物半導体薄膜層３は、一対のソース・ドレイン電極２の電極間にチャネルを形成するように配置されており、酸化亜鉛を主成分とする酸化物半導体から形成されている。ここで、酸化亜鉛を主成分とする酸化物半導体とは、真性の酸化亜鉛の他、Li、Na、N、C等のp型ドーパントおよびB、Al、Ga、In等のn型ドーパントがドーピングされた酸化亜鉛およびMg、Be等がドーピングされた酸化亜鉛を含む。
酸化物半導体薄膜層３は、主成分である酸化亜鉛が（００２）配向からなるもの、換言するとＣ軸配向性が高いものが考えられる。Ｃ軸配向性が高いことにより、電子移動度の優れた薄膜トランジスタを提供することができる。
また、主成分である酸化亜鉛が（００２）配向と（１０１）配向からなるものも考えられる。この場合、（００２）配向により生じるＸ線回折強度Ｉ（００２）の（１０１）配向により生じるＸ線回折強度Ｉ（１０１）に対する比率Ｉ（００２）／Ｉ（１０１）が２以下であるものが好ましい。このような酸化物半導体薄膜層を利用することで、Ｃ軸配向を崩すことによる電子移動度の低下などの影響が少ない状態で、表面の平滑化が図れ、ゲート絶縁膜の薄膜化が実現できるので電流駆動能力の優れた薄膜トランジスタとなる。また、耐熱性が向上し、酸化物半導体薄膜層の低抵抗化を抑制できるので、リーク電流を抑えることができる。 The oxide semiconductor thin film layer 3 is stacked on the substrate 1 and the pair of source / drain electrodes 2.
The oxide semiconductor thin film layer 3 is disposed so as to form a channel between the pair of source / drain electrodes 2, and is formed of an oxide semiconductor containing zinc oxide as a main component. Here, the oxide semiconductor containing zinc oxide as a main component is doped with intrinsic zinc oxide, p-type dopants such as Li, Na, N, and C, and n-type dopants such as B, Al, Ga, and In. And zinc oxide doped with Mg, Be and the like.
The oxide semiconductor thin film layer 3 may be one in which zinc oxide as a main component has a (002) orientation, in other words, one having a high C-axis orientation. Due to the high C-axis orientation, a thin film transistor with excellent electron mobility can be provided.
Moreover, the thing in which the main component zinc oxide consists of (002) orientation and (101) orientation is also considered. In this case, the ratio I (002) / I (101) of the X-ray diffraction intensity I (002) generated by the (002) orientation to the X-ray diffraction intensity I (101) generated by the (101) orientation is 2 or less. preferable. By using such an oxide semiconductor thin film layer, the surface can be smoothed and the thickness of the gate insulating film can be reduced in a state where there is little influence such as a decrease in electron mobility caused by breaking the C-axis orientation. Therefore, a thin film transistor having excellent current driving capability is obtained. In addition, since heat resistance is improved and resistance reduction of the oxide semiconductor thin film layer can be suppressed, leakage current can be suppressed.

第一ゲート絶縁膜４は、酸化物半導体薄膜層３の上側表面のみを被覆するように形成されている。この第一ゲート絶縁膜４は、ゲート絶縁膜の一部として設けられ、酸化物半導体薄膜層３を製造工程でのレジスト剥離液から保護する保護膜としての役割をも果たすものである。第一ゲート絶縁膜４の厚みは、特に限定されないが、例えば、20〜100nm、好ましくは約50nmに形成される。
第二ゲート絶縁膜６は、一対のソース・ドレイン電極２、酸化物半導体薄膜層３側面及び第一ゲート絶縁膜４の表面全面を被覆するように積層されている。このように、第二ゲート絶縁膜６が積層されることにより、酸化物半導体薄膜層３表面を第一ゲート絶縁膜４にて、側面を第二ゲート絶縁膜６にて完全に被覆することができる。
第二ゲート絶縁膜６の厚みは、例えば、200〜400nmに形成され、好ましくは、約300nmに形成される。 The first gate insulating film 4 is formed so as to cover only the upper surface of the oxide semiconductor thin film layer 3. The first gate insulating film 4 is provided as a part of the gate insulating film, and also serves as a protective film for protecting the oxide semiconductor thin film layer 3 from a resist stripping solution in the manufacturing process. The thickness of the first gate insulating film 4 is not particularly limited, but is, for example, 20 to 100 nm, preferably about 50 nm.
The second gate insulating film 6 is laminated so as to cover the pair of source / drain electrodes 2, the side surfaces of the oxide semiconductor thin film layer 3, and the entire surface of the first gate insulating film 4. Thus, by laminating the second gate insulating film 6, the surface of the oxide semiconductor thin film layer 3 can be completely covered with the first gate insulating film 4 and the side surface can be completely covered with the second gate insulating film 6. it can.
The thickness of the second gate insulating film 6 is formed, for example, to 200 to 400 nm, and preferably about 300 nm.

第一ゲート絶縁膜４及び第二ゲート絶縁膜６は、酸化珪素（SiOx）膜、酸窒化珪素（SiON）膜、窒化珪素（SiNx）膜あるいは窒化珪素（SiNx）に酸素もしくは酸素を構成元素に含む化合物を用いて酸素をドーピングした膜により形成される。この第一ゲート絶縁膜４及び第二ゲート絶縁膜６としては、酸化珪素化合物（SiOx）や酸窒化珪素（SiON）に比較して誘電率の大きい、SiNxに酸素あるいは酸素を構成元素として含む化合物、例えばN2O、を用いて酸素をドーピングした膜が好ましく用いられる。
第一ゲート絶縁膜４及び第二ゲート絶縁膜６は、例えばプラズマ化学気相成長（PCVD)法により形成される。このとき、プラズマ化学気相成長（PCVD)法による成膜は酸化物半導体薄膜層の還元もしくは酸化亜鉛の成分の脱離が生じない基板温度である200℃以上400℃以下で実施することが望ましい。 The first gate insulating film 4 and the second gate insulating film 6 are composed of silicon oxide (SiOx) film, silicon oxynitride (SiON) film, silicon nitride (SiNx) film or silicon nitride (SiNx) with oxygen or oxygen as a constituent element. It is formed by a film doped with oxygen using a compound containing it. As the first gate insulating film 4 and the second gate insulating film 6, a compound having a dielectric constant larger than that of a silicon oxide compound (SiOx) or silicon oxynitride (SiON) and containing oxygen or oxygen as a constituent element in SiNx For example, a film doped with oxygen using N 2 O is preferably used.
The first gate insulating film 4 and the second gate insulating film 6 are formed by plasma chemical vapor deposition (PCVD), for example. At this time, it is desirable that the film formation by plasma enhanced chemical vapor deposition (PCVD) is performed at a substrate temperature of 200 ° C. or more and 400 ° C. or less that does not cause reduction of the oxide semiconductor thin film layer or desorption of zinc oxide components. .

一対のソース・ドレイン外部電極２ａはそれぞれに対応するソース・ドレイン電極２とコンタクト部５ａを介して接続される。   The pair of source / drain external electrodes 2a are connected to the corresponding source / drain electrodes 2 via contact portions 5a.

ゲート電極７は、第二ゲート絶縁膜６上に形成されている。このゲート電極７は、薄膜トランジスタに印加するゲート電圧により酸化物半導体薄膜層３中の電子密度を制御する役割を果たすものである。
ゲート電極７はCr、Tiに例示される金属膜からなる。 The gate electrode 7 is formed on the second gate insulating film 6. The gate electrode 7 serves to control the electron density in the oxide semiconductor thin film layer 3 by a gate voltage applied to the thin film transistor.
The gate electrode 7 is made of a metal film exemplified by Cr and Ti.

画素電極８は、液晶ディスプレイに用いる液晶に薄膜トランジスタを介して電圧を印加するために形成される。なお、図１では、省略されているが、画素電極８は第二ゲート絶縁膜６上をゲート電極７と逆方向に延出されている。
画素電極８は、酸化亜鉛を主成分とする酸化物半導体から形成されている。ここで、酸化亜鉛を主成分とする酸化物半導体とは、真性の酸化亜鉛も含まれるが、酸化亜鉛に対してドナーとなる不純物をドーピングしたものである方が好ましい。これにより、画素電極を低抵抗化することができ、電圧降下を抑制できるからである。
ドナーとなる不純物としては、ガリウムやアルミニウムなどが例示できる。
本発明において、画素電極８の酸化亜鉛の配向は酸化物半導体薄膜層の酸化亜鉛の配向と異なるものを使用する。
画素電極８は、主成分である酸化亜鉛が（１００）配向と（１０１）配向からなるものを使用してもよい。この場合、（１０１）配向により生じるＸ線回折強度Ｉ（１０１）の（１００）配向により生じるＸ線回折強度Ｉ（１００）に対する比率Ｉ（１０１）／Ｉ（１００）が0．5以上5以下であるものが好ましい。このような酸化亜鉛を画素電極に用いることで、微細加工性が向上し、近年の液晶ディスプレイの画素の高精細化に対応したものとすることができる。 The pixel electrode 8 is formed in order to apply a voltage to the liquid crystal used in the liquid crystal display via a thin film transistor. Although omitted in FIG. 1, the pixel electrode 8 extends on the second gate insulating film 6 in the opposite direction to the gate electrode 7.
The pixel electrode 8 is formed from an oxide semiconductor whose main component is zinc oxide. Here, the oxide semiconductor containing zinc oxide as a main component includes intrinsic zinc oxide, but it is preferable that zinc oxide is doped with an impurity serving as a donor. This is because the resistance of the pixel electrode can be reduced and the voltage drop can be suppressed.
Examples of the impurity serving as a donor include gallium and aluminum.
In the present invention, the zinc oxide orientation of the pixel electrode 8 is different from the zinc oxide orientation of the oxide semiconductor thin film layer.
The pixel electrode 8 may be made of zinc oxide, which is a main component, having (100) orientation and (101) orientation. In this case, the ratio I (101) / I (100) of the X-ray diffraction intensity I (101) generated by the (101) orientation to the X-ray diffraction intensity I (100) generated by the (100) orientation is 0.5 or more and 5 or less. Are preferred. By using such zinc oxide for the pixel electrode, the fine workability is improved, and it can be adapted to the recent high definition of the pixel of the liquid crystal display.

本発明の一実施例に係る薄膜トランジスタ（TFT）の製造方法について、図２に基づいて以下に説明する。   A method of manufacturing a thin film transistor (TFT) according to an embodiment of the present invention will be described below with reference to FIG.

まず、図２（１）に示される如く、ガラス基板１上全面にマグネトロンスパッタリング法等により、Ti、Cr等の金属薄膜を例えば100nmの厚みで形成した後、この薄膜に、フォトリソグラフィー法を用いることにより一対のソース・ドレイン電極２を形成する。   First, as shown in FIG. 2A, after a metal thin film such as Ti or Cr is formed to a thickness of, for example, 100 nm on the entire surface of the glass substrate 1 by a magnetron sputtering method or the like, a photolithography method is used for this thin film. Thereby, a pair of source / drain electrodes 2 is formed.

図２（２）に示される如く、前記ガラス基板１および一対のソース・ドレイン電極２上の全面に酸化物半導体薄膜層３として酸化亜鉛を主成分とする半導体薄膜、好適には真性酸化亜鉛(ZnO)を、例えば30〜100nm程度の膜厚でマグネトロンスパッタリング法にて形成する。   As shown in FIG. 2 (2), a semiconductor thin film mainly composed of zinc oxide as an oxide semiconductor thin film layer 3 is formed on the entire surface of the glass substrate 1 and the pair of source / drain electrodes 2, preferably intrinsic zinc oxide ( ZnO) is formed by a magnetron sputtering method with a film thickness of about 30 to 100 nm, for example.

本発明では、酸化亜鉛を主成分とする酸化物半導体薄膜３を成膜する工程において、マグネトロンスパッタリング法を用いて（００２）方向に優先配向した薄膜を成膜することが考えられる。これにより、電子移動度の優れた薄膜トランジスタとなる。
また、本発明は同工程において、マグネトロンスパッタリングの成膜時に基板に高周波電力を印加することで酸化亜鉛を主成分とする半導体薄膜層の配向性を制御し、（００２）配向と（１０１）配向からなるよう成膜することも考えられる。具体的には、酸化物ターゲットに印加する高周波電力（本実施例では13．56MHzの高周波電力を180Ｗで印加）に対して、基板側に高周波電力（本実施例では13．56MHzの高周波電力）を印加する。なお、ターゲットに印加する高周波電力を投入電力、基板側に印加する高周波電力をバイアス電力とする。
バイアス電力を、約1〜10W、好ましくは約1〜5Wとすることで、Ｉ（００２）／Ｉ（１０１）が2以下の酸化物半導体薄膜層となる。このような酸化物半導体薄膜層を利用することで、酸化物半導体薄膜層表面の平滑化が図れ、ゲート絶縁膜の薄膜化が実現できる。そのため、電流駆動能力の優れた薄膜トランジスタとなる。また、耐熱性も向上し、酸化物半導体薄膜層の低抵抗化を抑制し、リーク電流を抑えることができる。なお、バイアス電力の下限は１Wに限定されるわけではなく、上記効果を有する電力であれば、１Ｗ未満の電力も当然含まれる。
上記したようなバイアス電力の印加による配向性の制御については、後述する実験例で図３を参照しつつ、詳細に説明する。
なお、酸化亜鉛の配向を制御する方法は、バイアス電力を印加する方法に限られず、他の成膜条件で制御することも可能である。 In the present invention, in the step of forming the oxide semiconductor thin film 3 containing zinc oxide as a main component, it is conceivable to form a thin film preferentially oriented in the (002) direction by using a magnetron sputtering method. Thereby, a thin film transistor having excellent electron mobility is obtained.
Further, in the same process, the present invention controls the orientation of the semiconductor thin film layer mainly composed of zinc oxide by applying high-frequency power to the substrate at the time of magnetron sputtering film formation, and (002) orientation and (101) orientation. It is also conceivable to form the film so as to consist of Specifically, the high frequency power applied to the oxide target (in this embodiment, 13.56 MHz high frequency power is applied at 180 W) is applied to the substrate side (high frequency power of 13.56 MHz in this embodiment). Apply. The high frequency power applied to the target is input power, and the high frequency power applied to the substrate side is bias power.
By setting the bias power to about 1 to 10 W, preferably about 1 to 5 W, an oxide semiconductor thin film layer having I (002) / I (101) of 2 or less is obtained. By using such an oxide semiconductor thin film layer, the surface of the oxide semiconductor thin film layer can be smoothed, and a thin gate insulating film can be realized. Therefore, the thin film transistor has excellent current driving capability. In addition, heat resistance can be improved, resistance reduction of the oxide semiconductor thin film layer can be suppressed, and leakage current can be suppressed. Note that the lower limit of the bias power is not limited to 1 W, and naturally power of less than 1 W is included as long as the power has the above effects.
The orientation control by applying the bias power as described above will be described in detail in an experimental example described later with reference to FIG.
Note that the method of controlling the orientation of zinc oxide is not limited to the method of applying bias power, and can be controlled by other film forming conditions.

図２（３）に示される如く、酸化物半導体薄膜層３上に低抵抗化されない手法および条件で第一ゲート絶縁膜４を形成する。
第一ゲート絶縁膜４の形成方法の一例として、プラズマ化学気相成長（PCVD）法でSiNxを20〜50nm厚で形成する方法が挙げられる。条件例としては、基板温度250℃でNH3とSiH4の混合ガスをNH3がSiH4の４倍の流量となるように調整して行うことが例示される。 As shown in FIG. 2 (3), the first gate insulating film 4 is formed on the oxide semiconductor thin film layer 3 by a technique and conditions that do not reduce the resistance.
An example of a method for forming the first gate insulating film 4 is a method of forming SiNx with a thickness of 20 to 50 nm by plasma enhanced chemical vapor deposition (PCVD). An example of the condition is that the mixed gas of NH 3 and SiH 4 is adjusted at a substrate temperature of 250 ° C. so that NH 3 has a flow rate four times that of SiH 4 .

図２（４）に示される如く、前記第一ゲート絶縁膜４上にフォトレジストをコーティングし、パターニングされたフォトレジスト４ａを形成し、このフォトレジスト４ａをマスクとして、前記第一ゲート絶縁膜４をSF6等のガスを用いてドライエッチングし、次いで0．2％HNO3溶液にて酸化物半導体薄膜層３に対しウェットエッチングを行う。 As shown in FIG. 2 (4), a photoresist is coated on the first gate insulating film 4 to form a patterned photoresist 4a. Using the photoresist 4a as a mask, the first gate insulating film 4 is formed. Is dry-etched using a gas such as SF 6 and then wet etching is performed on the oxide semiconductor thin film layer 3 with a 0.2% HNO 3 solution.

図２（５）は前記酸化物半導体薄膜層３のウェットエッチング後にフォトレジスト４ａを除去した断面図を示しており、酸化物半導体薄膜層３と同一形状の第一ゲート絶縁膜４を有するTFT活性層領域が形成されている。第一ゲート絶縁膜４は、酸化物半導体薄膜層３との界面形成に加えて、活性領域をパターン形成する時の酸化物半導体薄膜層を保護する役目も同時に果たしている。すなわち、活性層パターニング後のフォトレジスト４ａを剥離する場合に使用するレジスト剥離液が酸化物半導体薄膜層３表面に接すると、薄膜表面や結晶粒界をエッチングで荒らしてしまうが、第一ゲート絶縁膜４が酸化物半導体薄膜層３表面に存在することで、フォトリソグラフィー工程におけるレジスト剥離液といった各種薬液に対する保護膜としての機能を果たし、酸化物半導体薄膜層３の表面あれを防ぐことができる。   FIG. 2 (5) shows a cross-sectional view in which the photoresist 4 a is removed after wet etching of the oxide semiconductor thin film layer 3, and the TFT active having the first gate insulating film 4 having the same shape as the oxide semiconductor thin film layer 3. A layer region is formed. In addition to forming an interface with the oxide semiconductor thin film layer 3, the first gate insulating film 4 also plays a role of protecting the oxide semiconductor thin film layer when patterning the active region. That is, if the resist stripping solution used for stripping the photoresist 4a after patterning the active layer contacts the surface of the oxide semiconductor thin film layer 3, the surface of the thin film and the crystal grain boundary are roughened by etching, but the first gate insulation The presence of the film 4 on the surface of the oxide semiconductor thin film layer 3 serves as a protective film against various chemicals such as a resist stripping solution in a photolithography process, and can prevent surface roughness of the oxide semiconductor thin film layer 3.

TFT活性層領域のパターン形成後、図２（６）に示す如く、前記第一ゲート絶縁膜４および一対のソース・ドレイン電極２を被覆するように、前記基板１、一対のソース・ドレイン電極２、酸化物半導体薄膜層３、および第一ゲート絶縁膜４上全面に第二ゲート絶縁膜６を形成し、その後フォトリソグラフィー法を用いてソース・ドレイン電極２上にコンタクトホール５を開口する。この場合、第二ゲート絶縁膜６は第一ゲート絶縁膜４（界面制御型絶縁膜）と同様な条件で、プラズマ化学気相成長（PCVD）法を用いて形成することが望ましい。   After the patterning of the TFT active layer region, as shown in FIG. 2 (6), the substrate 1, the pair of source / drain electrodes 2 so as to cover the first gate insulating film 4 and the pair of source / drain electrodes 2 are covered. Then, a second gate insulating film 6 is formed on the entire surface of the oxide semiconductor thin film layer 3 and the first gate insulating film 4, and then a contact hole 5 is opened on the source / drain electrode 2 by using a photolithography method. In this case, it is desirable that the second gate insulating film 6 be formed using a plasma enhanced chemical vapor deposition (PCVD) method under the same conditions as the first gate insulating film 4 (interface control type insulating film).

その後、図２（７）に示す如く、前記第二ゲート絶縁膜６上にCr、Tiといった金属膜からなるゲート電極７を形成し、ゲート電極７と同一材料にて一対のソース・ドレイン外部電極２ａをコンタクト部５aを介してそれぞれに対応するソース・ドレイン電極２と接続するよう形成する。   Thereafter, as shown in FIG. 2 (7), a gate electrode 7 made of a metal film such as Cr or Ti is formed on the second gate insulating film 6, and a pair of source / drain external electrodes are made of the same material as the gate electrode 7. 2a is formed so as to be connected to the corresponding source / drain electrode 2 through the contact portion 5a.

最後に、図（８）に示す如く、酸化亜鉛を主成分とする画素電極８を形成する。このとき、マグネトロンスパッタリング法を用い、酸化物半導体薄膜層３の形成と同様に、投入電力（本実施例では13．56MHzの高周波電力を180Ｗで印加）に対して、バイアス電力（本実施例では13．56MHzの高周波電力）を基板に印加する。このとき、バイアス電力の値が10Wすなわち投入電力に対するバイアス電力の比率が5％を超えると酸化物半導体薄膜の配向状態が変化し、バイアス電力比率5％以下で見られた（００２）と（１０１）配向から（１００）と（１０１）配向に変化した。バイアス電力の投入電力に対する比率を5％以上に設定することで、Ｉ（１００）／Ｉ（１０１）が0．5以上5以下である酸化物半導体薄膜層が得られる。それにより、微細加工性に優れた画素電極が得られ、画素の高精細化が実現できる。但し、前記した投入電力に対するバイアス電力の比率である5％という値は、後述する実験例の条件下での値であり、装置の構成やバイアス電力の周波数などによって変わるものである。
また、画素電極８に酸化亜鉛に対してドナーとなる不純物をドーピングしてもよい。これにより、画素電極を低抵抗化することができ、電圧降下を抑制できる。
ドナーとなる不純物としては、ガリウムやアルミニウムなどが例示できる。 Finally, as shown in FIG. 8 (8), the pixel electrode 8 mainly composed of zinc oxide is formed. At this time, using the magnetron sputtering method, as in the formation of the oxide semiconductor thin film layer 3, the bias power (in this example, 13.56 MHz high frequency power is applied at 180 W) with respect to the input power (in this example, 13. Apply 56MHz high frequency power) to the substrate. At this time, when the value of the bias power is 10 W, that is, when the ratio of the bias power to the input power exceeds 5%, the orientation state of the oxide semiconductor thin film changes, and (002) and (101) were observed when the bias power ratio was 5% or less. ) Orientation changed to (100) and (101) orientation. By setting the ratio of bias power to input power to 5% or more, an oxide semiconductor thin film layer having I (100) / I (101) of 0.5 to 5 can be obtained. Thereby, a pixel electrode excellent in fine workability can be obtained, and high definition of the pixel can be realized. However, the value of 5%, which is the ratio of the bias power to the input power described above, is a value under the conditions of an experimental example described later, and changes depending on the configuration of the apparatus, the frequency of the bias power, and the like.
Further, the pixel electrode 8 may be doped with an impurity serving as a donor with respect to zinc oxide. Thereby, the resistance of the pixel electrode can be reduced, and the voltage drop can be suppressed.
Examples of the impurity serving as a donor include gallium and aluminum.

試験例Test example

以下、本発明に係る薄膜トランジスタアレイの酸化物半導体薄膜層及び画素電極を評価するための実験例を示すことにより、本発明の効果をより明確なものとする。なお、当該実験で使用する酸化亜鉛を主成分とする薄膜層（以下、被験体と称す）は、マグネトロンスパッタリング法を用いて、ターゲットに印加する13．56MHzの投入電力（180Ｗ）に対して、基板側に印加する13．56MHzのバイアス電力を変化させて成膜した。   Hereinafter, the effect of the present invention will be made clearer by showing experimental examples for evaluating the oxide semiconductor thin film layer and the pixel electrode of the thin film transistor array according to the present invention. In addition, the thin film layer (henceforth a test subject) which has the zinc oxide used as the main component in the said experiment is 13.56 MHz input power (180 W) applied to a target using a magnetron sputtering method, The film was formed by changing the bias power of 13.56 MHz applied to the substrate side.

図３は被験体の主成分である酸化亜鉛の成膜時に印加するバイアス電力を変化させてＸ線回折強度を測定した図である。具体的には、バイアス電力を0Ｗ，1Ｗ，2Ｗ，5Ｗ，10Ｗ，20Ｗ，40Ｗ，80Ｗと変化させ、被験体を成膜した。   FIG. 3 is a diagram in which the X-ray diffraction intensity is measured by changing the bias power applied during the formation of zinc oxide, which is the main component of the subject. Specifically, the subject was deposited by changing the bias power to 0 W, 1 W, 2 W, 5 W, 10 W, 20 W, 40 W, and 80 W.

バイアス電力を印加しなかった場合、（００２）配向以外は検出できなかった。
バイアス電力を1W印加した場合、（００２）配向が減少し、（１０１）配向が生じることが示された。１W以下の状態はバイアス電力の印加に用いた高周波電源の設定精度の関係で確認できなかったが、１W以下の微小なバイアス電力の印加でも同様の効果が得られるものと考えられる。
バイアス電力が1W以上10W未満の領域では、Ｉ（００２）／Ｉ（１０１）が2以下の被験体となることが示された。このような被験体は表面の平滑化し、耐熱性も向上するので、酸化物半導体薄膜層として好適に利用できる。
また、バイアス電力の値が10Wすなわち投入電力に対するバイアス電力の比率が5％を超えると被験体の配向状態が変化し、バイアス電力比率5％以下で見られた（００２）配向と（１０１）配向からなる状態から（１００）配向と（１０１）配向からなる状態に変化し、I（１００）／Ｉ（１０１）が0．5以上5以下である被験体となることが示された。このような被験体は、微細加工性が向上したものとなり、画素電極に好適に利用できる。 When no bias power was applied, it was not possible to detect other than (002) orientation.
It was shown that when (1) bias power was applied, (002) orientation decreased and (101) orientation occurred. The state of 1 W or less could not be confirmed due to the setting accuracy of the high frequency power source used for applying the bias power, but it is considered that the same effect can be obtained by applying a minute bias power of 1 W or less.
In the region where the bias power is 1 W or more and less than 10 W, it was shown that I (002) / I (101) is a subject having 2 or less. Since such a subject smoothes the surface and improves heat resistance, it can be suitably used as an oxide semiconductor thin film layer.
In addition, when the bias power value is 10 W, that is, when the ratio of the bias power to the input power exceeds 5%, the orientation state of the subject changes, and the (002) orientation and the (101) orientation observed when the bias power ratio is 5% or less. The state was changed from the state consisting of (100) orientation to the state consisting of (101) orientation, indicating that I (100) / I (101) was a test subject having a ratio of 0.5 or more and 5 or less. Such a subject has improved microfabrication and can be suitably used for a pixel electrode.

次いで、本発明に係る酸化物半導体薄膜層の表面平滑性について検証する。
図４（ａ）及び（ｂ）は順にバイアス電力を0Ｗ，5Ｗ印加したときの酸化亜鉛薄膜断面の透過電子顕微鏡（TEM）像を示した写真である。
バイアス電力を0Ｗ印加したとき、つまりバイアス電力を印加しないときにはC軸（００２）配向に起因すると見られる柱状の結晶構造が観察でき、表面の凹凸が激しい。
一方、バイアス電力を5Ｗ印加した断面TEM像からは、被験体がC軸配向性を残してはいるものの微結晶化して、表面が平滑化されていることが確認できる。このような表面平滑性に優れた被験体を酸化物半導体薄膜層としてTFTに用いた場合、ゲート絶縁膜の薄膜化が実現でき、電流駆動能力の優れた薄膜トランジスタとなる。 Next, the surface smoothness of the oxide semiconductor thin film layer according to the present invention will be verified.
FIGS. 4A and 4B are photographs showing transmission electron microscope (TEM) images of zinc oxide thin film sections when bias powers of 0 W and 5 W were sequentially applied.
When a bias power of 0 W is applied, that is, when no bias power is applied, a columnar crystal structure that can be attributed to the C-axis (002) orientation can be observed, and the surface irregularities are severe.
On the other hand, from the cross-sectional TEM image to which 5 W of bias power was applied, it can be confirmed that the subject was microcrystallized although the C-axis orientation remained, and the surface was smoothed. When such a subject having excellent surface smoothness is used for a TFT as an oxide semiconductor thin film layer, a thin gate insulating film can be realized, and a thin film transistor having excellent current driving capability can be obtained.

次いで、本発明に係る酸化物半導体薄膜層の耐熱性について検証する。
図５（ａ）及び（ｂ）はバイアス電力を0Ｗ印加したときの被験体を用い、昇温脱離法(TDS)により酸化亜鉛の成分であるZnの脱離量の測定を行った結果を示した図である。また、図６（ａ）及び（ｂ）はバイアス電力を5Ｗ印加したときの被験体を用い、同様にZnの脱離量の測定を行った結果を示した図である。また、図５及び６の（ａ）は質量数(m/e)=64及び66のZnの脱離量を、（ｂ）は質量数(m/e)=67及び68のZnの脱離量を示している。
バイアス電力を0Ｗ印加したとき、つまりバイアス電力を印加しないときは、約２００℃より高温で熱処理した場合、酸化亜鉛の成分であるZnの脱離が始まり、熱処理温度が３００℃を超えるとZnの脱離が急激に増加した。これは、被験体が柱状構造からなるため、多くの結晶粒界を有し、熱的に不安定な状態にあるからである。
一方、バイアス電力を5Ｗ印加したときは、柱状の結晶構造が崩れ、高温で処理しても酸化亜鉛の成分の脱離量が少ないまま維持された。そのため、このような被験体を酸化物半導体薄膜層としてTFTに用いた場合、ゲート絶縁膜被膜時等の熱処理による酸化亜鉛の成分の脱離に起因する酸化物半導体薄膜層の低抵抗化を防ぐことができ、リーク電流が抑制することができる。 Next, the heat resistance of the oxide semiconductor thin film layer according to the present invention will be verified.
FIGS. 5 (a) and 5 (b) show the results of measuring the amount of desorption of Zn, which is a component of zinc oxide, by the temperature programmed desorption method (TDS) using a subject when 0 W of bias power was applied. FIG. FIGS. 6A and 6B are diagrams showing the results of measuring the amount of Zn desorbed in the same manner using a subject when 5 W of bias power was applied. FIGS. 5 and 6 show (a) the desorption amount of Zn with mass numbers (m / e) = 64 and 66, and (b) the desorption of Zn with mass numbers (m / e) = 67 and 68. Indicates the amount.
When bias power of 0 W is applied, that is, when bias power is not applied, when heat treatment is performed at a temperature higher than about 200 ° C., desorption of Zn, which is a component of zinc oxide, begins, and when the heat treatment temperature exceeds 300 ° C., Zn Desorption increased rapidly. This is because the subject has a columnar structure and thus has many crystal grain boundaries and is in a thermally unstable state.
On the other hand, when 5 W of bias power was applied, the columnar crystal structure collapsed and was maintained with a small amount of zinc oxide desorbed even when treated at a high temperature. Therefore, when such a subject is used for a TFT as an oxide semiconductor thin film layer, the resistance of the oxide semiconductor thin film layer is prevented from being reduced due to the detachment of the zinc oxide component by heat treatment such as when the gate insulating film is coated. And leakage current can be suppressed.

最後に、本発明に係る画素電極の微細加工性の効果を検証する。
図７（ａ）及び（ｂ）は順にバイアス電力を0Ｗ，40Ｗ印加して形成した被験体（酸化亜鉛）をドライエッチングしたときの側壁部分の走査型電子顕微鏡(SEM)像を示した写真である。なお、ドライエッチングはCH4ガスにより行った。
バイアス電力を0Ｗ印加したとき、つまりバイアス電力を印加しないときは、ドライエッチングを行うと酸化亜鉛のパターン側壁部分に凹凸が生じる。これは、被験体がC軸（００２）配向からなる、換言すると被験体の主成分である酸化亜鉛が柱状の結晶構造をとるため、その結晶粒に沿ってエッチングが進むからである。
一方、バイアス電力を40Ｗ印加したときは、柱状の結晶構造が崩れ、凹凸が減少し、側壁部分が直線状に加工される。このように、バイアス電力を印加することによって、微細加工性が向上する。そのため、このような被験体を画素電極に用いると、画素の高精細化が図れる。 Finally, the effect of the fine workability of the pixel electrode according to the present invention will be verified.
FIGS. 7 (a) and 7 (b) are photographs showing scanning electron microscope (SEM) images of the side walls when a subject (zinc oxide) formed by applying bias power of 0 W and 40 W in order is dry-etched. is there. The dry etching was performed with CH 4 gas.
When a bias power of 0 W is applied, that is, when no bias power is applied, unevenness is generated on the side wall portion of the zinc oxide pattern when dry etching is performed. This is because the subject has a C-axis (002) orientation, in other words, zinc oxide, which is the main component of the subject, has a columnar crystal structure, so that etching proceeds along the crystal grains.
On the other hand, when a bias power of 40 W is applied, the columnar crystal structure collapses, the irregularities are reduced, and the side wall portion is processed into a straight line. Thus, the fine workability is improved by applying the bias power. Therefore, when such a subject is used for a pixel electrode, high definition of the pixel can be achieved.

以上説明した如く、本発明に係る薄膜トランジスタアレイは、優れた性能を有するものであり、液晶ディスプレイ等に好適に利用可能である。   As described above, the thin film transistor array according to the present invention has excellent performance and can be suitably used for a liquid crystal display or the like.

本発明における薄膜トランジスタ（TFT）の一実施例の形態を示す断面図である。It is sectional drawing which shows the form of one Example of the thin-film transistor (TFT) in this invention. 本発明における薄膜トランジスタ（TFT）の一実施例の製法の一形態を経時的に示す断面図であり、下記（１）乃至（７）よりなる。（１）基板上にソース・ドレインを成形した構造の断面図（２）酸化物半導体薄膜層を被膜した構造の断面図（３）第一ゲート絶縁膜を被覆した構造の断面図（４）フォトレジストをコーティングした構造の断面図（５）酸化物半導体薄膜及び第一ゲート絶縁膜をパターニングした構造の断面図（６）第二ゲート絶縁膜及びコンタクトホールを形成した構造の断面図（７）ゲート電極、コンタクト部、ソース・ドレイン外部電極を形成した構造の断面図（８）画素電極を形成した断面図It is sectional drawing which shows one form of the manufacturing method of one Example of the thin-film transistor (TFT) in this invention with time, and consists of following (1) thru | or (7). (1) Cross-sectional view of structure in which source / drain is formed on substrate (2) Cross-sectional view of structure in which oxide semiconductor thin film layer is coated (3) Cross-sectional view of structure in which first gate insulating film is covered (4) Photo Cross-sectional view of structure coated with resist (5) Cross-sectional view of structure patterned oxide semiconductor thin film and first gate insulating film (6) Cross-sectional view of structure formed with second gate insulating film and contact hole (7) Gate Sectional view of structure in which electrode, contact portion, source / drain external electrode are formed (8) Sectional view in which pixel electrode is formed バイアス電力を0Ｗ，1Ｗ，2Ｗ，5Ｗ，10Ｗ，20Ｗ，40Ｗ，80Ｗ印加したときのＸ線回折の結果を示した図である。It is the figure which showed the result of the X-ray diffraction when bias electric power is applied 0W, 1W, 2W, 5W, 10W, 20W, 40W, 80W. （ａ）バイアス電力を0Ｗ印加したときの被験体の断面ＴＥＭ像を示した写真である。（ｂ）バイアス電力を5Ｗ印加したときの被験体の断面ＴＥＭ像を示した写真である。(A) A photograph showing a cross-sectional TEM image of a subject when 0 W of bias power was applied. (B) A photograph showing a cross-sectional TEM image of a subject when 5 W of bias power was applied. （ａ）バイアス電力を0Ｗ印加した被験体を用い、昇温脱離法(TDS)により質量数(m/e)=64及び66のZnの脱離量の測定結果を示した図である。（ｂ）バイアス電力を0Ｗ印加した被験体を用い、昇温脱離法(TDS)により質量数(m/e)=67及び68のZnの脱離量の測定結果を示した図である。(A) It is the figure which showed the measurement result of the desorption amount of Zn of mass number (m / e) = 64 and 66 by the temperature-programmed desorption method (TDS) using the test object which applied 0 W of bias electric power. (B) It is the figure which showed the measurement result of the desorption amount of Zn of mass number (m / e) = 67 and 68 by the temperature-programmed desorption method (TDS) using the test subject to which 0 W of bias power was applied. （ａ）バイアス電力を5Ｗ印加した被験体を用い、昇温脱離法(TDS)により質量数(m/e)=64及び66のZnの脱離量の測定結果を示した図である。（ｂ）バイアス電力を5Ｗ印加した被験体を用い、昇温脱離法(TDS)により質量数(m/e)=67及び68のZnの脱離量の測定結果を示した図である。(A) It is the figure which showed the measurement result of the desorption amount of Zn of mass number (m / e) = 64 and 66 by the temperature-programmed desorption method (TDS) using the test subject to which 5 W of bias power was applied. (B) It is the figure which showed the measurement result of the desorption amount of Zn of mass number (m / e) = 67 and 68 by the temperature-programmed desorption method (TDS) using the test subject to which 5 W of bias power was applied. （ａ）バイアス電力を0Ｗ印加した被験体をドライエッチングしたときの側壁部分の走査型電子顕微鏡(SEM)像を示した写真である。（ｂ）バイアス電力を40Ｗ印加した被験体をドライエッチングしたときの側壁部分の走査型電子顕微鏡(SEM)像を示した写真である。(A) It is the photograph which showed the scanning electron microscope (SEM) image of the side wall part when the test subject to which 0 W of bias power was applied was dry-etched. (B) It is the photograph which showed the scanning electron microscope (SEM) image of the side wall part when the test subject to which 40 W of bias power was applied was dry-etched.

符号の説明Explanation of symbols

１ 基板
２ ソース・ドレイン電極
３ 酸化物半導体薄膜層
４ 第一ゲート絶縁膜
６ 第二ゲート絶縁膜
７ ゲート電極
１００ 薄膜トランジスタ



DESCRIPTION OF SYMBOLS 1 Substrate 2 Source / drain electrode 3 Oxide semiconductor thin film layer 4 First gate insulating film 6 Second gate insulating film 7 Gate electrode 100 Thin film transistor



Claims (7)

基板上にチャネルとして形成される酸化亜鉛を主成分とする酸化物半導体薄膜層と、酸化亜鉛を主成分とする画素電極を少なくとも有し、前記酸化物半導体薄膜層の酸化亜鉛の配向と前記画素電極の酸化亜鉛の配向が異なることを特徴とする薄膜トランジスタアレイ。 An oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on a substrate and a pixel electrode mainly composed of zinc oxide, and an orientation of zinc oxide in the oxide semiconductor thin film layer and the pixel A thin film transistor array characterized in that the orientation of zinc oxide of electrodes is different. 前記画素電極の主成分である酸化亜鉛が（１００）配向と（１０１）配向からなることを特徴とする請求項１記載の薄膜トランジスタアレイ。 2. The thin film transistor array according to claim 1, wherein zinc oxide which is a main component of the pixel electrode has (100) orientation and (101) orientation. 前記画素電極が酸化亜鉛に対してドナーとなる不純物がドーピングされていることを特徴とする請求項１又は２記載の薄膜トランジスタアレイ。 3. The thin film transistor array according to claim 1, wherein the pixel electrode is doped with an impurity serving as a donor for zinc oxide. 前記酸化物半導体薄膜層の主成分である酸化亜鉛が（００２）配向からなることを特徴とする請求項１乃至３いずれか記載の薄膜トランジスタアレイ。 4. The thin film transistor array according to claim 1, wherein zinc oxide which is a main component of the oxide semiconductor thin film layer has a (002) orientation. 前記酸化物半導体薄膜層の主成分である酸化亜鉛が（００２）配向と（１０１）配向からなることを特徴とする請求項１乃至３いずれか記載の薄膜トランジスタアレイ。 4. The thin film transistor array according to claim 1, wherein zinc oxide, which is a main component of the oxide semiconductor thin film layer, has a (002) orientation and a (101) orientation. 5. 基板上に酸化亜鉛を主成分とする酸化物ターゲットを用いて酸化物半導体薄膜層をチャネルとして形成する工程と、該酸化物半導体薄膜層の上表面及び側面を被覆してゲート絶縁膜を形成する工程と、該ゲート絶縁膜の上にゲート電極を積載する工程と、酸化亜鉛を主成分とする酸化物ターゲットを用いて画素電極を形成する工程を有する薄膜トランジスタアレイの製法であって、前記画素電極、或いは該画素電極と前記酸化物半導体薄膜層を成膜する際、前記基板に高周波電力を印加しながら行うことで、該画素電極と該酸化物半導体薄膜層の主成分である酸化亜鉛の配向を制御し、異なるものとすることを特徴とする薄膜トランジスタアレイの製法。 A step of forming an oxide semiconductor thin film layer as a channel using an oxide target containing zinc oxide as a main component on a substrate, and forming a gate insulating film covering the upper surface and side surfaces of the oxide semiconductor thin film layer A method of manufacturing a thin film transistor array, comprising: a step of stacking a gate electrode on the gate insulating film; and a step of forming a pixel electrode using an oxide target composed mainly of zinc oxide. Alternatively, when forming the pixel electrode and the oxide semiconductor thin film layer while applying high frequency power to the substrate, the orientation of zinc oxide that is a main component of the pixel electrode and the oxide semiconductor thin film layer is performed. A method of manufacturing a thin film transistor array, characterized in that the control is different. 前記画素電極の成膜、或いは該画素電極と前記酸化物半導体薄膜層の成膜をマグネトロンスパッタリング法を用いて行い、前記基板への高周波電力の印加を基板ステージを介して行うことを特徴とする請求項６記載の薄膜トランジスタアレイの製法。
The pixel electrode is formed, or the pixel electrode and the oxide semiconductor thin film layer are formed using a magnetron sputtering method, and high-frequency power is applied to the substrate through a substrate stage. A method for producing a thin film transistor array according to claim 6.
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