JP2007214558A - Group iii-v compound semiconductor light-emitting diode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Group III-V compound semiconductor light-emitting diode which allows a problem of light-interception by an electrode to be completely in principle eliminated and also allows a total reflection at an interface to be suppressed effectively. <P>SOLUTION: In a Group III-V compound semiconductor light-emitting diode including at least a barrier layer and an active layer in the growth layers of epitaxial growth made on a substrate 1 that has a plurality of crystallographic planes, the growth layers are characterized in that at least the active layer of the growth layers has, in the surface direction thereof, a plurality of crystallographic planes having different band-gap energies and ohmic electrodes 4 formed for current injection on crystallographic planes having a higher band-gap energy of the plurality of crystallographic planes. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a high-efficiency light-emitting diode using a III-V compound semiconductor as a material, and more specifically, a group III-V having improved light extraction efficiency by separating a light extraction region and a current injection region. The present invention relates to a compound semiconductor light emitting diode.

  Light emitting diodes made of III-V compound semiconductors (AlGaAs, AlGaInP, AlGaInN, etc.) are attracting a great deal of attention as light sources for next-generation energy-saving and long-life lighting displays that can replace incandescent and fluorescent lamps.

  The light emission efficiency of a light emitting diode is generally determined by the product of the internal quantum efficiency and the light extraction efficiency. Recent advances in crystal growth technology have realized internal quantum efficiencies close to 100%, especially for AlGaAs and AlGaInP materials. On the other hand, it is very difficult to efficiently extract the light generated in the active layer to the outside, and it is no exaggeration to say that it is the biggest factor limiting the light emission efficiency of the light emitting diode.

  There are two basic reasons for this. The first cause is a problem of so-called total reflection of light. That is, since the refractive index of a III-V group compound semiconductor is usually much larger than 1, light is totally reflected at the interface between the semiconductor and air and returned to the inside of the semiconductor. What can be extracted to the outside is light incident on the interface at an angle smaller than the critical angle of total reflection. For example, in the case of GaAs, the critical angle of total reflection is about 16.1 °, and the proportion of light within this critical angle is only 0.5 × (1-cos16.1 °) = 2%. Furthermore, since a part of the light within the critical angle is also reflected by the surface, the proportion of the light that can actually be extracted to the outside is only about 1%. In order to suppress total reflection of light, (1) sealing with a resin having a high refractive index, (2) dicing the crystal into an inverted pyramid shape (Non-patent Document 1), (3) microcavity (4) Intentionally forming minute irregularities on the semiconductor surface and using light scattering at the interface to change the incident angle of light (Non-patent document 2) Document 3) is used.

The second cause is light shielding by the metal electrode. The driving current of the light emitting diode is usually injected from a metal electrode formed on the surface of the crystal. In this case, the current density directly under the electrode is the highest, but the light generated there is almost blocked by the electrode and cannot be extracted to the surface. In order to solve this problem, several techniques have been proposed so far focusing on diffusing the injected current in the lateral direction as far as possible out of the electrode region. The main technologies are as follows: (1) A thick current diffusion layer (approximately 10 μm) is provided between the active layer and the electrode (Non-patent document 4), (2) A composite structure of metal electrode and ITO transparent electrode is used (Non-patent document) Document 5), (3) Introducing a current blocking layer directly under the electrode (Non-Patent Document 6). However, even if these structures are used, the current density directly under or near the metal electrode remains the highest, and the effect is limited. In addition, the introduction of a thick current spreading layer or current blocking layer complicates the manufacturing process and raises the problem of increased production costs.
Furthermore, in the conventional light emitting diode structure, the carriers injected from the electrode are concentrated in the vicinity of the electrode, and the carrier density, that is, the light emission intensity rapidly decreases when the carrier is separated from the electrode. For this reason, there is a limit to the output power of light obtained from one light-emitting diode chip, and for applications that require high optical output power, a large number of chips must be used.

  An object of the present invention is to use a III-V group compound semiconductor that can completely eliminate the above-described light shielding problem due to the metal electrode and that can effectively suppress total reflection at the interface. The object is to provide a highly efficient light emitting diode. Another object of the present invention is to use a group III-V compound semiconductor that can easily obtain a high light output power from a single chip because the light output power of the light emitting diode increases in proportion to the area of the chip. It is in providing a highly efficient light emitting diode.

The present invention employs the following means in order to solve the above problems.
The first means is a group III-V compound semiconductor light emitting diode having at least a barrier layer and an active layer in a growth layer epitaxially grown on a substrate having a plurality of crystal planes, wherein the growth layer includes at least the growth layer. The active layer has a plurality of crystal planes having different band gap energies in the in-plane direction, and an ohmic electrode for current injection is formed on the crystal plane having the higher band gap energy among the plurality of crystal planes. A III-V compound semiconductor light emitting diode.
The second means is a group III-V compound semiconductor light emitting diode having at least a barrier layer and an active layer in a growth layer epitaxially grown on a substrate having a plurality of crystal planes, wherein the growth layer includes at least the growth layer. The active layer has a plurality of crystal planes having different band gap energies in the in-plane direction, and a first ohmic electrode for current injection is formed on the crystal plane having the higher band gap energy among the plurality of crystal planes. Further, a III-V group compound characterized in that a second ohmic electrode for current injection is formed on the crystal plane having a higher band gap energy after the substrate is removed from the growth layer. Semiconductor light emitting diode.
According to a third means, in the first means or the second means, the plurality of crystal faces having different band gap energies are more than the first crystal face having a higher band gap energy among the plurality of crystal faces. A second crystal plane having a low band gap energy, and one or more crystal planes positioned between the first and second crystal planes, and positioned between the first and second crystal planes. The III-V compound semiconductor light emitting diode is characterized in that the crystal plane is a band gap energy between the band gap energy of the first crystal plane and the band gap energy of the second crystal plane.
A fourth means is characterized in that in any one of the first means to the third means, a plurality of crystal planes having different band gap energies are arrayed in an in-plane direction. And a III-V compound semiconductor light emitting diode.
According to a fifth means, in any one of the first means to the fourth means, the substrate is constituted by two (111) A faces and two (001) faces at the top and bottom [ 1-10] a substrate including a groove shape in the direction, and among the plurality of crystal planes having different band gap energies, a crystal plane having a lower band gap energy and a crystal plane having a higher band gap energy are respectively A III-V compound semiconductor light emitting diode grown on a (001) plane and a (111) A plane of a substrate, wherein the ohmic electrode is formed on a (111) A plane.
Sixth means is that in any one of the first to fourth means, the substrate is constituted by two (111) A faces and one upper (001) face [1-10] And a crystal plane having a lower band gap energy and a crystal plane having a higher band gap energy among the plurality of crystal planes having different band gap energies. A III-V compound semiconductor light emitting diode grown on a (001) plane and a (111) A plane, wherein the ohmic electrode is formed on a (111) A plane.
A seventh means is the method according to any one of the first to fourth means, wherein the substrate has a (111) A plane, an upper (001) plane, and the (111) A plane and upper (001) plane. A substrate having at least one high-index plane formed between the plane and a plurality of crystal planes having different band gap energies; III-V group compound semiconductor light-emitting diode, wherein high crystal planes are grown on the upper (001) plane and (111) A plane of the substrate, respectively, and the ohmic electrode is formed on the (111) A plane It is.
According to an eighth means, in any one of the first to seventh means, when the active layer of the III-V compound semiconductor light emitting diode is a binary compound, a quantum well structure, a ternary and In the case of a quaternary mixed crystal, a III-V compound semiconductor light emitting diode is used, which uses a quantum well structure or a bulk structure.

According to the group III-V compound semiconductor light emitting diode of the present invention, at least the epitaxial growth layer serving as the active layer is composed of a plurality of crystal planes having different band gap energies, and the light emitted from the crystal plane having the lower band gap energy. In order to avoid the radiation path, a metal electrode for current injection is formed on the crystal plane having a higher band gap energy, and the current injection region and the light emitting region are spatially separated. A light-emitting diode in which light shielding by the metal electrode that has been used can be obtained is obtained.
In addition, since a substrate having a convex cross-sectional shape is used, the proportion of light incident on the surface at an angle smaller than the critical angle of total reflection increases, and total reflection at the interface between the semiconductor and air is also effective. It becomes possible to suppress to.
Furthermore, since the optical output power of the III-V compound semiconductor light emitting diode of the present invention can be increased in proportion to the area of the sample, it is particularly suitable for applications that require high optical output power.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
1 and 2 are schematic views of a III-V compound semiconductor light emitting diode according to the invention of this embodiment.
In these figures, 1 is an n-type (001) GaAs substrate, 2 is an AlGaAs with a low Al composition, 3 is an AlGaAs with a high Al composition, 4 is a p-type ohmic electrode, 5 is an n-type ohmic electrode, and 6 is an electron transfer Direction, 7 is the hole movement direction, and 8 is the GaAs quantum well active layer.

  The basic configuration of the III-V compound semiconductor light emitting diode of the present invention will be described with reference to schematic diagrams 1 and 2. First, using photolithography and wet etching, a U-shaped groove with a (111) A inclined surface and two (001) flat surfaces at the top and bottom on a (001) flat GaAs substrate 1 in the [1-10] direction To form an array. Next, a compound semiconductor multilayer film having a light emitting diode structure, for example, (Al) GaAs / AlGaAs, is grown on the processed shape substrate 1 by using a crystal growth method such as metal organic vapor phase epitaxy. When a compound semiconductor multilayer film grows on such a non-flat substrate, some group III atoms diffuse from the (111) A inclined surface to the top and bottom (001) flat surfaces under appropriate growth conditions. There is a nature to do. In this diffusion process, the diffusion rate of Ga atoms is generally faster than that of Al atoms. Due to the anisotropy of crystal growth, the crystal growth thickness and Al composition vary depending on the crystal plane orientation. That is, the thickness of the (111) A inclined surface is thinner than the (001) flat surface at the top and bottom, and the Al composition is higher than that of the (001) flat surface. Therefore, when an (Al) GaAs quantum well is used for the active layer 8, the energy level of the quantum well on the (111) A tilted surface is It is higher than the energy level of 001) flat surface quantum well. Here, the case of the quantum well active layer has been described. However, when a ternary or quaternary mixed crystal such as AlGaAs or AlGaInP is used as the material of the active layer, it is possible to take a bulk structure as the active layer structure .

Finally, the ohmic electrode 4 on the surface side for current injection is selectively formed on a part of the (111) A inclined surface so as to avoid the radiation path of light emitted from the (001) flat surface as much as possible. . In this structure, carriers injected from the (111) A inclined plane move to the (001) flat-plane quantum well with a low energy level through the (Al) GaAs active layer or (Al) GaAs active layer and AlGaAs barrier layer. Then, it can be made to emit light. In this case, since the proportion of carriers moving to the (001) flat surface increases exponentially with the energy difference between the (111) A inclined surface quantum well and the (001) flat surface quantum well, the inclined surface quantum well And the flat surface quantum well are sufficiently larger than the thermal energy, carriers can move to the (001) flat surface at a rate close to 100%. In other words, this means that the carrier density directly below the ohmic electrode approaches zero as much as possible. For this reason, in the light emitting diode of the present invention, unlike the conventional technique, the region immediately below the electrode corresponds to a region where the carrier saturation is least likely to occur, and the ohmic electrode can be formed infinitely small in principle. For example, if current photolithography technology is used, an ohmic electrode having a width of 1 μm or less can be easily formed. Thus, if the width of the ohmic electrode 4 is made sufficiently smaller than the light emitting region, the current injection region and the light emitting region can be spatially completely separated and radiated into the upper hemispherical space by the metal electrode. In principle, it is possible to completely eliminate light shielding.
Further, as shown in FIG. 2, in the invention of FIG. 1, the shaped substrate used for the growth is removed from the epitaxial growth layer which becomes the main body of the light emitting diode structure by a method such as selective etching or epitaxial lift-off, and the ohmic electrode 5 on the back side is removed. Similarly to the ohmic electrode 4 on the surface side, the (111) A inclined surface is selectively made small so as to avoid the radiation path of light emitted from the (001) flat surface quantum well as much as possible. As a result, there is no shielding of the light emitted to the entire space by the metal electrode, and it can be expected to realize light extraction efficiency close to 100%.

  In addition, the convex cross-sectional shape composed of the (111) A inclined surface and the upper (001) flat surface has a function of a microlens, and can effectively suppress total reflection on the surface. That is, a part of the light incident on the (001) flat surface at an angle larger than the critical angle of total reflection can be incident on the (111) A inclined surface at an angle smaller than the critical angle of total reflection. The percentage of light that can be extracted is increased.

  Furthermore, as is clear from the above description, since a large number of U groove patterns are arranged in an array on the substrate, there is no in-plane distribution of light emission intensity as in conventional devices, and light is uniformly distributed over the entire substrate. As a result, the chip area can be increased, and high optical output power can be easily extracted from a single chip.

Next, a method of manufacturing an AlGaAs / GaAs light emitting diode using a V-groove GaAs substrate according to the present invention will be described with reference to FIGS. 3 to 6 (Example 1).
In these figures, 9 is a Si-doped n-type Al _0.65 Ga _0.35 As barrier layer, 10 is a non-doped Al _0.3 Ga _0.7 As barrier layer, 11 is a non-doped Al _0.3 Ga _0.7 As barrier layer, and 12 is a Zn-doped p-type Al _0.65 Ga barrier layer. _0.35 As barrier layer, 13 is non-doped GaAs quantum well active layer, 14 is Zn-doped GaAs cap layer, 15 is SiO ₂ film, 16 is Si-doped n-type GaAs buffer layer, 17 is Si-doped n-type (001) flat surface Al _0.65 Ga _0.35 As barrier layer, 18 Si-doped n-type (111) A tilted surface Al _0.69 Ga _0.31 As barrier layer, 19 Si-doped n-type Al _0.61 Ga _0.39 As vertical quantum well, 20 non-doped (001) flat surface Al _0.3 Ga _0.7 As barrier layer, 21 is an undoped (111) A tilted surface Al _0.34 Ga _0.66 As barrier layer, 22 is an undoped Al _0.26 Ga _0.74 As vertical quantum well, 23 is an undoped (001) flat surface GaAs quantum well, 24 the non-doped (111) A inclined plane GaAs quantum wells, 25 non-doped V groove bottom crescent GaAs quantum wire, 26 a non-doped (001) flat surface Al _0.3 Ga _0.7 As barrier layer, 27 is non-doped (111) A Slope Al _0.34 Ga _0.66 As barrier layer, an undoped Al _0.26 Ga _0.74 As vertical quantum wells 28, 29 Zn-doped p-type (001) flat surface Al _0.65 Ga _0.35 As barrier layer, 30 is a Zn-doped p-type (111) A Tilted plane Al _0.69 Ga _0.31 As barrier layer, 31 Zn-doped p-type Al _0.61 Ga _0.39 As vertical quantum well, 32 n-type ohmic electrode (AuGe / Ni / Au), 33 p-type ohmic electrode (Ti / Au) 34 are Cr / Au bonding pads.

  This V-groove substrate is formed by etching until the bottom (001) flat surface disappears in the manufacture of the U-shaped substrate of FIG. 1, and the ohmic electrode on the surface has the advantage that it can be formed in a self-aligned manner. Yes.

In FIG. 3, the [1-10] direction is formed on an n-type (001) GaAs substrate 1 using photolithography and wet etching (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 3: 50). A V-groove pattern with a period of 4 μm is formed. Next, on the substrate 1, using a metalorganic vapor phase epitaxy method, a 0.37 μm Si-doped n-type GaAs buffer layer 16, a 0.71 μm Si-doped n-type Al _0.65 Ga _0.35 As barrier layer 9, a 0.25 μm Non-doped Al _0.3 Ga _0.7 As barrier layer 10, 14.5 nm non-doped GaAs quantum well active layer 13, 0.15 μm non-doped Al _0.3 Ga _0.7 As barrier layer 11, 0.73 μm Zn-doped p-type Al _0.65 Ga _0.35 As barrier layer 12, Then, a Zn-doped p-type GaAs cap layer 14 having a thickness of 25 nm is sequentially grown. Here, the composition of Al and the grown film thickness are measured on the (001) upper flat surface. In this growth, trimethylaluminum (TMAl), triethylgallium (TEGa) and tertiarybutylarsine (TBAs) were used as raw materials for Al, Ga and As, respectively. The growth temperature was 690 ° C.

FIG. 4 is a schematic cross-sectional view showing details of the crystal structure of the light-emitting diode sample. As shown in this figure, at the bottom of the V-groove, the GaAs quantum well layer and the AlGaAs barrier layer have a crescent-shaped quantum wire 25 (width of about 40 nm) and a width of about 15 nm called vertical quantum wells 19, 22, 28, 31 respectively. The stripe structure has a low Al composition. The Al composition of each crystal plane of the non-doped AlGaAs barrier layers 10 and 11, that is, the (001) flat plane, the (111) A inclined plane, and the V-groove bottom vertical quantum well was measured by photoluminescence. Band gap energy = 1.798 eV), 0.34 (band gap energy at room temperature = 1.848 eV), and 0.26 (band gap energy at room temperature = 1.748 eV). The thicknesses of the (001) flat surface quantum well 23, the (111) A inclined surface quantum well 24, and the crescent-shaped quantum wire 25 at the bottom of the V groove are about 14.5, 7.3, and 15.4 nm, respectively.
Thereafter, a 140 nm thick SiO ₂ film is deposited on the surface of the sample by plasma CVD, and a stripe pattern 15 for forming a bonding pad with a width of 200 μm is formed in the vertical direction of the V groove using photolithography and wet etching. To do.

Next, in FIG. 5, Ti (40 nm) and Au (150 nm) are vapor-deposited on the surface as a metal for forming a p-type ohmic electrode. Next, a photoresist is applied to flatten the V-groove surface. Thereafter, O ₂ plasma ashing is performed to expose a part of the (001) flat surface and the (111) A inclined surface so that a part of the photoresist remains only in the V groove. Next, using the photoresist remaining in the V groove as a mask, Au and Ti were etched with KI: I ₂ and HF: H ₂ O ₂ : H ₂ O based etchants, respectively (111) A p-type ohmic electrode 33 is formed on the A inclined surface and the V-groove bottom. The p-type ohmic electrode 33 can also be formed using photolithography and lift-off technology. Further, AuGe / Ni / Au is vacuum deposited on the entire back surface of the sample to form an n-type electrode. Finally, alloy processing is performed to complete the p-type ohmic electrode 33 and the n-type ohmic electrode 32.

Next, in FIG. 6, a slightly narrow Cr / Au pattern (180 μm) 34 is formed as a bonding pad on the stripe of the SiO ₂ film 15 using photolithography and the lift-off method to complete the device.

FIG. 7 is a diagram showing an emission spectrum of a chip having a size of 1 × ¹ mm ² (bonding pad area removed) measured under conditions of room temperature and direct current drive.
Note that the chip used for the measurement is only die-bonded to the lead frame, and is not sealed with an epoxy resin.
As shown in the figure, the emission from the (111) A inclined plane quantum well, the (001) flat plane quantum well, and the V-groove bottom quantum wire was observed around 836.2 nm, 848.7, 857.5 nm, and 864.3 nm, respectively. Emission from the (001) flat surface quantum well is strongly observed, and it can be clearly confirmed that the carriers injected from the (111) A inclined surface are efficiently moved to the (001) flat surface. Although not shown here, in the measurement at a low temperature of about 100K, almost no light emission from the (111) A inclined plane quantum well was observed, and the carriers injected from the (111) A inclined plane were 100 It has also been found that they migrate to (001) flat-plane quantum wells and quantum wires at the bottom of the V-groove with an efficiency close to%. The emission of the (111) A inclined plane quantum well was observed at room temperature because the difference in emission energy between the (111) A inclined plane quantum well and the (001) flat plane quantum well of the sample used in this experiment (21.8 This is because some carriers were excited from the (001) quantum well to the (111) A quantum well by thermal energy (26 meV) at room temperature. This can be solved by increasing the energy difference between the (111) A inclined plane quantum well, the (001) flat plane quantum well, and the V-groove bottom quantum wire by optimizing the growth conditions or using mixed crystal material (AlGaAs). It is.

  Further, as can be seen from the device structure of FIG. 6 and the emission spectrum of FIG. 7, although the crescent moon-like quantum wire 25 is directly under the metal electrode 33, very strong light emission is observed from this region. This is considered to be due to the lateral waveguiding effect as shown in FIG. That is, in this device, the low Al composition barrier layers 10 and 11 (Al composition about 30%) are considered to be lateral waveguides sandwiched between the high Al composition barrier layers 9 and 12 (Al composition about 65%). . Then, it is considered that a part of the light emission 35 of the quantum wire 25 is guided to this waveguide in the lateral direction and taken out from the light extraction region between the electrodes 33 through the (111) A inclined surface.

FIG. 9 is a diagram showing the injection current dependence of the optical output power and the external quantum efficiency.
As shown in the figure, an external quantum efficiency of about 7% is obtained around 50 mA. Also, from the comparison of the integrated emission intensity at room temperature and low temperature (4.5K), the internal quantum efficiency at room temperature is calculated to be about 46%. Using these values, a light extraction efficiency of about 15.2% can be obtained. This is a value about an order of magnitude higher than the theoretical value of the external extraction efficiency in the case of a flat substrate. As a result of observation of the light emission pattern with a CCD camera, it was found that the light emission intensity in the region where the (001) flat surface intersects the (111) A inclined surface is stronger than the central part of the (001) flat surface. From these results, the suppression effect of total reflection at the interface due to the presence of the (111) A inclined surface was clearly confirmed. In the future, it is considered that the extraction efficiency can be further improved by sealing the chip with an epoxy resin.

Next, another embodiment of the present invention will be described with reference to FIGS. 10a and 10b.
FIG. 10a is a schematic cross-sectional view of a substrate used for sample growth in this example, and FIG. 10b is a schematic cross-sectional view of a group III-V compound semiconductor light emitting diode according to the invention of this example.
In this figure, 36 is a crystal plane having an index higher than that of the (111) A plane.
First, a photoresist line / space pattern is formed in the [1-10] direction on a (001) flat GaAs substrate 1 using photolithography. Next, the substrate is etched using NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 3: 50 solution, and is composed of two (111) A inclined surfaces and one (001) upper flat surface. A V-groove pattern to be formed is formed on the substrate. Thereafter, with the photoresist remaining on the (001) flat surface, the etching solution is changed to, for example, NH ₄ OH: H ₂ O ₂ : H ₂ O = 4: 0.5: 40, and additional etching is performed. By this additional etching, a crystal plane 36 having a higher index than the (111) A plane, for example, the (113) A plane can be formed between the (111) A inclined plane and the (001) flat plane (FIG. 10a). Here, by changing the amount of H ₂ O _{2 in} the NH ₄ OH: H ₂ O ₂ : H ₂ O solution used for the additional etching, the plane orientation of the high index plane 36 to be formed, that is, the high index plane 36 and ( 001) The angle of intersection with the flat surface can be controlled. For example, in addition to the (113) A surface, a high index surface 36 such as a (112) A surface or a (114) A surface can be formed. FIG. 10a shows the case where one high index surface 36 is formed between the (111) A inclined surface and the (001) flat surface. For example, by changing the etching solution stepwise, the high index surface 36 is formed. It is also possible to form two or more high index surfaces between the (111) A inclined surface and the (001) flat surface, where the surface 36 has two or more surface orientations.

Next, after removing the photoresist, a light emitting diode structure having the same structure as that of Example 1 is grown on the substrate by using a metal organic vapor phase epitaxy method. Here, the width of the high index surface 36 and the Al composition can be controlled by the growth conditions, particularly the growth temperature and the flow rate of As. Therefore, due to the anisotropy of crystal growth in the same manner as described above, the epitaxially grown active layer and barrier layer have different band gap energies for the (111) A plane, the high index plane 36 and the (001) plane in the in-plane direction. Can be adjusted. Specifically, for the active layer, the active layer has a higher band gap energy on the (111) A plane, a lower band gap energy on the (001) plane, and a band gap energy between them on the high index plane 36. Can grow. In addition, since AlGaAs is used for the barrier layer in this example, this barrier layer also has a higher band gap energy on the (111) A plane and higher band gap energy on the (001) plane due to the anisotropy of crystal growth. A barrier layer can be grown that is lower and has a high index plane 36 and a band gap energy therebetween.
Then, after the crystal growth, the p-type electrode 33 and the n-type electrode 32 are formed on a part of the (111) A surface (in the V groove) and the entire back surface by using the same process as in Example 1, respectively. Such a light emitting diode is obtained. The electrode (33) may partially extend to the high index plane 36 beyond the (111) A plane.
In this structure, carriers injected from the electrode are (Al) GaAs active layers, or (001) flat surface quantum wells with low energy levels through (Al) GaAs active layers and AlGaAs barrier layers, and crescent-shaped quantum at the bottom of the V-groove. It is moved to a thin line where it can emit light.
In this device, due to the presence of the high index surface 36, the transverse cross-sectional shape of the light extraction region between the V-shaped electrodes approaches a semicircular shape that is most effective in suppressing total reflection. For this reason, it can be expected that the effect of suppressing the total reflection is further improved as compared with the case where the high index surface 36 is not provided.

It is a cross-sectional schematic diagram for demonstrating the basic composition of the III-V group compound semiconductor light emitting diode of this invention. It is a cross-sectional schematic diagram for demonstrating the basic composition of the III-V group compound semiconductor light emitting diode of this invention. It is a three-dimensional schematic diagram which shows the manufacturing process of the III-V compound semiconductor light emitting diode of this invention. It is a cross-sectional schematic diagram which shows the detail of the crystal structure of the III-V group compound semiconductor light emitting diode sample of this invention. It is a three-dimensional schematic diagram which shows the manufacturing process of the III-V compound semiconductor light emitting diode of this invention. It is a three-dimensional schematic diagram which shows the manufacturing process of the III-V compound semiconductor light emitting diode of this invention. It is a figure which shows the emission spectrum measured on the conditions of room temperature and direct current drive of the chip | tip of size 1x1mm < ² > (bonding pad area | region removal). It is a cross-sectional schematic diagram for demonstrating the lateral waveguide effect in taking out of quantum wire light emission. It is a figure which shows the injection current dependence of optical output power and external quantum efficiency. It is a cross-sectional schematic diagram of the board | substrate used for the growth of the epitaxial growth layer which concerns on the other Example of this invention. It is a cross-sectional schematic diagram of the III-V compound semiconductor light emitting diode which concerns on the other Example of this invention.

Explanation of symbols

1 n-type (001) GaAs substrate 2 AlGaAs with low Al composition
3 AlGaAs with high Al composition
4 p-type ohmic electrode 5 n-type ohmic electrode 6 electron movement direction 7 hole movement direction 8 GaAs quantum well active layer 9 Si-doped n-type Al _0.65 Ga _0.35 As barrier layer 10 non-doped Al _0.3 Ga _0.7 As barrier layer 11 non-doped Al _0.3 Ga _0.7 As barrier layer 12 Zn-doped p-type Al _0.65 Ga _0.35 As barrier layer 13 GaAs quantum well active layer 14 Zn-doped GaAs cap layer 15 SiO ₂ film 16 Si-doped n-type GaAs buffer layer 17 Si-doped n-type (001 ) Flat surface Al _0.65 Ga _0.35 As barrier layer 18 Si-doped n-type (111) A inclined surface Al _0.69 Ga _0.31 As barrier layer 19 Si-doped n-type Al _0.61 Ga _0.39 As vertical quantum well 20 Non-doped (001) flat surface Al _0.3 Ga _0.7 As barrier layer 21 Non-doped (111) A inclined surface Al _0.34 Ga _0.66 As barrier layer 22 Non-doped Al _0.26 Ga _0.74 As vertical quantum well 23 Non-doped (001) flat surface GaAs quantum well 24 Non-doped (111) A inclined surface GaAs quantum Well 25 Non-doped V-groove bottom crescent-shaped GaAs quantum wire 26 Ndopu (001) flat surface Al _0.3 Ga _0.7 As barrier layer 27 non-doped (111) A sloping surface Al _0.34 Ga _0.66 As barrier layer 28 non-doped Al _0.26 Ga _0.74 As vertical quantum well 29 Zn-doped p-type (001) flat surface Al _0.65 Ga _0.35 As barrier layer 30 Zn-doped p-type (111) A tilted surface Al _0.69 Ga _0.31 As barrier layer 31 Zn-doped p-type Al _0.61 Ga _0.39 As vertical quantum well 32 n-type ohmic electrode (AuGe / Ni / Au)
33 p-type ohmic electrode (Ti / Au)
34 Cr / Au bonding pad 35 Quantum wire emission (partial) extraction direction 36 Crystal plane with higher index than (111) A plane

Claims (8)

In a group III-V compound semiconductor light emitting diode having at least a barrier layer and an active layer in a growth layer epitaxially grown on a substrate having a plurality of crystal planes,
The growth layer has a plurality of crystal faces having different band gap energies in an in-plane direction, and at least the active layer of the growth layer has a current injection into a crystal face having a higher band gap energy. A III-V compound semiconductor light emitting diode, characterized in that an ohmic electrode is formed. In a group III-V compound semiconductor light emitting diode having at least a barrier layer and an active layer in a growth layer epitaxially grown on a substrate having a plurality of crystal planes,
The growth layer has a plurality of crystal faces having different band gap energies in an in-plane direction, and at least the active layer of the growth layer has a current injection into a crystal face having a higher band gap energy. A first ohmic electrode is formed, and a second ohmic electrode for current injection is formed on the higher crystal plane of the band gap energy after the substrate is removed from the growth layer. A group III-V compound semiconductor light emitting diode.   The plurality of crystal planes having different band gap energies include a first crystal plane having a higher band gap energy, a second crystal plane having a lower band gap energy, and the first and first crystal planes. One or more crystal planes positioned between the two crystal planes, and the crystal plane positioned between the first and second crystal planes has a band gap energy of the first crystal plane and a first 3. The group III-V compound semiconductor light emitting diode according to claim 1, wherein the band gap energy is between the band gap energies of two crystal planes.   4. The group III-V compound semiconductor light-emitting diode according to claim 1, wherein a plurality of crystal planes having different band gap energies are arranged in an array in the in-plane direction. The substrate includes a (1-10) -direction groove shape constituted by two (111) A planes and two (001) planes at the top and bottom,
Among the plurality of crystal planes having different band gap energies, a crystal plane having a lower band gap energy and a crystal plane having a higher band gap energy grow on the (001) plane and the (111) A plane of the substrate, respectively. The III-V compound semiconductor light emitting diode according to any one of claims 1 to 4, wherein the ohmic electrode is formed on a (111) A plane. The substrate includes a [1-10] V-groove shape constituted by two (111) A surfaces and one upper (001) surface;
Among the plurality of crystal planes having different band gap energies, a crystal plane having a lower band gap energy and a crystal plane having a higher band gap energy grow on the (001) plane and the (111) A plane of the substrate, respectively. The III-V compound semiconductor light emitting diode according to any one of claims 1 to 4, wherein the ohmic electrode is formed on a (111) A plane. The substrate has a (111) A plane, an upper (001) plane, and at least one high index plane formed between the (111) A plane and the upper (001) plane;
Among the plurality of crystal planes having different band gap energies, a crystal plane having a lower band gap energy and a crystal plane having a higher band gap energy are respectively formed on the upper (001) plane and the (111) A plane of the substrate. The III-V compound semiconductor light emitting diode according to any one of claims 1 to 4, wherein the ohmic electrode is grown on the (111) A plane.   The active layer of the III-V compound semiconductor light emitting diode uses a quantum well structure in the case of a binary compound, or a quantum well structure or a bulk structure in the case of a ternary and quaternary mixed crystal. The III-V compound semiconductor light emitting diode in any one of thru | or 7.