JP2007214275A - Semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method for reducing variations in wiring resistance. <P>SOLUTION: In the semiconductor device manufacturing method, a first conductive film (13) is formed on an insulating film 12 provided on a semiconductor substrate (11) and having a plurality of recesses (12a, 12b) as a trench or a hole. Then a surface layer (13a) of the first conductive film (13) is removed. After that, a second conductive film (14) is formed on the first conductive film (13). Then parts existing outside a plurality of the recesses (12a, 12b) are removed in the first/second conductive films (13), (14). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device capable of reducing a surface step.

  In recent years, the miniaturization of multilayer wiring structures has progressed, and in particular, copper having low resistance and excellent electromigration resistance has been adopted as a wiring material used for LSI (Large Scale Integration) in the process generation of 130 nm and later. ing. When forming a copper wiring, it is necessary to embed a copper film in a recess such as a trench or a through hole formed on the substrate, but an electrolytic plating method is generally employed. This is because the electrolytic plating method is relatively low-cost and high-throughput for mass production applications, and has excellent embedding characteristics in the recesses.

In order to form a copper wiring by using an electrolytic plating method, generally, after forming a diffusion prevention film made of tantalum or the like inside a recess formed in an insulating film on a substrate, an electrolytic plating made of a copper film is performed. The seed layer is formed. Thereafter, a copper film is formed so as to fill the inside of the recess using an electrolytic plating method, and then the copper film existing outside the recess is removed using a CMP method. In this way, a copper wiring is formed inside the recess by performing a series of steps generally called a damascene method (see, for example, Patent Document 1).
JP 2003-193300 A

  By the way, as LSI miniaturization progresses, for example, the size of a recess such as a trench or a through hole becomes smaller, so it is necessary to improve the embedding property of the copper film in the recess during electrolytic plating.

  When copper is embedded in the recess using the electrolytic plating method, a liquid containing an additive in a liquid such as a copper sulfate solution (hereinafter referred to as a plating solution) is used, and this plating solution has a plurality of roles. In many cases, the copper film is composed of several kinds of components, and depending on the additive contained, the manner in which the copper film grows inside the recess is greatly changed.

  Here, as a general additive included in the plating solution, for example, an inhibitor (suppressor) such as a polymer polymer, a leveler (smoother) such as a polar surfactant, and a bright compound such as a sulfur compound, for example. There is a toner (brightener). Inhibitors or levelers have the effect of suppressing the growth rate of the plating film by increasing the polarization of the cathode surface. In addition, since the inhibitor is often composed of a high molecular weight polymer or the like, the volume occupied in the space becomes large, and therefore, the inhibitor has a property that it is difficult to enter a narrow recess. Furthermore, since the leveler has a surfactant function and polarity, it tends to adhere to the location where the electrolysis concentrates near the edge of the recess, thus inhibiting the growth of the plating film near the edge of the recess. And it is thought that it has the effect | action which prevents that a bridge | bridging is formed in the upper part of a recessed part. On the other hand, brighteners often contain sulfur compounds and have the effect of increasing the growth rate of the plating film by reducing the polarization of the cathode surface.

  Usually, the wiring used in the LSI is designed to have a certain range of wiring width. For this reason, in the region where the opening diameter of the concave portion such as a trench or a through hole is the smallest and it is difficult to ensure good embedding characteristics, it is included in the plating solution so that good embedding characteristics can be obtained. It is necessary to adjust the additive. In addition, when the adjustment of the additive is not appropriate, the copper film grown from the upper end of the recess comes into contact with each other before the copper film grown by the plating method is sufficiently embedded in the recess. Grows leaving holes. For this reason, if the plating film is removed until the upper surface of the insulating film is exposed by CMP performed after the plating film is formed, wiring having holes is formed, so that such wiring is not formed. It is necessary to adjust the additive contained in the plating solution.

  On the other hand, in order to cope with miniaturization, an additive contained in a plating solution is adjusted so as to obtain a film growth characteristic called bottom-up. Here, bottom-up means that each of the above-described additives is used to increase the inside of the recess by the action of Brightner, and the growth rate inside the recess is faster than the growth rate in other parts. This is a film growth characteristic that improves the embedding characteristic. In bottom-up, while the growth rate of the uppermost layer on the surface of the insulating film is slow, the plating film grows preferentially from the bottom of the recess, so that the possibility of remaining voids in the recess is reduced. For this reason, in the wiring process in which miniaturization of LSIs after the process generation of 130 nm has progressed, a technique using bottom-up is an effective means for ensuring the embedding characteristics in the recess having a high aspect ratio. .

  When improving the embedding characteristics by bottom-up, good embedding characteristics are realized inside the recesses in which the copper film is embedded, while recesses are formed in the upper part of the densely formed recesses. A convex surface that rises thicker than the thickness of the copper film formed on the unformed part is formed. In this way, in a region where minute concave portions are densely formed, a swell called protrusion occurs.

  Protrusion occurs depending on the type of additive contained in the plating solution.Brightener remains on the plating film near the upper end of the recess even after the recess is completely embedded. The growth rate is faster. For this reason, a swell called protrusion occurs, and in particular, it becomes apparent in a region where the wiring density is high where the concave portions are densely formed.

  Here, FIG. 7A shows a cross section of a main part of the semiconductor device for explaining the protrusion.

  As shown in FIG. 7A, the insulating film 102 on the semiconductor substrate 101 is provided with a first recess 102a having a wide opening diameter, such as a trench or a through hole, in the first region Ra. In the second region Rb, for example, a trench or a through hole, and the second recess 102b having a fine opening diameter is formed. They are formed relatively densely (in the figure, there are four second recesses 102b). After forming a diffusion prevention film 102c made of tantalum or the like on the insulating film 102 including the walls and bottom of the first and second recesses 102a and 102b, through a seed layer formed by PVD method or CVD method, When the copper film 103 is formed so as to fill the insides of the first and second recesses 102a and 102b by electrolytic plating, as shown in FIG. 7A, prototrusion is formed in the second region Rb. Is done. Here, the protrusion is a convex amount protruding from the height of the surface of the copper film formed on the insulating film 102 where the first and second concave portions 102a and 102b are not formed (that is, the step d2). ) And the step d2 is usually in the range of 200 nm to 500 nm. On the other hand, in the first region Ra, a step d1 caused by the first recess 102a is formed, and the step d1 is about 200 nm. For this reason, the initial level difference represented by the sum of the level differences d1 and d2 before the subsequent CMP is about 400 to 700 nm.

From the viewpoint of electrolytic concentration or volume due to high molecular weight, the proto-trusion becomes larger as the opening diameter of the second recess 102b formed in the insulating film 102 becomes smaller. The film thickness of the copper film formed on the portion where the recess 102b is formed is approximately twice the film thickness of the copper film formed on the portion of the insulating film 102 where the second recess 102b is not formed. Sometimes.

  Until now, in order to suppress proto-trusion while ensuring the embedding property in the recess, the combination of additives has been optimized for each node of each device. However, in order to ensure the embedding characteristics with the progress of miniaturization, it is necessary to relatively strengthen the action of Brightner, and as a result, it is difficult to suppress the protrusion. As the miniaturization progresses, the opening diameters of the first and second recesses 102a and 102b tend to be reduced, and the depths of the first and second recesses 102a and 102b tend to be shallow. The aspect ratio of the first and second recesses 102a and 102b is not reduced. In this case, since the absolute value of the depth of the first and second recesses 102a and 102b is reduced, the total amount and thickness of the plating film embedded in the first and second recesses 102a and 102b are reduced. In many cases, the amount of protrusion with respect to the thickness of the plated film to be formed does not change relatively.

  Here, FIGS. 7B to 7C are views for explaining a process using CMP after the copper film is formed by the electrolytic plating method described with reference to FIG. .

  As shown in FIG. 7B, in the CMP performed after the copper film 103 is formed by electrolytic plating, the surface of the copper film 103 is removed before the upper ends of the first and second recesses 102a and 102b are exposed. Flatten as much as possible. Thereafter, as shown in FIG. 7C, before and after the exposure of different types of films such as the diffusion prevention film 102c and the insulating film 102, the CMP polishing rate for the different types of films to be polished is adjusted. Thus, the copper film existing outside the region where the wiring is formed is removed. As described above, the surface of the copper film 103 is planarized as much as possible before exposing the first and second recesses 102a and 102b. I am trying to reduce the level difference from other areas.

  Usually, when the depth of the first and second recesses 102a and 102b is about 200 nm, the thickness of the copper film formed by the electrolytic plating method is often set between about 600 to 1500 nm. . As will be described later, this film thickness depends on the planarization performance by CMP, but all the copper films formed outside the first and second recesses 102a and 102b are sacrificed by polishing and removal by CMP. Become a layer.

  Here, the planarization performance in CMP is generally represented by a difference between a first polishing rate in a region having a high height relative to the substrate and a second polishing rate in a region having a low height relative to the substrate. If the first polishing rate can be made larger than the second polishing rate, the planarization performance can be improved. For this reason, if the above-mentioned initial level difference is small, the amount of polishing required to eliminate the initial level difference is reduced, that is, planarization can be realized with a small level of polishing. Therefore, in order to reduce the initial level difference, it is important to reduce the level difference d2 due to the protrusion.

  On the other hand, if the initial level difference is large, increasing the polishing amount to eliminate the level difference after CMP increases the absolute variation in the polishing rate within the wafer surface during CMP. Therefore, it is necessary to absorb this variation in polishing rate. For example, as shown in FIG. 7C, in the step of removing the copper film existing outside the region where the wiring is formed, the film thickness of the portion where the protrusion is formed in the copper film 103 is thick. For this reason, the polishing residue 105 of the copper film 103 may occur, and the polishing residue 105 causes a short circuit between the wirings. In order to absorb the variation in the polishing rate, the copper film existing outside the first and second recesses 102a and 102b is usually completely removed on average using an optical method. After detecting the time as the end point, a time required to extend the polishing called the over-polishing time is required. For this reason, the above-described dissimilar film is exposed at the time of overpolishing, so that dishing 106 occurs in the wiring portion formed in the first recess 102a due to the difference in polishing rate or the second recess 102b. An erosion 107 occurs in the wiring portion to be formed. As described above, when the dishing 106 or the erosion 107 occurs, the wiring resistance increases. Therefore, it is important to reduce variations in the polishing rate.

  In view of the above, an object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce variations in wiring resistance.

  In order to solve the above-described problem, a method of manufacturing a semiconductor device according to one aspect of the present invention includes a first conductive film formed on a substrate and having an insulating film having a plurality of recesses as trenches or holes. Forming a second conductive film on the first conductive film after the step (a) of forming the step, the step (b) of removing the surface layer of the first conductive film, and the step (b). The process (c) and the process (d) which removes the part which exists outside the some recessed part in a 1st electrically conductive film and a 2nd electrically conductive film after a process (c) are provided.

  According to the method for manufacturing a semiconductor device according to one aspect of the present invention, after the first conductive film is formed, the surface layer of the first conductive film is improved by removing the surface layer of the first conductive film. The additive used in forming the first conductive film remaining on the first surface layer can be removed. For this reason, since the second conductive film formed on the first conductive film with improved flatness is formed conformally, generation of protrusion when forming the second conductive film is performed. And the surface flatness of the second conductive film is improved. Therefore, when removing portions of the first conductive film and the second conductive film that exist outside the plurality of recesses, the occurrence of erosion or dishing can be suppressed. As a result, it is possible to suppress variations in wiring resistance.

  In the method for manufacturing a semiconductor device according to one aspect of the present invention, the steps (a) and (c) are preferably performed by an electrolytic plating method using copper.

  In this way, it is possible to effectively suppress prototrusion that occurs when the first conductive film made of copper is formed by electrolytic plating.

  In the method for manufacturing a semiconductor device according to one aspect of the present invention, the first conductive film and the second conductive film are preferably made of the same material.

  In the method for manufacturing a semiconductor device according to one aspect of the present invention, the step (b) preferably includes a step of removing the entire surface layer by a CMP method.

  If the surface layer is completely removed in this manner, for example, steps due to convex portions such as protrusion can be easily reduced.

  In the method for manufacturing a semiconductor device according to one aspect of the present invention, it is preferable that the step (b) includes a step of selectively removing the protrusions on the surface layer by a CMP method.

  Thus, if the convex part in a surface layer is selectively removed, the level | step difference resulting from convex parts, such as a protrusion, can be reduced effectively, and planarization can be implement | achieved more effectively. In addition, since only the convex portions in the surface layer are selectively removed, the film thickness of the first conductive film to be formed can be reduced.

  In this case, the step (b) is preferably performed using an insoluble complex.

  In this way, highly selective polishing by the CMP method can be performed, so that the convex portions on the surface of the first conductive film can be more selectively removed.

  In the method for manufacturing a semiconductor device according to one aspect of the present invention, the step (b) is preferably performed by wet etching.

  In this case, it is preferable to further include a step of oxidizing the surface of the first conductive film after the step (a) and before the step (b).

  In this way, the oxidized surface layer in the first conductive film can be easily removed.

  In the method for manufacturing a semiconductor device according to one aspect of the present invention, the step (b) is preferably performed by brush cleaning.

  Thus, the surface layer of the first conductive film can be removed also by a physical action by the brush.

  In this case, the step (b) is preferably performed using an organic acid as an etchant.

  Thus, the surface layer of the first conductive film can be effectively removed without depending on the surface state of the surface layer of the first conductive film. In particular, in the case where the first conductive film is made of copper plating and the cleaning after plating is only replacement cleaning, the surface of the copper plating may be oxidized in an island shape. By performing brush cleaning using, wet etching of the oxidized region effectively proceeds in addition to removal by physical action on the surface layer.

  In the method for manufacturing a semiconductor device according to one aspect of the present invention, a step (e) of performing a heat treatment on the first conductive film after the step (a) and before the step (b). It is preferable to include.

  In this manner, the surface of the first conductive film can be planarized before the step of removing the surface layer of the first conductive film. For this reason, after the surface layer of the first conductive film is removed, the level difference on the surface of the first conductive film is further reduced.

  In this case, the step (e) is preferably performed in an atmosphere in which a reducing gas is added to an inert nitrogen gas.

  In this way, the surface layer of the first conductive film can be stably removed. For example, when the first conductive film is made of copper, it is possible to prevent copper oxidation from reaching the inside of the copper film during the heat treatment.

  Further, the step (e) is preferably performed while introducing oxygen at least at the final stage of the heat treatment.

  In this manner, an oxide layer can be formed on the surface of the first conductive film that has been planarized, so that the surface layer of the first conductive film can be easily removed.

  Further, the step (e) preferably includes a step of depositing impurities contained in the first conductive film on the surface of the first conductive film.

  In this case, when the surface layer of the first conductive film is removed, impurities deposited on the surface can be effectively removed.

  In addition, it is preferable that the step (c) includes a step of forming the second conductive film by preferentially growing the film from a relatively low portion of the surface of the first conductive film.

  In this way, by forming the second conductive film by using bottom-up in which the film is grown from a relatively low portion of the surface of the first conductive film, the surface of the second conductive film is more Flattened.

  In the method for manufacturing a semiconductor device according to one aspect of the present invention, the method may be a step of forming a first conductive film having a thickness obtained by adding at least the depth of the concave portion to the thickness removed in the step (b). preferable.

  In this way, variations in removal within the wafer surface can be reduced.

  According to the method for manufacturing a semiconductor device of one aspect of the present invention, it is possible to form a conductive pattern such as a wiring or a plug that does not cause a wiring short circuit and does not cause erosion or dishing.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below.

  FIG. 1A to FIG. 1D are cross-sectional views showing a principal part of the semiconductor device manufacturing method according to the first embodiment of the present invention in the order of steps, and FIG. 1A represents each drawing. A first region Ra which is a recess, such as a trench or a through hole (not shown), and which has a wide opening diameter and is relatively sparsely formed; It shows a second region Rb which is a concave portion such as a hole (not shown) and in which the second concave portion 12b having a fine opening diameter is formed relatively densely.

  In each embodiment of the present invention, a case where one first concave portion and four second concave portions are formed in the figure will be described, but the present invention is not limited to this number. A region (Ra) in which a recess having a relatively large opening diameter relative to one recess is formed sparsely, and a region in which a recess having a relatively small opening diameter relative to the other recess is formed densely The present invention can be applied to any level difference generated when an insulating film is formed with respect to (Rb).

  First, as shown in FIG. 1A, an insulating film 12 made of, for example, a silicon oxide film is formed on a semiconductor substrate 11 made of, for example, silicon. Subsequently, a first recess 12a having a wide opening diameter is formed in the insulating film 12 in the first region Ra by, for example, a dry etching method, and a fine fineness is formed in the insulating film 12 in the second region Rb. A second recess 12b having an opening diameter is formed. Subsequently, a diffusion prevention film 12c made of, for example, tantalum is formed on the insulating film 12 including the bottom and wall portions of the first recess 12a and the second recess 12b. Subsequently, a copper seed layer (not shown) at the time of electrolytic plating described later is formed by using a PVD method (Phycal Vapor Deposition) or a CVD method (Chemical Vapor Deposition). Subsequently, the first recess 12a and the second recesses are formed on the insulating film 12 by a first electrolytic plating method using a liquid (hereinafter, referred to as a plating solution) containing an additive in a liquid such as a copper sulfate solution. The first copper film 13 is formed so as to fill the recesses 12b. In addition, as a general additive included in the plating solution, as described above, for example, an inhibitor (suppressor) such as a polymer, a leveler (smooth agent) such as a polar surfactant, for example, a sulfur compound. Such as brighteners (brighteners). Here, for example, a plating solution containing, for example, a brightener is usually used for the purpose of improving the embedding characteristics in the second recess 12b having a fine opening diameter by utilizing the above-described bottom-up. For this reason, the upper portion of the second recess 12b in the second region Rb protrudes beyond the surface height of the first copper film 13 formed on the region other than the region where the second recess 12b is formed. Protrusion is formed. Here, as shown in the figure, the level difference d2 caused by the protrusion is higher than the surface height of the first copper film 13 formed on the region other than the region where the second recess 12b is formed in Rb. Expressed by the protruding amount of protrusion. On the other hand, the first copper film 13 is formed on a region other than the region where the first recess 12a is formed above the first recess 12a in the first region Ra. It is recessed more than the surface height of. And the level | step difference d1 resulting from the dent is represented by the quantity dented rather than the surface height of the 1st copper film 13 formed on area | regions other than the area | region where the 1st recessed part 12a is formed in Ra. The

  In the step shown in FIG. 1A, the first copper film 13 is preferably formed to have a film thickness equal to or greater than the depth of the first recess 12a and the second recess 12b. The thickness is set to be equal to or larger than the thickness obtained by adding the depth of the first recess 12a and the second recess 12b to the thickness of removing the entire surface layer of the first copper film 13 by the first CMP performed in the next step. It is still preferred. In this way, it is possible to reduce variations in the polishing rate within the wafer surface during the first CMP.

  Next, as shown in FIG. 1B, the surface layer 13a in the first copper film 13 shown in FIG. 1A is entirely removed by polishing by the first CMP. As shown, the first copper film 13b remains after the surface layer 13a is removed.

  Here, in the first CMP, a chemical solution containing abrasive particles called slurry is dropped on the polishing pad, and the first copper film 13 side to be the film to be polished is pressed against the polishing pad, thereby forming the surface layer 13a. Remove by polishing. The film thickness of the surface layer 13a to be removed by polishing may be a thickness that can remove at least a portion where the additive contained in the plating solution remains. Further, the first CMP may be performed by a process in which the polishing rate can be easily controlled. Specifically, when the surface layer 13a of the first copper film 13 is removed by polishing, it is usually desirable for the polishing rate to be about 20 (nm / min) or more for the stability of the process. When the depth of the first recess 12a and the second recess 12b is about 200 nm, the thickness of the first copper film 13 formed by the first plating method is about 230 nm, and the first CMP is performed. Thus, the surface layer 13a is removed by polishing for a thickness of about 30 nm. In this case, the initial step before performing the first CMP is expressed by the sum of the steps d1 and d2 shown in FIG. 1A as described above, but is caused by the wide first recess 12a. Although it depends on the level of the step d1 of about 200 nm and the type of additive contained in the plating solution, it is the sum of the level difference d2 of about 150 nm due to prototrusion and the initial step (d1 + d2) is about 350 nm.

  In the first CMP, since the surface layer 13a is entirely removed by polishing, it is desirable to perform the first CMP using a soft polishing pad having excellent surface followability such as a nonwoven fabric. The soft polishing pad is also effective in controlling the polishing rate low. In addition, by using a soft polishing pad, the polishing pad can be made to follow the entire surface layer 13a. However, in the region where the prototrusion in the second region Rb is formed, the region on the first recess 12a is formed. Since the pressure during polishing is larger than that, the amount of polishing is increased, and the planarization of the surface of the first copper film 13b is improved. Here, the soft pad and the hard pad in the second embodiment described later may be defined as a soft pad having a Shore hardness of less than 10 and a hard pad having a Shore hardness of 80 or less, for example. However, the soft pad as used in the present embodiment means that the entire surface of the first copper film 13 can be removed by polishing. The hard pad referred to in the second embodiment means that it is sufficient if the convex portion on the surface of the first copper film 23 can be selectively removed.

  In this way, the surface layer 13a of the first copper film 13 formed by the first electrolytic plating method and containing the additive is completely removed, thereby causing the additive in the plating solution. Remove the cause of the protrusion to occur.

  Next, as shown in FIG. 1C, a second copper film 14 is formed on the first copper film 13b by a second electrolytic plating method. At the time of forming the second copper film 14 by the second electrolytic plating method, the additive has already been removed together with the removal of the surface layer 13a of the first copper film 13, and therefore the second copper film No. 14 is deposited conformally and does not cause any new protrusion. For this reason, the surface step difference is not increased by the second electrolytic plating method. As a result, the film thickness of the second copper film 14 depends on the planarization performance in the second CMP, which will be described later. For example, when polishing is performed in an amount necessary to eliminate the initial step, It is preferable to set so that polishing can be performed at a height higher than the surface height of the insulating film 12 in the region where the first recess 12a and the second recess 12b are not formed (that is, overpolishing is not performed).

  Further, since the widths of the first recess 12a and the second recess 12b in which wirings are formed are normally designed within a certain range, the first CMP in the process shown in FIG. After the surface layer 13a is completely removed by the above, a recess remains in the first copper film 13b above the first recess 12a in the first region Ra. Therefore, in the step shown in FIG. 1C, the additive used for the second electrolytic plating is performed so that a bottom-up film growth characteristic using the depression of the first copper film 13b above the first depression 12a is generated. The flatness of the formed second copper film 14 can be further improved by adjusting the agent.

  Next, as shown in FIG. 1 (d), the first copper film 13b and the second copper film 14 existing outside the first recess 12a and the second recess 12b by the second CMP. Remove. Thereby, the first wiring 13c having a wide wiring width and the second wiring 13d having a fine wiring width are formed.

  As described above, according to the manufacturing method of the semiconductor device according to the first embodiment of the present invention, after the first copper film 13 is formed by the first electrolytic plating method, the first CMP is used. By removing the entire surface layer 13a, the surface flatness of the first copper film 13b is improved, and the additive used when forming the first copper film 13 remaining on the surface layer 13a is removed. Can do. Therefore, when the second copper film 14 is formed by the second electrolytic plating method on the first copper film 13b remaining after the surface layer 13a containing the additive is removed, the second copper film 14 is Conformally formed, the occurrence of proto-trusion is suppressed, the initial step is reduced, and the surface flatness of the second copper film 14 is improved. Therefore, when the first copper film 13b and the second copper film 14 existing outside the first recess 12a and the second recess 12b are removed by the second CMP, generation of erosion or dishing is suppressed. Is done. As a result, it is possible to suppress variations in wiring resistance.

  For example, after depositing a barrier film or a seed film, in a state where the groove depth is 200 nm and the groove width is 500 nm before the Cu film is plated, if the formation of the Cu film by the plating method is 230 nm, the Cu film When conformally formed following the underlying groove step by plating, a recess with a maximum depth of 200 nm and a width of about 40 nm remains near the center of the process groove, depending on the plating method and plating solution. become. Depending on the process conditions for removing the surface layer on the entire surface of the Cu film, in such a narrow recess, when the surface layer is removed by 30 nm by the first CMP, only about 30 nm on both sides of the recess is polished and removed, and the depth is 170 nm. A concave step with a width of about 40 nm remains. The concave portion remaining in such a narrow width acts as a bottom-up when the Cu film is formed by the second electrolytic plating method, and the wide wiring portion remaining in the conventional Cu film formation by one electrolytic plating is used. The step can be reduced.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below.

  FIGS. 2A to 2D are cross-sectional views showing the main part of the semiconductor device manufacturing method according to the second embodiment of the present invention in the order of steps, and FIG. 2A represents each drawing. A first region Ra which is a recess such as a trench or a through hole (not shown), and has a relatively wide first opening 22a, and a trench or a through, for example. A second region Rb, which is a concave portion such as a hole (not shown) and in which the second concave portion 22b having a fine opening diameter is formed relatively densely, is shown.

  First, as shown in FIG. 2A, an insulating film 22 made of, for example, a silicon oxide film is formed on a semiconductor substrate 21 made of, for example, silicon. Subsequently, a first recess 22a having a wide opening diameter is formed in the insulating film 22 in the first region Ra, for example, by dry etching, and a fine portion is formed in the insulating film 22 in the second region Rb. A second recess 22b having an opening diameter is formed. Subsequently, a diffusion prevention film 22c made of, for example, tantalum or the like is formed on the insulating film 22 including the bottom and wall portions of the first recess 22a and the second recess 22b. Subsequently, a copper seed layer (not shown) at the time of electrolytic plating described later is formed by using a PVD method (Phycal Vapor Deposition) or a CVD method (Chemical Vapor Deposition). Subsequently, the first recess 22a and the second recess 22b are embedded in the insulating film 22 by the first electrolytic plating method using the same plating solution as in the first embodiment. A copper film 23 is formed. Here, the use of a plating solution containing, for example, a brightener for the purpose of improving the embedding property in the second recess 22b having a fine opening diameter by utilizing the bottom-up described above is the same as the first embodiment. It is the same. Therefore, the upper portion of the second recess 22b in the second region Rb protrudes from the surface height of the first copper film 23 formed on the region other than the region where the second recess 22b is formed. Protrusion is formed. On the other hand, the first copper film 23 is formed on the region other than the region where the first recess 22a is formed above the first recess 22a in the first region Ra. It is recessed more than the surface height of. As in the first embodiment described above, the step due to the dent in the first region Ra is denoted as d1, and the step due to the prototrusion in the second region Rb is denoted as d2.

  In the step shown in FIG. 2A, the first copper film 23 is preferably formed so as to have a film thickness equal to or greater than the depth of the first recess 22a and the second recess 22b. The thickness of the first concave portion 22a and the second concave portion 22b is added to the depth to selectively remove the convex portion 23a of the first copper film 23 by the first CMP performed in the next process. It is preferable to form. In this way, it is possible to reduce variations in the polishing rate within the wafer surface during the first CMP.

  Next, as shown in FIG. 2B, the convex portions 23a in the surface layer of the first copper film 23 shown in FIG. 2A are selectively removed by polishing by the first CMP. As shown in the figure, the first copper film 23b remains after the protrusion 23a is removed.

  Here, in the first CMP, a chemical solution containing abrasive particles called a slurry is dropped on the polishing pad, and the first copper film 23 side to be the film to be polished is pressed against the polishing pad, so that the convex portion 23a is formed. Remove by polishing. Here, in order to selectively remove the protrusions 23a in the first copper film 23, it is desirable to use a hard pad with low surface followability. In this case, it is desirable that the processing pressure during the first CMP be 2 Psi or less in order to suppress the follow-up to the surface of the first copper film 23 caused by the deformation of the hard pad. Further, as shown in FIG. 2B, for the purpose of improving the selectivity in the first CMP, in the recessed portion of the first copper film 23 in the first region Ra where the degree of contact with the polishing pad is low, It is more desirable to perform the first CMP after forming the insoluble complex 24. In this case, since the insoluble complex 24 described above remains in the recessed portion in the first region Ra that remains slightly after the first CMP, the second electrolytic plating as the next step is performed. Before performing the step, it is necessary to remove the region where the insoluble complex 24 remains, for example, by applying a reverse bias.

  Further, in the first CMP, about 30 nm is removed at the highest portion of the convex portion 23a of the first copper film 23 on the second concave portion 22b. Therefore, for example, when the depth of the first recess 22a and the second recess 22b is about 200 nm, the first copper film 23 formed by the first plating method in the step shown in FIG. A film thickness of about 230 nm is sufficient. Thus, the film thickness of the first copper film 23 to be formed can be reduced by selectively removing the protrusions 23a on the surface of the first copper film 23 by the first CMP. Therefore, as described above, the initial level difference before the first CMP is represented by the sum of the level differences d1 and d2 shown in FIG. 1A, but is caused by the wide first recess 22a. Although it depends on the level of the step d1 of about 200 nm and the type of additive contained in the plating solution, it is the sum of the step d2 of about 50 nm due to the protrusion and the initial step (d1 + d2) is about 250 nm. Since the initial level difference is reduced, in this embodiment, the surface flatness after the first CMP and the second CMP described later can be further improved.

  Next, as shown in FIG. 2C, a second copper film 25 is formed on the first copper film 23b by a second electrolytic plating method. At the time of forming the second copper film 25 by the second electrolytic plating method, the additive is removed at the same time as the protrusion 23a of the first copper film 23 is removed. The second copper film 25 is deposited conformally and does not cause any new protrusion. For this reason, the surface step difference is not increased by the second electrolytic plating method. For this reason, the film thickness of the second copper film 25 depends on the planarization performance in the second CMP, which will be described later, but, for example, when a necessary amount of polishing is performed to eliminate the initial step, It is preferable to set so that polishing can be performed at a level higher than the surface height of the insulating film 22 in a region where the first recess 22a and the second recess 22b are not formed (that is, overpolishing is not performed).

  In addition, since the widths of the first recess 22a and the second recess 22b in which wirings and the like are normally formed are designed within a certain range, the first CMP in the process shown in FIG. After the convex portion 23b is selectively removed by the above, even in the present embodiment, the concave portion remains in the first copper film 23b in the upper portion of the second concave portion 22a in the first region Ra. . Therefore, in the step shown in FIG. 2C, the plating used for the second electrolytic plating is performed so that a bottom-up film growth characteristic using the depression of the first copper film 23b above the first depression 22a is generated. By adjusting the additive to be added to the liquid, the flatness of the formed second copper film 25 can be further improved.

  Next, as shown in FIG. 2D, the first copper film 23b and the second copper film 25 existing outside the first recess 22a and the second recess 22b by the second CMP. Remove. As a result, the first wiring 23c having a wide wiring width and the second wiring 23d having a fine wiring width are formed.

  As described above, according to the method for manufacturing a semiconductor device according to the second embodiment of the present invention, after the first copper film 23 is formed by the first electrolytic plating method, the first CMP is used. By selectively removing the convex portion 23a on the surface, the surface flatness of the first copper film 23b is improved, and the additive used when forming the first copper film 23 remaining on the convex portion 23a is removed. can do. Therefore, when the second copper film 25 is formed by the second electrolytic plating method on the first copper film 23b remaining after the surface layer 23a containing the additive is removed, the second copper film 25 is Conformally formed, the occurrence of proto-trusion is suppressed, the initial step is reduced, and the surface flatness of the second copper film 25 is improved. In particular, in the second embodiment, by selectively removing the protrusions 23a in the first copper film 23, the first copper film 23b after the removal of the protrusions 23a and the second copper film formed after that are formed. The surface flatness of the copper film 25 is further improved. Therefore, when the first copper film 23b and the second copper film 25 existing outside the first recess 22a and the second recess 22b are removed by the second CMP, erosion or dishing is more generated. Can be suppressed. As a result, it is possible to further suppress variations in wiring resistance. Further, the convex portion 23a in the first copper film 23 is selectively removed, and the concave portion of the first copper film 23 formed on the first concave portion 22a is hardly removed. The film thickness of the copper film 23 can be reduced.

(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described below.

  FIGS. 3A to 3D are cross-sectional views of relevant parts showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps, and FIG. 3A represents each drawing. A first region Ra which is a concave portion such as a trench or a through hole (not shown) and which has a wide opening diameter and is relatively sparsely formed; The second region Rb is a concave portion such as a hole (not shown), and the second concave portion 42b having a fine opening diameter is formed relatively densely.

  First, as shown in FIG. 3A, an insulating film 42 made of, for example, a silicon oxide film is formed on a semiconductor substrate 41 made of, for example, silicon. Subsequently, a first recess 42a having a wide opening diameter is formed in the insulating film 42 in the first region Ra by, for example, a dry etching method, and a fine fineness is formed in the insulating film 42 in the second region Rb. A second recess 42b having an opening diameter is formed. Subsequently, a diffusion prevention film 42c made of, for example, tantalum or the like is formed on the insulating film 42 including the bottom and wall portions of the first recess 42a and the second recess 42b. Subsequently, a copper seed layer (not shown) at the time of electrolytic plating described later is formed by using a PVD method (Phycal Vapor Deposition) or a CVD method (Chemical Vapor Deposition). Subsequently, the first concave portion 42a and the second concave portion 42b are embedded in the insulating film 42 by the first electrolytic plating method using the same plating solution as in the first embodiment. A copper film 43 is formed. Here, the use of a plating solution containing, for example, a brightener for the purpose of improving the embedding characteristics in the second recess 42b having a fine opening diameter by utilizing the above-described bottom-up is generally the same as in the first embodiment. It is the same. Therefore, the upper portion of the second recess 42b in the second region Rb protrudes from the surface height of the first copper film 43 formed on the region other than the region where the second recess 42b is formed. Protrusion is formed. On the other hand, the first copper film 43 is a first copper film 43 formed on a region other than the region where the first recess 42a is formed above the first recess 42a in the first region Ra. It is recessed more than the surface height of. As in the first embodiment described above, the step due to the dent in the first region Ra is denoted as d1, and the step due to the prototrusion in the second region Rb is denoted as d2.

  In the step shown in FIG. 3A, the first copper film 43 is preferably formed so as to have a film thickness equal to or greater than the depth of the first recess 42a and the second recess 42b. A thickness is added to the depth of the first recess 42a and the second recess 42b to completely remove the surface layer 43a of the first copper film 43 by wet etching performed in the next step (see FIG. 3B). It is preferable to form so as to have a different thickness. In this way, the variation in the etching rate within the wafer surface during wet etching can be reduced.

  Next, as shown in FIG. 3B, the surface layer 43a of the first copper film 43 is entirely removed by wet etching using an inorganic acid such as dilute sulfuric acid. As shown in the figure, the first copper film 43b remains after the surface layer 43a is removed.

  Here, as wet etching, a manufacturing apparatus having a spin rinse function is usually used. Further, the film thickness of the surface layer 43a to be removed by wet etching may be a thickness that can remove at least a portion where the additive contained in the plating solution remains, and is a process in which the etching rate can be easily controlled. Wet etching should be performed. Specifically, when the first copper film 43a is removed by wet etching, the etching rate is usually about 30 (nm / min) or more, which is a restriction on process controllability. When the depth of the first concave portion 42a and the second concave portion 42b is about 200 nm, the thickness of the first copper film 43 formed by the first plating method is about 230 nm. The surface layer 43a is removed by etching to a thickness of about 30 nm. In this case, the initial step before the wet etching is represented by the sum of the steps d1 and d2 shown in FIG. 3A as described above, but the step d1 caused by the wide first recess 42a. However, depending on the type of additive contained in the plating solution, the total difference between the step d2 due to prototrusion is about 150 nm and the initial step (d1 + d2) is about 350 nm.

  Next, as shown in FIG. 3C, a second copper film 44 is formed on the first copper film 43b by a second electrolytic plating method. When the second copper film 44 is formed by the second electrolytic plating method, the additive has already been removed together with the removal of the surface layer 43a of the first copper film 43 described above, so the second copper film 44 is deposited conformally and does not cause any new proto-trusion. For this reason, the surface step difference is not increased by the second electrolytic plating method. For this reason, the thickness of the second copper film 44 depends on the planarization performance in CMP, which will be described later. For example, when the amount of polishing necessary for eliminating the initial step is performed, It is preferable to set so that polishing can be performed at a level higher than the surface height of the insulating film 42 in a region where the recess 42a and the second recess 42b are not formed (that is, overpolishing is not performed).

  In addition, since the width of the first concave portion 42a and the second concave portion 42b in which wirings and the like are normally formed is designed in a certain range, the surface is formed by wet etching in the process shown in FIG. After the layer 43a is completely removed, a recess remains in the first copper film 43b above the first recess 42a in the first region Ra. Therefore, in the step shown in FIG. 4C, the additive used for the second electrolytic plating is performed so that a bottom-up film growth characteristic using the depression of the first copper film 43b in the upper part of the first depression 42a is generated. The flatness of the formed second copper film 44 can be further improved by adjusting the agent.

  Next, as shown in FIG. 3D, the first copper film 43b and the second copper film 44 existing outside the first recess 42a and the second recess 42b are removed by CMP. . As a result, the first wiring 43c having a wide wiring width and the second wiring 43d having a fine wiring width are formed.

  As described above, according to the manufacturing method of the semiconductor device according to the third embodiment of the present invention, after the first copper film 43 is formed by the first electrolytic plating method, the surface layer 43a is formed by wet etching. By removing the entire surface, it is possible to improve the surface flatness of the first copper film 43b and to remove the additive used when forming the first copper film 43 remaining on the surface layer 43a. Therefore, when the second copper film 44 is formed by the second electrolytic plating method on the first copper film 43b remaining after the surface layer 43a containing the additive is removed, the second copper film 44 is Conformally formed, the occurrence of prototrusion is suppressed, the initial step is reduced, and the surface flatness of the second copper film 44 is improved. Therefore, when the first copper film 43b and the second copper film 44 existing outside the first recess 42a and the second recess 42b are removed by CMP, the occurrence of erosion or dishing is suppressed. As a result, it is possible to suppress variations in wiring resistance.

(Fourth embodiment)
A method for manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described below.

  4 (a) to 4 (d) are cross-sectional views of relevant parts showing a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps, and FIG. 4 (a) represents each drawing. A first region Ra which is a concave portion such as a trench or a through hole (not shown) and which has a wide opening diameter and is relatively sparsely formed; The second region Rb is a concave portion such as a hole (not shown), and the second concave portion 52b having a fine opening diameter is formed relatively densely.

  First, as shown in FIG. 4A, an insulating film 52 made of, for example, a silicon oxide film is formed on a semiconductor substrate 51 made of, for example, silicon. Subsequently, a first recess 52a having a wide opening diameter is formed in the insulating film 52 in the first region Ra, for example, by a dry etching method, and the insulating film 52 is finely formed in the second region Rb. A second recess 52b having an opening diameter is formed. Subsequently, a diffusion prevention film 52c made of, for example, tantalum or the like is formed on the insulating film 52 including the bottom and wall portions of the first recess 52a and the second recess 52b. Subsequently, a copper seed layer (not shown) at the time of electrolytic plating described later is formed by using a PVD method (Phycal Vapor Deposition) or a CVD method (Chemical Vapor Deposition). Subsequently, the first recess 52a and the second recess 52b are embedded on the insulating film 52 by the first electrolytic plating method using the same plating solution as that of the first embodiment. A copper film 53 is formed. Here, the use of a plating solution containing, for example, a brightener for the purpose of improving the embedding characteristics in the second recess 52b having a fine opening diameter by utilizing the bottom-up described above is generally the same as in the first embodiment. It is the same. Therefore, the upper portion of the second recess 52b in the second region Rb protrudes from the surface height of the first copper film 53 formed on the region other than the region where the second recess 52b is formed. Protrusion is formed. On the other hand, the first copper film 53 is formed on a region other than the region where the first recess 52a is formed above the first recess 52a in the first region Ra. It is recessed more than the surface height of. As in the first embodiment described above, the step due to the dent in the first region Ra is denoted as d1, and the step due to the prototrusion in the second region Rb is denoted as d2.

  In the step shown in FIG. 4A, the first copper film 53 is preferably formed so as to have a film thickness equal to or greater than the depth of the first recess 52a and the second recess 52b. A film obtained by adding the film thickness (several nm) at which the first copper film 53 is oxidized by the oxidation process performed in the next step (see FIG. 4B) to the depth of the first recess 52a and the second recess 52b. It is preferable to form so as to have a thickness. In this way, it is possible to reduce variations in the polishing surface within the wafer surface during the first CMP (see FIG. 4C).

  Next, as shown in FIG. 4B, the surface oxide layer 53a is formed by oxidizing the entire surface layer of the first copper film 53 by several nm using, for example, ozone water.

  Next, as shown in FIG. 4C, only the surface oxide layer 53a oxidized by ozone in the first copper film 53 is removed by wet etching using an organic acid such as oxalic acid or citric acid, for example. To do. As shown in the figure, the first copper film 53b remains after the surface oxide layer 53a is removed.

  Here, since the organic acid has a property of dissolving only the copper oxide layer, an extremely thin surface oxide layer 53a is formed by controlling the amount of oxidation by ozone water, and then the film thickness is thin by the organic acid. The surface oxide layer 53a can be removed. In this case, since the additive contained in the plating solution used at the time of the first electrolytic plating remains on the surface oxide layer 53a, the additive causing the occurrence of prototrusion is removed in this step. Can do. In addition, the organic acid dissolves in the oxidized copper, but does not dissolve in the unoxidized bulk copper. Therefore, the surface thickness oxidized and removed in the first copper film 53 is extremely accurate. Can be adjusted. In this case, as described above, the initial step before removing the surface oxide layer 53a is represented by the sum of the steps d1 and d2 shown in FIG. 4A, but the wide first recess 52a. However, depending on the type of additive contained in the plating solution, the total difference is about 150 nm of the step d2 caused by the protrusion, and the initial step (d1 + d2) is about 350 nm. is there.

  Next, as shown in FIG. 4D, a second copper film 54 is formed on the first copper film 53b by a second electrolytic plating method. When the second copper film 54 is formed by the second electrolytic plating method, the additive has already been removed together with the removal of the surface oxide layer 53a of the first copper film 53 described above. The film 54 is deposited conformally and does not cause any new prototrusion. For this reason, the surface step difference is not increased by the second electrolytic plating method. For this reason, the thickness of the second copper film 54 depends on the planarization performance in CMP, which will be described later. For example, when the amount of polishing necessary for eliminating the initial step is performed, It is preferable to set so that polishing can be performed at a height higher than the surface height of the insulating film 52 in a region where the recess 52a and the second recess 52b are not formed (that is, overpolishing is not performed).

  Further, since the widths of the first recess 52a and the second recess 52b in which wirings are formed are usually designed within a certain range, the surface oxide layer 53a in the process shown in FIG. After the removal, the dent remains in the first copper film 53b above the first recess 52a in the first region Ra. Therefore, in the step shown in FIG. 4C, the addition used for the second electrolytic plating is performed so that bottom-up film growth characteristics using the depression of the first copper film 53b above the first depression 52a are generated. By adjusting the agent, the flatness of the formed second copper film 54 can be further improved.

  Next, as shown in FIG. 4E, the first copper film 53b and the second copper film 54 existing outside the first recess 52a and the second recess 52b are removed by CMP. . As a result, a first wiring 53c having a wide wiring width and a second wiring 53d having a fine wiring width are formed.

  As described above, according to the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, after forming the first copper film 53 by the first electrolytic plating method, the surface of the first copper film 53 is formed. The oxide layer 53a is formed, and then the surface oxide layer 53a is removed using an organic acid, thereby removing the additive in the plating solution used when forming the first copper film 53 remaining on the surface oxide layer 53a. In addition, the thickness of the surface oxide layer 53a to be removed by using an organic acid can be adjusted with high accuracy. Therefore, when the second copper film 54 is formed by the second electrolytic plating method on the first copper film 53b remaining after the surface oxide layer 53a containing the additive is removed, the second copper film 54 is formed. Is formed conformally, suppresses the occurrence of protrusion, reduces the initial step, and improves the surface flatness of the second copper film 54. Therefore, by removing the first copper film 53b and the second copper film 54 existing outside the first recess 52a and the second recess 52b by CMP, generation of erosion or dishing can be suppressed. it can. As a result, variations in wiring resistance are suppressed.

(Fifth embodiment)
Hereinafter, a method for fabricating a semiconductor device according to the fifth embodiment of the present invention will be described.

  FIG. 5A to FIG. 5D are cross-sectional views showing the principal part of the semiconductor device manufacturing method according to the fifth embodiment of the present invention in the order of steps, and FIG. 5A represents each drawing. A first region Ra which is a recess such as a trench or a through hole (not shown), and has a relatively wide first opening 22a, and a trench or a through, for example. A second region Rb, which is a concave portion such as a hole (not shown) and in which the second concave portion 22b having a fine opening diameter is formed relatively densely, is shown.

  First, as shown in FIG. 5A, an insulating film 62 made of, for example, a silicon oxide film is formed on a semiconductor substrate 61 made of, for example, silicon. Subsequently, a first recess 62a having a wide opening diameter is formed in the insulating film 62 in the first region Ra by, for example, a dry etching method, and a fine fineness is formed in the insulating film 62 in the second region Rb. A second recess 62b having an opening diameter is formed. Subsequently, a diffusion prevention film 62c made of, for example, tantalum is formed on the insulating film 62 including the bottom and wall portions of the first recess 62a and the second recess 62b. Subsequently, a copper seed layer (not shown) at the time of electrolytic plating described later is formed by using a PVD method (Phycal Vapor Deposition) or a CVD method (Chemical Vapor Deposition). Subsequently, the first recess 62a and the second recess 62b are embedded on the insulating film 62 by the first electrolytic plating method using the same plating solution as that of the first embodiment. A copper film 63 is formed. Here, the use of a plating solution containing, for example, a brightener for the purpose of improving the embedding characteristics in the second recess 62b having a fine opening diameter by using the bottom-up described above is generally the same as in the first embodiment. It is the same. Therefore, the upper portion of the second recess 62b in the second region Rb protrudes from the surface height of the first copper film 63 formed on the region other than the region where the second recess 62b is formed. Protrusion is formed. On the other hand, the first copper film 63 is formed above the first recess 62a in the first region Ra on the region other than the region where the first recess 62a is formed. It is recessed more than the surface height of. As in the first embodiment described above, the step due to the dent in the first region Ra is denoted as d1, and the step due to the prototrusion in the second region Rb is denoted as d2.

  In the step shown in FIG. 5A, the first copper film 63 is preferably formed so as to have a film thickness equal to or greater than the depth of the first recess 62a and the second recess 62b. The thickness of the first concave portion 62a and the second concave portion 62b is added to the depth to selectively remove the surface layer 63a of the first copper film 63 by the first CMP performed in the next step. It is preferable to form. In this way, it is possible to reduce variations in the polishing rate within the wafer surface during the first CMP. In this case, the initial step before the surface layer 63a is removed in the next step is represented by the sum of the steps d1 and d2 shown in FIG. Although it depends on the type of the additive contained in the plating solution and about 200 nm of the step d1 caused by the recess 62a, it is a total of about 150 nm of the step d2 caused by the protrusion, and the initial step (d1 + d2) is 350 nm. Degree.

  Next, as shown in FIG. 5B, the entire surface layer 63a in the first copper film 63 shown in FIG. 5A is removed by first CMP. Here, the surface layer 63a is removed by applying a physical force to the surface of the first copper film 63 and cleaning it using a brush 64 formed of a material such as PVA (polyvinyl acetal). . In this brush cleaning, for example, a roll-shaped brush having protrusions is pressed against the surfaces of both surfaces of the wafer, the number of rotations of the brush is set to 50 to 800 rpm, and the rotation of the wafer is set to 1 to 200 rpm. The pressure is such that an amount of indentation of 0.1 mm or more with respect to the surface can be secured, and rinsing with DIW (Distilled Ion Water) is performed. In this case, since the additive contained in the plating solution used at the time of the first electrolytic plating remains on the surface layer 63a, in this step, the additive causing the occurrence of prototrusion can be removed. it can.

Further, the first copper film 63 formed by the first plating method depends on the cleaning method after plating, but when only the plating solution replacement cleaning using DIW, for example, is performed, the surface is formed in an island shape. May be oxidized. Therefore, in such a case, when brush cleaning is performed using an organic acid such as oxalic acid or citric acid, in addition to the physical action of the brush, wet etching on the oxidized region by the organic acid proceeds, and the effect Next, as shown in FIG. 5C, a second copper film 65 is formed on the first copper film 63b by a second electrolytic plating method. When the second copper film 65 is formed by the second electrolytic plating method, the additive remaining on the surface layer 63a is removed at the same time as the surface layer 63a of the first copper film 63 is removed. Therefore, the second copper film 65 is deposited conformally and does not newly cause prototrusion. For this reason, the surface step difference is not increased by the second electrolytic plating method. For this reason, the thickness of the second copper film 65 depends on the planarization performance in CMP, which will be described later. For example, when the amount of polishing necessary for eliminating the initial step is performed, It is preferable to set so that polishing can be performed at a height higher than the surface height of the insulating film 62 in a region where the recess 62a and the second recess 62b are not formed (that is, overpolishing is not performed).

  In addition, since the width of the first recess 62a and the second recess 62b in which the wiring is formed is normally designed within a certain range, the surface is cleaned by brush cleaning in the process shown in FIG. After the layer 63a is removed, even in the present embodiment, a recess remains in the first copper film 63b above the second recess 62a in the first region Ra. Therefore, in the step shown in FIG. 5C, the plating used for the second electrolytic plating so as to produce a bottom-up film growth characteristic using the depression of the first copper film 63b above the first depression 62a. By adjusting the additive added to the liquid, the flatness of the formed second copper film 65 can be further improved.

  Next, as shown in FIG. 5D, the first copper film 63b and the second copper film 65 existing outside the first recess 62a and the second recess 62b are removed by CMP. . As a result, a first wiring 63c having a wide wiring width and a second wiring 63d having a fine wiring width are formed.

  As described above, according to the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention, after forming the first copper film 63 by the first electrolytic plating method, the physical using brush cleaning is performed. By removing the surface layer 63a using the action, the surface flatness of the first copper film 63 is improved, and the additive used when forming the first copper film 63 remaining on the surface layer 63a is added. Can be removed. Therefore, when the second copper film 65 is formed by the second electrolytic plating method on the first copper film 63b remaining after the surface layer 63a containing the additive is removed, the second copper film 65 is Conformally formed, the occurrence of proto-trusion is suppressed, the initial step is reduced, and the surface flatness of the second copper film 65 is improved. Therefore, when the first copper film 63b and the second copper film 65 existing outside the first recess 62a and the second recess 62b are removed by CMP, generation of erosion or dishing is further suppressed. Can do. As a result, it is possible to further suppress variations in wiring resistance.

(Sixth embodiment)
The method for manufacturing a semiconductor device according to the sixth embodiment of the present invention will be described below.

  FIGS. 6A to 6D are cross-sectional views showing the principal part of the method of manufacturing a semiconductor device according to the sixth embodiment of the present invention in the order of steps, and FIG. A first region Ra which is a concave portion such as a trench or a through hole (not shown) and which has a wide opening diameter and is relatively sparsely formed; The second region Rb is a concave portion such as a hole (not shown), and the second concave portion 72b having a fine opening diameter is formed relatively densely.

  The method for manufacturing a semiconductor device according to the sixth embodiment of the present invention is after the first copper film is formed by the first plating method and before the surface layer of the first copper film is removed. The present invention is characterized in that it includes a step of performing a heat treatment, and this step can be applied to all the semiconductor device manufacturing methods according to the first to fifth embodiments described above. Hereinafter, a case where the heat treatment process, which is a feature of the present embodiment, is applied to the semiconductor device manufacturing method according to the above-described fifth embodiment will be described as an example. For this reason, in the following, the parts common to the description in the fifth embodiment will not be repeated.

  First, as shown in FIG. 6A, an insulating film 72 having a first recess 72a and a second recess 72b is formed on a semiconductor substrate 71 in the same manner as the process shown in FIG. Then, a diffusion prevention film 72c and a first copper film 73 are sequentially formed on the insulating film 72 including the insides of the first recess 72a and the second recess 72b.

  Next, as shown in FIG. 6B, a heat treatment 74 is performed. Thereby, the copper atom which comprises the 1st copper film 73 migrates, and the smoothing of the surface of the 1st copper film 73 advances. That is, the surface can be flattened as compared with the case where heat treatment is not performed.

  In addition to the additive used in the first plating method, impurities remaining in the copper film and the like are grown on the surface layer of the first copper film 73 after the heat treatment step. It is precipitated in the process. For this reason, in the process of removing the surface layer of the first copper film 73 performed in the next process, by removing these additives and impurities, it is possible to suppress the occurrence of protrusion caused by the remaining additives. In addition, impurities contained in the first copper film 73 can be effectively removed. Here, examples of impurities deposited on the surface layer of the first copper film 73 include Sn, Al, Ag, Ti, Mn, S, C, and Cl.

  In addition, since the first copper film formed by the first plating method has grain growth with the passage of time called self-annealing, the characteristics of the copper film change in this process. For this reason, in the step of removing the surface layer of the first copper film 73 performed in the next step, for example, CMP or wet etching, the rate of removing the surface layer of the first copper film 73 may be made unstable. is there. Therefore, the heat treatment here is performed in an inert nitrogen gas in a range of 100 ° C. to 500 ° C. using resistance overheating, lamp heat, or furnace so that the copper oxidation does not reach the inside of the copper film. It is preferable to carry out by adding hydrogen having reducibility.

  Further, in the final stage of the heat treatment, it is possible to form an oxide layer (not shown) having a certain thickness on the surface of the first copper film 73 by introducing low concentration oxygen. If this step is used, the formation of an oxide layer by ozone water is performed before removing the surface layer of the first copper film using the organic acid in the third embodiment (see FIG. 4A) (FIG. 4). 4 (b)).

  In the subsequent steps, as shown in FIGS. 6C to 6E, the surface layer 73a (an oxide layer) of the first copper film 73 is formed in the same manner as the above-described FIGS. 5B to 5D, for example. In this case, the second copper film 75 is formed by the second plating method, and then the first wirings 73c and 73d are formed by CMP.

  As described above, according to the method of manufacturing a semiconductor device according to the sixth embodiment of the present invention, the first copper film 73 is formed by the first electrolytic plating method, and then the heat treatment is performed, thereby forming the step. The surface of the first copper film 73 is flattened by reduction. After that, by removing the surface layer 73a of the first copper film, the additive remaining on the surface of the first copper film 73 can be added and impurities deposited by the heat treatment can be removed. Since the additive remaining on the surface of the first copper film 73 is removed, when the second copper film 75 is formed by the second electrolytic plating method, the second copper film 75 is formed conformally, Protrusion is suppressed and the initial level difference is reduced, and the surface flatness of the second copper film 75 is further improved. Therefore, by removing the first copper film 73b and the second copper film 75 existing outside the first recess 72a and the second recess 72b by CMP, the generation of erosion or dishing is further suppressed. Can do. As a result, it is possible to further suppress variations in wiring resistance.

  In addition, according to the manufacturing method of the semiconductor device according to each of the above embodiments, although the number of steps is increased, the low polishing rate condition at a low pressure with little damage can be used, so that the productivity due to the decrease in the polishing amount can be used. Can be compensated for. In addition, in the semiconductor device manufacturing method described in the conventional example, an electrolytic etching apparatus is newly required. However, in the semiconductor device manufacturing method according to each embodiment, for example, the damascene method using copper in LSI is usually used. By combining the manufacturing apparatus, the surface step of the copper film by the electrolytic plating method can be reduced.

  In each of the above embodiments, CMP is performed after a soluble complex having solubility in copper is formed on a copper film to be polished and removed before the step using CMP. It is also possible. In this way, the polishing rate in CMP can be increased.

  In each of the above embodiments, after forming the copper film by electrolytic plating, the step of removing the surface layer is performed. Further, after forming the copper film by electrolytic plating, the insulating film existing outside the recess is formed. Although the case of performing the removal CMP has been described, the present invention is not limited to this. That is, a series of steps of removing the surface layer after electrolytic plating may be performed a plurality of times so that the flatness of the surface of the insulating film to be finally removed is further enhanced.

  As described above, the present invention is useful for a method for manufacturing a semiconductor device in which wiring is formed using copper.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 5th Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 6th Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 7th Embodiment of this invention in process order.

Explanation of symbols

11, 21, 41, 51, 61, 71 Semiconductor substrate 12, 22, 42, 52, 62, 72 Insulating film 12a, 22a, 42a, 52a, 62a, 72a First recess 12b, 22b, 42b, 52b, 62b 72b Second recess 12c, 22c, 42c, 52c, 62c, 72c Diffusion prevention film 13, 13b, 23, 23b, 43, 43b, 53, 53b, 63, 63b, 73, 73b First copper film 13a, 23a, 43a, 63a, 73a Surface layer 13c, 23c, 43c, 53c, 63c, 73c First wiring 13d, 23d, 43d, 53d, 63d, 73d Second wiring 14, 25, second copper film 24 Soluble complex 53a Surface oxide layer 64 Cleaning brush

Claims (16)

A step (a) of forming a first conductive film on an insulating film provided on the substrate and having a plurality of recesses as trenches or holes;
Removing the surface layer of the first conductive film (b);
(C) forming a second conductive film on the first conductive film after the step (b);
A step (d) of removing a portion of the first conductive film and the second conductive film existing outside the plurality of recesses after the step (c). Manufacturing method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the steps (a) and (c) are performed by an electrolytic plating method using copper.   The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive film and the second conductive film are made of the same material.   The method of manufacturing a semiconductor device according to claim 1, wherein the step (b) includes a step of removing the surface layer entirely by a CMP method.   The said process (b) includes the process of selectively removing the convex part in the said surface layer by CMP method, The manufacturing of the semiconductor device of any one of Claims 1-3 characterized by the above-mentioned. Method.   Forming an insoluble complex in a relatively low portion of the surface of the first conductive film after the step (a) and before the step (b). A method for manufacturing a semiconductor device according to claim 5.   The method of manufacturing a semiconductor device according to claim 1, wherein the step (b) is performed by wet etching.   8. The semiconductor device according to claim 7, further comprising a step of oxidizing the surface of the first conductive film after the step (a) and before the step (b). Manufacturing method.   The method of manufacturing a semiconductor device according to claim 1, wherein the step (b) is performed by brush cleaning.   The method of manufacturing a semiconductor device according to claim 9, wherein the step (b) is performed using an organic acid as an etchant.   9. A step (e) of performing a heat treatment on the first conductive film after the step (a) and before the step (b). The manufacturing method of the semiconductor device of any one of these.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the step (e) is performed in an atmosphere in which a reducing gas is added to an inert nitrogen gas.   The method of manufacturing a semiconductor device according to claim 11, wherein the step (e) is performed while introducing oxygen at least in the final stage of the heat treatment.   The method of manufacturing a semiconductor device according to claim 11, wherein the step (e) includes a step of depositing impurities contained in the first conductive film on a surface of the first conductive film.   The step (c) includes a step of forming the second conductive film by preferentially growing a film from a relatively low portion of the surface of the first conductive film. A method for manufacturing a semiconductor device according to claim 1.   The step (a) is a step of forming the first conductive film having a thickness obtained by adding at least the depth of the recess to the thickness removed in the step (b). Item 3. A method for manufacturing a semiconductor device according to Item 1 or 2.

Images