JP2007213415A - Memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory device capable of stopping operation in an optional state. <P>SOLUTION: A command decoder 11 decodes a command received from the external. A CPU 12 controls the operation of a flash memory 20 in accordance with the decoded result of the command decoder 11. Then the CPU 12 stops operation when a program count value coincides with a BREAK address stored in a mode register 16. Thereby the operation of the memory device 1 can be stopped in an optional state. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory device incorporating a CPU (Central Processing Unit), and more particularly to a memory device having a break function of a CPU.

  In recent years, various high-performance memory devices have been developed, and many are equipped with a CPU. In such a memory device, if there is a function for monitoring the internal state of the memory device, testing, evaluation, analysis and the like can be easily performed.

  In a conventional memory device, a CPU executes a program stored in a ROM (Read Only Memory) or the like, and controls the memory device by outputting a control signal to a peripheral circuit in the memory device.

  In order to monitor the internal state of the memory device, a break function for stopping the operating CPU is often installed. For example, a stop instruction (BREAK instruction) is embedded in a ROM that stores a program, and the execution of the program is stopped by the CPU executing the stop instruction. It is possible to monitor the internal state of the memory device by outputting the internal state to the outside while the operation of the CPU is stopped.

As a technique related to this, there is an invention disclosed in Patent Document 1. In the debugging support device disclosed in Patent Document 1, the module number comparator compares the module number field with the module number held in the module number register, and the address comparator holds the stop address held in the address field. The fetch address of an instruction RAM (Random Access Memory) is compared, and a break signal is output when they match.
JP 2003-223340 A

  In the conventional memory device described above, the CPU can be stopped at an arbitrary point by embedding a stop instruction in the ROM. However, it is necessary to store the stop instruction in advance at the point at which the CPU is stopped. . When the memory storing the program is ROM, the breakpoint cannot be rewritten. Therefore, it is necessary to store breakpoints at optimal positions. To change the breakpoints, it is necessary to modify the mask, which increases the development cost and the development period. There was a problem. The same problem occurs when a new test is desired.

  In the debugging support apparatus disclosed in Patent Document 1, the program can be stopped at an arbitrary address by rewriting the stop address held in the address field. However, the debugging support apparatus disclosed in Patent Document 1 is intended for debugging of a general microcomputer, and the invention disclosed in Patent Document 1 cannot be applied to testing, evaluation, analysis, etc. of a memory device. .

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a memory device capable of stopping operation in an arbitrary state.

  According to one aspect of the present invention, a memory device includes a memory, a command decoding unit that decodes a command received from the outside, a processor that controls the operation of the memory according to a decoding result by the command decoding unit, a break address The processor stops the operation when the program count value matches the break address stored in the storage means.

  According to an aspect of the present invention, the processor stops the operation when the program count value matches the break address stored in the storage unit, so that the operation of the memory device can be stopped in an arbitrary state. It becomes.

  FIG. 1 is a block diagram illustrating a configuration example of a memory device equipped with a CPU. This memory device stores a command decoder (COMDEC) 110 that analyzes an external command, a CPU 120 that performs overall control of the memory device according to an analysis result by the command decoder 110, and a program that the CPU 120 executes. ROM 21, external clock generation circuit 22, and internal clock generation circuit 23 are included.

  In addition, the CPU 120 selects and outputs either an instruction from the ROM 21 or an external CPU instruction, an instruction register (IR) 42 that holds an instruction from the combination circuit 41, a break mode control unit 43, And a selector 49 for selectively outputting clocks from the external clock generation circuit 22 and the internal clock generation circuit 23.

  When the address control signal is at a high level (hereinafter referred to as “H level”) and the command control signal is at a low level (hereinafter referred to as “L level”), the command decoder 110 receives I / O [7 at the rising edge of the write enable signal. : 0] is taken in as an address and written into an address buffer (not shown). Further, the command decoder 110 takes in the value of I / O [7: 0] as a command at the rising edge of the write enable signal when the address control signal is L level and the command control signal is H level.

  The command decoder 110 activates the CPU 120 if the fetched command is a normal command. At this time, the busy control unit 31 controls the internal state to be in a busy state so as not to accept subsequent commands. When the CPU 120 is activated, the internal clock from the internal clock generation circuit 23 is given to the IR 42. When the internal operation by the CPU 120 is completed, the busy control unit 31 controls the internal state to be ready and accepts the next command.

  When an instruction decoder (not shown) in the CPU 120 decodes the Break instruction, the Break mode control unit 43 controls the combinational circuit 41 to select the external CPU instruction and the selector 49 to select the external clock from the external clock generation circuit 22. Do.

  The external clock generation circuit 22 generates an external clock in synchronization with the write enable signal and supplies it to the CPU 120. When the CPU 120 enters the Break mode, an external CPU instruction is given to the CPU 120 in synchronization with the external clock from the external clock generation circuit 22, and the CPU 120 executes the external CPU instruction, thereby testing and evaluating the memory device. Analysis is performed.

  However, in the memory device shown in FIG. 1, since the BREAK instruction is embedded in the ROM 21, it is difficult to stop the CPU 120 at an arbitrary BREAK point.

  In addition, since the external clock generation circuit 22 and the internal clock generation circuit 23 are provided separately, a different clock switching process is required. It is relatively easy to synchronize different clocks in systems such as microcomputers where clocks are always input, but in systems where clocks are input irregularly, such as memory devices, different clocks are synchronized. It is difficult to take.

  Therefore, adding a test mode may adversely affect the normal mode function. For this reason, it is desirable to operate only with the CPU clock without using a different clock even in the test mode.

(First embodiment)
FIG. 2 is a block diagram showing a schematic configuration of the memory device according to the first embodiment of the present invention. The memory device 1 includes a command decoder 11, a CPU 12, a PAD 13, a data register 14, an address control circuit 15, a mode register 16, a status register 17, a sense / latch unit 18, a power control unit 19, and the like. And the flash memory 20.

  The command decoder 11 takes in the value of I / O [7: 0] as an address at the rising edge of the write enable signal when the address control signal input via the PAD 13 is H level and the command control signal is L level. Write to the address buffer. Further, the command decoder 11 takes in the value of I / O [7: 0] as a command at the rising edge of the write enable signal when the address control signal is L level and the command control signal is H level.

  When the command decoder 11 takes in the command, it decodes the command. If the fetched command is a CPU command during normal processing, the command decoder 11 outputs a CPU enable signal to start the CPU 12 and issue the CPU command to the CPU 12. When the CPU 12 finishes processing the CPU command received from the command decoder 11, it outputs a CPU processing end signal to the command decoder 11.

  In addition, when the command decoder 11 decodes a return command from the break mode during the break mode, the command decoder 11 outputs a break return selection signal to the CPU 12 and issues a CPU instruction code at the time of the break return to the CPU 12. The command decoder 11 determines whether or not the CPU 12 is in the Break mode based on the Break mode signal from the CPU 12.

  The data register 14 is a register that temporarily holds write data to the flash memory 20 and read data from the flash memory 20, and sets the value of I / O [7: 0] when the write enable signal is at the H level. Data is taken in, and the data held when the read enable signal is at H level is output to I / O [7: 0].

  The address control circuit 15 decodes the address held in the address buffer inside the command decoder 11 and generates a select signal for designating a register such as the row address, the column address, and the mode register 16 of the flash memory 20.

  The mode register 16 holds information such as setting of a break mode (to be described later), enabling break, changing the voltage value of the flash memory control power supply, and changing the sequence. By referring to the contents of the mode register 16, the memory device 1 changes the setting. The CPU 12 can also rewrite the contents of the mode register 16.

  The status register 17 is a register that holds the state of the flash memory 20, and outputs the state of the flash memory 20 to the outside via I / O [7: 0].

  The sense / latch unit 18 performs sense control and data latch at the time of data reading from the flash memory 20, and data latch at the time of data writing to the flash memory 20 and control of a voltage applied to the memory array.

  The power control unit 19 refers to the contents of the mode register 16 in accordance with an instruction from the CPU 12 and performs power source control of the flash memory 20 such as voltage setting and the number of times of application. Further, the power control unit 19 outputs the power control state of the flash memory 20 to the CPU 12.

  FIG. 3 is a diagram showing signals between the command decoder 11 and the CPU 12 divided by operation mode. In normal processing (normal operation mode), when the command decoder 11 decodes a command, it outputs a CPU enable signal to the CPU 12 and issues a CPU command. When the CPU 12 finishes processing the CPU command, it outputs a CPU processing end signal to the command decoder 11.

  In addition, in the Break mode, the command decoder 11 receives the Break mode signal from the CPU 12 and recognizes that the Break mode is in progress. When a return command from the break mode is decoded during the break mode, a break return selection signal is output to the CPU 12 and a CPU instruction code for returning to the break is issued to the CPU 12. When receiving a CPU instruction code from the command decoder 11, the CPU 12 executes the instruction code.

  FIG. 4 is a block diagram showing a detailed configuration of the command decoder 11 according to the first embodiment of the present invention. The command decoder 11 includes an external I / F (Interface) control unit 32, a command control unit 33, a BRAK control unit 34, and a clock generation unit 35. The Break control unit 34 includes a Break release command decoding unit 36, a state control unit 37, and a data buffer 38.

  The external I / F control unit 32 addresses the value of I / O [7: 0] at the rising edge of the write enable signal when the address control signal input via the PAD 13 is H level and the command control signal is L level. And write to an address buffer (not shown). The command decoder 11 takes in the value of I / O [7: 0] as a command at the rising edge of the write enable signal when the address control signal is at the L level and the command control signal is at the H level. The data is output to the break cancellation command decoding unit 36.

  The command control unit 33 receives and decodes the command from the external I / F control unit 32. If the command is a CPU command during normal processing, the command control unit 33 outputs a CPU enable signal to start the CPU 12, and Issued to CPU12. At this time, the command control unit 33 notifies the outside of the BUSY state by a Ready / Busy signal. In addition, when receiving a CPU processing end signal from the CPU 12, the command control unit 33 notifies the outside of the Ready state by a Ready / Busy signal.

  When receiving a command from the external I / F control unit 32 while receiving a break mode signal from the CPU 12, the break release command decoding unit 36 determines whether or not the command is a break release command. If it is a break release command, the break release command decoding unit 36 outputs a break return selection signal to the CPU 12, instructs the state control unit 37 on the return method, and writes the CPU instruction code to be subsequently input to the data buffer 38. Include.

  There are a plurality of types of break release commands. For example, when the break release command decoding unit 36 decodes the break release command “C0”, the CPU 12 is notified of this by a break return selection signal. When the CPU 12 receives a notification that the BRAK release command “C0” has been issued in response to the break return selection signal, the CPU 12 immediately releases the break mode, supplies the internal clock to the CPU 12, and fetches the instruction code from the next address of the ROM 21. Resume.

  Further, when the break release command decoding unit 36 decodes the break release command “C1”, the CPU 12 is notified of this by a break return selection signal. At this time, the state control unit 37 performs control to input a CPU instruction code via I / O [7: 0] in three cycles of the write enable signal, and stores the CPU instruction code in the data buffer 38. For example, if the CPU instruction code is 17 bits, the CPU instruction code [15: 8] is input at the first rising edge of the write enable signal, and the CPU instruction code [7: 0] is input at the second rising edge. Control is performed so that the CPU instruction code [16] is input at the second rise.

  In the case of the break release command “C1”, the break mode is not released, and after the CPU 12 executes the CPU instruction code, the break mode state is maintained. In order to cancel the Break mode, it is necessary to input the above-described Break cancellation command “C0” from the outside.

  The clock control unit 35 receives a write enable signal via the PAD 13 and generates a clock signal to be given to each block in the command decoder 11.

  FIG. 5 is a block diagram showing a detailed configuration of the CPU 12 in the first embodiment of the present invention. The CPU 12 includes an instruction control unit 41, an instruction register 42, a break mode control unit 43, a program counter 44, an incrementer 45 that increments the value of the program counter 44, a decoder 46 that decodes the CPU instruction, and an accumulator. 47 and general purpose registers 48-1 to 48-n.

  The instruction control unit 41 fetches a CPU instruction from the ROM 21 and stores it in the instruction register 42 in the normal operation mode. In addition, the instruction control unit 41 receives an external CPU instruction (BREAK return CPU instruction code) from the command decoder 11 and stores it in the instruction register 42 in the Break mode.

  The break mode control unit 43 receives the break permission signal and the break address from the mode register 16 and receives the current program count value from the program counter 44. The break mode control unit 43 compares the break address set in the mode register 16 with the program count value when break permission is set in the mode register 16, and outputs a break mode signal and sets the break mode in the break mode. The command decoder 11 and the instruction control unit 41 are notified of the occurrence of the failure and the internal clock is stopped.

  The program counter 44 increments the program count value by 1 by the incrementer 45 during normal operation, and supplies the incremented program count value to the ROM 21 as a ROM address. Further, when the branch instruction is decoded by the decoder 46, the branch destination address is set in the program counter 44.

  Further, the program counter 44 stops incrementing the program count value in the Break mode. Then, the program counter 44 resumes incrementing the program count value when returning from the Break mode.

  The decoder 46 decodes the instruction stored in the instruction register 42 and generates a control signal for each block in the CPU 12.

  The CPU 12 receives a BREAK return selection signal from the command decoder 11 and determines a return method from the BREAK mode. When the command decoder 11 decodes the break release command “C0”, the CPU 12 resumes the supply of the internal clock and starts executing the program from the instruction next to the break address.

  When the command decoder 11 decodes the BRAK return release command “C1”, the CPU 12 resumes the supply of the internal clock and takes in the external CPU instruction. After executing the external CPU instruction, the CPU 12 stops the internal clock again. Enter the Break mode. At this time, the value of the program counter 44 is held as it is. By giving the break return cancellation command “C1” from the outside, arbitrary processing can be performed while the CPU 12 is in the break state.

  As a method of using such a BREAK mode, for example, a BREAK address is set in the mode register 16 from the outside, and the CPU 12 is shifted to the BREAK mode with the address. At this time, a high voltage is applied to the memory cell, and how much voltage is applied to each power supply pump in the memory device 1 is measured, and the information is stored in the status register 17. The internal state of the memory device 1 can be monitored by reading the contents of the status register 17 from the outside. When the monitoring of the internal state is completed, execution of the instruction next to the Break address is resumed by returning to Break.

  Further, the CPU 12 is shifted to the Break mode to monitor the internal state. Then, when the CPU 12 is in the Break mode, the next Break address is set in the mode register 16. After the CPU 12 enters the normal operation mode by the break return, the CPU 12 can be stopped again at the next break address. By repeating this operation, the internal state can be continuously monitored in an arbitrary state.

  Further, the CPU 12 is shifted to the Break mode to monitor the internal state. Then, it is possible to monitor the internal state by changing the state by giving an external CPU command to the CPU 12.

  As described above, according to the memory device of the present embodiment, the CPU 12 shifts to the Break mode when the Break address set in the mode register 16 matches the address of the program counter 44. The CPU 12 can be stopped at an arbitrary address. Therefore, there is no need to embed a Break instruction in the ROM as in the prior art, and it becomes unnecessary to modify a mask for changing the Break point, thereby reducing the development cost and the development period.

  Further, by changing the BREAK address of the mode register 16 during the BREAK mode, it becomes possible to test, evaluate, and analyze the memory device step by step.

  In addition, since a single clock is supplied to the CPU 12 and the BREAK mode is realized by stopping / resuming the supply of the clock, it is possible to reduce defects associated with clock switching when using a different clock. It was.

  Since the CPU 12 fetches and executes an external CPU instruction when the CPU 12 returns from the break mode (enters the break mode again), the CPU 12 can perform arbitrary processing, and the memory device Testing, evaluation, analysis, etc. can now be performed easily.

(Second Embodiment)
FIG. 6 is a block diagram showing a schematic configuration of the memory device according to the second embodiment of the present invention. This memory device includes a command decoder 11 ′, a CPU 12 ′, a ROM 21, an external clock generation circuit 51, and an internal clock generation circuit 52. Parts having the same configuration and function as those of the memory device in the first embodiment are given the same reference numerals, and detailed description thereof will not be repeated.

  The command decoder 11 ′ includes a busy control unit 31, a command buffer 39, and a clock control unit 40.

  The command buffer 39 stores a group of instructions given to the CPU 12 'as an external CPU instruction when the CPU 12' is in the Break mode. The command buffer 39 is designated by writing an address into the address buffer under external control. Then, at the rising edge of the write enable signal, external CPU instructions are sequentially stored in the command buffer 39 via I / O [7: 0]. An external clock generation circuit 51 generates a timing signal for writing an external CPU instruction to the command buffer 39.

  The clock control unit 40 controls an internal clock given to the CPU 12 '. During the normal operation of the CPU 12 ', the clock control unit 40 controls the internal clock generation circuit 52 to supply the internal clock to the CPU 12'. Further, when the CPU 12 'is in the break mode, the clock control unit 40 controls the internal clock generation circuit 52 so as to stop the supply of the internal clock to the CPU 12'. When an external CPU instruction is given to the CPU 12 ′, the internal clock generation circuit 52 is controlled to resume the supply of the internal clock, and the external CPU instructions stored in the command buffer 39 are sequentially transmitted to the CPU 12 ′ in synchronization with the internal clock. To give.

  As described above, according to the memory device of the present embodiment, one clock is supplied to the CPU 12 ', and the BRAKE mode is realized by stopping / resuming the supply of the clock. This makes it possible to reduce defects associated with clock switching.

  Further, since the CPU 12 'can sequentially give the external CPU instructions stored in the command buffer 39 to the CPU 12' during the break mode, it becomes possible to more easily test, evaluate, and analyze the memory device. .

(Third embodiment)
The schematic configuration of the memory device according to the third embodiment of the present invention is the same as the schematic configuration of the memory device according to the first embodiment shown in FIG. The configuration of the command decoder 11 and the CPU 12 in the third embodiment of the present invention is the same as the configuration of the command decoder 11 and the CPU 12 in the first embodiment shown in FIGS. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  In the CPU 12 shown in FIG. 5, the break mode control unit 43 receives the checksum test signal set in the mode register 16. The break mode control unit 43 controls to always increment the value of the program counter by one regardless of the contents of the instruction register 42 when entering the break mode when the checksum test signal is valid. Therefore, branch instructions are ignored.

  For example, when the command decoder 11 decodes the break return cancellation command, the CPU 12 resumes the supply of the internal clock, fetches the CPU instruction from the ROM 21, and stores the CPU instruction in the status register 17. Then, the external system reads the value stored in the status register 17. At this time, the CPU 12 enters the Break mode again. The external system can calculate the checksum value by reading the value stored in the status register 17 and sequentially adding it after issuing the BRAK return release command. Also, the expected checksum value is stored in the ROM 21 in advance, and the checksum test can be easily performed by comparing the calculated checksum value with the expected value.

  As described above, according to the memory device of the present embodiment, when the CPU 12 enters the Break mode, the contents of the ROM 21 are read and stored in the status register 17 so that the external system reads the contents of the ROM 21. Since it can be used, it is possible to easily perform a checksum test.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows the structural example of the memory device carrying CPU. 1 is a block diagram showing a schematic configuration of a memory device according to a first embodiment of the present invention. It is a figure which divides and shows the signal between the command decoder 11 and CPU12 by the operation mode. It is a block diagram which shows the detailed structure of the command decoder 11 in the 1st Embodiment of this invention. It is a block diagram which shows the detailed structure of CPU12 in the 1st Embodiment of this invention. It is a block diagram which shows schematic structure of the memory device in the 2nd Embodiment of this invention.

Explanation of symbols

  1 memory device, 11, 11 ′, 110 command decoder, 12, 12 ′, 120 CPU, 13 PAD, 14 data register, 15 address control circuit, 16 mode register, 17 status register, 18 sense / latch unit, 19 power control 20, flash memory, 22, 51 external clock generation circuit, 23, 52 internal clock generation circuit, 31 busy control unit, 32 external I / F control unit, 33 command control unit, 34 BRAK control unit, 35 clock generation unit, 36 BRAK release command decode unit, 37 state control unit, 38 data buffer, 39 command buffer, 40 clock control unit, 41 instruction control unit, 42 instruction register, 43 BRAK mode control unit, 44 program counter, 45 increment Data, 46 a decoder, 47 accumulator, 48-1~48-n general purpose registers.

Claims (10)

Memory,
Command decoding means for decoding a command received from the outside;
A processor for controlling the operation of the memory in accordance with a decoding result by the command decoding means;
First storage means for storing a break address;
The processor is a memory device that stops operation when a program count value matches a break address stored in the storage means.   3. The memory device according to claim 2, wherein the first storage means receives and stores a break address from the outside. The memory device further includes second storage means for storing an instruction code received from the outside,
2. The memory device according to claim 1, wherein the command decoding unit gives the instruction code stored in the second storage unit to the processor for execution when a predetermined command is received from the outside while the processor is stopped. . The second storage means stores a plurality of instruction codes received from the outside,
4. The command decoding means, when receiving a predetermined command from the outside while the processor stops operating, sequentially gives a plurality of instruction codes stored in the second storage means to the processor for execution. Memory device.   4. The memory device according to claim 3, wherein the processor stops operation again after executing the instruction code stored in the second storage means.   The memory device further stops supply of a clock to the processor when the processor stops operation, and causes the processor to execute an instruction code stored in the second storage unit. The memory device according to claim 3, further comprising clock control means for restarting the supply of the clock. The memory device further includes program storage means for storing a program executed by the processor,
2. The memory device according to claim 1, wherein the command decoding unit causes the processor to read an instruction code from the program storage unit and output the same to the outside when a predetermined command is received from the outside while the processor is stopped.   8. The memory device according to claim 7, wherein said processor sequentially reads out instruction codes from said program storage means while incrementing a program count value and outputs them to the outside. The command decoding means gives a decoding result of a command received from the outside during normal processing to the processor to enable the processor, and notifies the processing end from the processor when processing of the command by the processor is completed. received,
The command decoding means receives a notification that a break is in progress from the processor in the break mode, and notifies the processor to return from the break mode and causes the processor to execute when the processor is returned from the break mode. The memory device of claim 1, wherein a code is provided. The memory device further includes a pad connected to the command decoding means and the first storage means,
3. The memory device according to claim 2, wherein the processor is connected to the command decoding means and the first storage means without being connected to the pad.

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