JP2007208483A - Output circuit - Google Patents

Abstract

An object of the present invention is to prevent malfunction due to power supply noise by reducing power supply noise of a tristate output circuit.
A high-impedance state, a high-level state, and a low-level state can be output. The high-level state and the low-level state are low-impedance states, and the high-impedance state and the low-impedance state according to a first control signal The tristate output circuit (101) for switching between the high impedance state and the low impedance state with respect to the delay time of the timing of the second control signal that inputs the second control signal and switches from the low impedance state to the high impedance state Output circuit having a delay circuit (102) for delaying the second control signal and outputting the first control signal to the tri-state output circuit so that the delay time of the timing of the second control signal to be switched to becomes longer Is provided.
[Selection] Figure 1

Description

  The present invention relates to an output circuit.

  With the increase in power supply noise accompanying an increase in LSI current consumption and the reduction in the voltage of LSI internal circuits, the need to reduce power supply noise is increasing. Among such noises, a technique for reducing noise caused by simultaneous switching of a plurality of I / O cells has been proposed as noise caused by switching of I / O cells (Patent Document 1).

JP 2004-334271 A

  In addition to noise due to simultaneous switching of a plurality of I / O cells, power supply noise may occur in one tri-state output circuit.

  An object of the present invention is to prevent malfunction due to power supply noise by reducing power supply noise of a tri-state output circuit.

  According to an aspect of the present invention, it is possible to output a high impedance state, a high level state, and a low level state, and the high level state and the low level state are low impedance states, and according to a first control signal A tri-state output circuit that switches between the high impedance state and the low impedance state, and a second control signal, and a delay time of the timing of the second control signal that switches from the low impedance state to the high impedance state And delaying the second control signal so that the delay time of the timing of the second control signal for switching from the high impedance state to the low impedance state becomes longer. A delay circuit for outputting to the output circuit Output circuit that is provided.

  By generating the first control signal obtained by delaying the second control signal, the timing of switching from the high impedance state to the low impedance state can be delayed. Thereby, the time range in which the transition between the high level state and the low level state can be made can be expanded, and noise can be prevented. In addition, malfunction due to noise can be prevented.

  FIG. 15 is a diagram showing the tristate output circuit 101, and FIG. 16 is a timing chart for explaining the operation thereof. The input signal IN and the control signal CTL are shown in FIGS. 16 and 17 with the voltages slightly shifted in order to make the level transition easy to understand. Actually, the input signal IN and the control signal CTL have a low level of 0V and a high level of 1.3V. The power supply voltage VDD is 3.3V, and the reference voltage VSS is 0V.

  The tri-state output circuit 101 is connected between the power supply voltage VDD and the reference voltage VSS, receives the control signal CTL and the input signal IN, and outputs the output signal OUT. When the control signal CTL is at a low level, the output signal OUT is also at a high level if the input signal IN is at a high level, and the output signal OUT is also at a low level if the input signal IN is at a low level. When the control signal CTL is at a high level, the output of the tri-state output circuit 101 is in a high impedance state, and the output signal OUT maintains the previous state. The tri-state output circuit 101 can output three states: a high impedance state, a high level state, and a low level state. In the high level state and the low level state, the output is a low impedance state.

  The period T21 is a period from the falling edge of the input signal IN to the rising edge of the control signal CTL. Since the period T21 is sufficiently long, almost no noise is generated in the power supply voltage VDD and the reference voltage VSS. As a result, no noise occurs in the output signal OUT.

  FIG. 17 is a timing chart showing a case where power supply noise occurs in the tristate output circuit 101, and corresponds to FIG. The period T22 is a period from the falling edge of the input signal IN to the rising edge of the control signal CTL. Since the period T22 is too short, noise occurs in the power supply voltage VDD and the reference voltage VSS. As a result, noise also occurs in the output signal OUT. Specifically, a large current flows in the tristate output circuit 101 as the input signal IN changes from a high level to a low level. In the meantime, the control signal CTL changes from the low level to the high level, whereby the transistors in the tristate output circuit 101 perform the switching operation. This causes power supply noise.

  FIG. 18 is a diagram illustrating a level transition of the control signal CTL and a range ST in which the level transition of the input signal IN can be accompanied. The upper part of the figure shows a case where the control signal CTL changes from a low level (low impedance state) to a high level (high impedance state), and the lower part of the figure shows that the control signal CTL changes from a high level (high impedance state) to a low level (low impedance state). (Impedance state).

  First, the case where the control signal CTL changes from the low level to the high level in the upper part of the drawing will be described. The case where the input signal IN makes a level transition before the time t11 is the case of FIG. When the level of the input signal IN changes, a current flows in the tristate output circuit 101, and the level of the output signal OUT changes. When the level transition of the output signal OUT is completed, the current in the tristate output circuit 101 does not flow. Thereafter, since the control signal CTL changes from the low level to the high level, no power supply noise occurs.

  The case where the level of the input signal IN transitions between time t11 and time t12 is the case of FIG. When the input signal IN makes a level transition, a large current flows in the tristate output circuit 101. Since the control signal CTL changes from the low level to the high level while a large current is flowing, power supply noise is generated by the switching operation in the tristate output circuit 101.

  Next, a case where the input signal IN undergoes level transition after time t12 will be described. When the level of the input signal IN transitions, current starts to flow in the tristate output circuit 101. However, since the current is still small immediately after the start of switching, even if the control signal CTL changes from the low level to the high level at this time, almost no power supply noise occurs.

  Further, when the control signal CTL changes from the low level to the high level, the output of the tristate output circuit 101 enters a high impedance state. Thereafter, even if the input signal IN makes a level transition, no power supply noise occurs.

  Next, the case where the control signal CTL changes from the high level to the low level will be described in the lower part of the figure. A case where the input signal IN undergoes level transition before time t13 will be described. When the control signal CTL is at a high level, the output of the tristate output circuit 101 is in a high impedance state. In this state, even if the input signal IN makes a level transition, no power supply noise occurs.

  Further, when the control signal CTL changes from the high level to the low level, the transistor in the tristate output circuit 101 performs the switching operation, and the switching current starts to flow. However, since the current is still small immediately after the start of switching, power supply noise hardly occurs even if the input signal IN makes a level transition at this point.

  Next, a case where the level of the input signal IN changes between time t13 and time t14 will be described. When the control signal CTL changes from the high level to the low level, the above switching current flows. The switching current will eventually become a large current. When the input signal IN makes a level transition while a large current is flowing, power supply noise occurs.

  Next, a case where the input signal IN undergoes level transition after time t14 will be described. When the control signal CTL changes from the high level to the low level, the above switching current flows. The switching current hardly flows when the level of the output signal OUT settles. Even if the input signal IN subsequently changes in level, no power supply noise occurs.

  The period from time t11 to t12 is several ns. The period T12 from time t12 to time t13 is several tens to several tens of ps. The period from time t13 to t14 is several ns. Periods T11, T12, and T13 are periods in which the ranges in which power supply noise does not occur overlap in the upper and lower stages of the figure.

  As described above, the case where the control signal CTL transits from the low level to the high level is shown in the upper part of the figure. When the input signal IN changes when the control signal CTL is at a low level (low impedance state), the output signal OUT of the tristate output circuit 101 is switched. If the control signal CTL transits from low level to high level during this switching, the current flowing between the power supplies in the transistor driving the output is suddenly cut. Noise that is larger than the time is applied to the power supply.

  The case where the control signal CTL transits from the high level to the low level is shown in the lower part of the figure. When the input signal IN is inverted while the tri-state output circuit 101 is switching because the control signal CTL changes from the high level to the low level, the power supply and the tri-state output circuit 101 Due to the sudden change in current between the two, noise larger than that during normal switching is applied to the power supply.

  In this way, when simultaneous switching is performed using the input signal IN and the control signal CTL, a larger noise is applied to the power supply than during normal switching. Therefore, if the circuit design is performed considering only noise due to normal switching, the internal circuit malfunctions. there is a possibility. This problem can be avoided if the logic design can cope with the input signal IN so that the input signal IN does not change in the clock cycle in which the control signal CTL switches, but this solution is not always applicable when the timing requirement of the control signal CTL is severe.

  In order to avoid this problem by adjusting the delay between the input signal IN and the control signal CTL, the switching timing by the input signal IN and the control signal CTL needs to satisfy the following requirements.

  First, the requirements when the control signal CTL in the upper part of the figure transitions from a low level to a high level will be described. The control signal CTL changes before the switching current of the tri-state output circuit 101 increases to some extent due to the change of the input signal IN or after the switching current becomes sufficiently small.

  Next, requirements when the control signal CTL transitions from a high level to a low level will be described. The input signal IN changes before the switching current of the tri-state output circuit 101 becomes large to some extent due to the change of the control signal CTL or after the switching current becomes sufficiently small.

  As can be seen from FIG. 18, since the requirements of the transition order of the input signal IN and the control signal CTL are reversed at the rise and fall of the control signal CTL, the control signal CTL and the input are required to suppress power supply noise. The transition timing of the signal IN must be separated enough or vice versa. There are the following three measures.

  First, the transition timing between the control signal CTL and the input signal IN is sufficiently separated. However, in this case, there is a problem that the delay performance is greatly deteriorated.

  Secondly, the power supply is strengthened as a noise countermeasure. However, in this case, there is a problem that the semiconductor chip size increases and the cost increases.

  Third, the transition timing between the control signal CTL and the input signal IN is very close. However, in this case, since adjustment is required for a large number of tristate output circuits (input / output circuits) 101, there is a problem that the number of design steps increases. Further, depending on the characteristics of the tri-state output circuit 101, there are cases where this countermeasure cannot be implemented because the timing window for this adjustment is hardly open.

  FIG. 1 is a diagram showing an output circuit according to an embodiment of the present invention, and FIG. 3 is a timing chart showing control signals CTL and CTL1. The output circuit is a semiconductor integrated circuit having a tristate output circuit 101 and a delay circuit 102.

  At time t1, the control signals CTL and CTL1 transition from the low level to the high level. At time t2, the control signal CTL changes from the high level to the low level. At time t3, the control signal CTL1 changes from the high level to the low level. The period from time t2 to t3 is a delay time T. When the control signal CTL rises, the delay circuit 102 outputs the control signal CTL1 with almost no delay time, and when the control signal CTL falls, the delay circuit 102 outputs the control signal CTL1 with a predetermined delay time T.

  That is, the delay circuit 102 receives the control signal CTL, and the timing of the control signal CTL for switching from the high level to the low level with respect to the delay time (for example, 0) of the timing of the control signal CTL for switching from the low level to the high level. The control signal CTL is delayed and the control signal CTL1 is output to the tristate output circuit 101 so that the delay time T becomes longer. The delay circuit 102 can generate a control signal CTL1 having hysteresis characteristics with respect to the control signal CTL.

  Similarly to FIG. 16, the tristate output circuit 101 is connected between the power supply voltage VDD and the reference voltage VSS, receives the control signal CTL1 and the input signal IN, and outputs the output signal OUT. When the control signal CTL1 is at a low level, the output signal OUT is also at a high level if the input signal IN is at a high level, and the output signal OUT is also at a low level if the input signal IN is at a low level. When the control signal CTL1 is at a high level, the output of the tri-state output circuit 101 is in a high impedance state, and the output signal OUT maintains the previous state. The tri-state output circuit 101 can output three states: a high impedance state, a high level state, and a low level state. In the high level state and the low level state, the output is a low impedance state. The output of the tri-state output circuit 101 is in a high impedance state when the control signal CTL1 is at a high level, and is in a low impedance state when the control signal CTL1 is at a low level.

  FIG. 2 is a circuit diagram illustrating a configuration example of the tri-state output circuit 101. A negation (NOT) circuit 201 logically inverts the input signal IN and outputs it. The negation circuit 202 logically inverts and outputs the control signal CTL1. Hereinafter, the MOS field effect transistor is simply referred to as a transistor. The p-channel transistor 203 has a gate connected to the output terminal of the negative circuit 201, a source connected to the power supply voltage VDD, and a drain connected to the source of the p-channel transistor 204. The p-channel transistor 204 has a gate connected to the control signal CTL1 line and a drain connected to the output signal OUT line. The n-channel transistor 205 has a gate connected to the output terminal of the negative circuit 202, a drain connected to the line of the output signal OUT, and a source connected to the drain of the n-channel transistor 206. The n-channel transistor 206 has a gate connected to the output terminal of the negation circuit 201 and a source connected to the reference voltage VSS.

  When the control signal CTL1 becomes high level, the transistors 204 and 205 are turned off. As a result, the line of the output signal OUT enters a high impedance state. When the control signal CTL1 becomes low level, the transistors 204 and 205 are turned on. As a result, the line of the output signal OUT is in a low impedance state.

  When the control signal CTL1 is at a low level and the input signal IN is at a high level, the transistors 203 to 205 are turned on and the transistor 206 is turned off. As a result, the output signal OUT becomes a high level (power supply voltage VDD).

  When the control signal CTL1 is at a low level and the input signal IN is at a low level, the transistors 204 to 206 are turned on and the transistor 203 is turned off. As a result, the output signal OUT becomes low level (reference voltage VSS).

  FIG. 4 is a circuit diagram illustrating a configuration example of the delay circuit 102. The p-channel transistor 401 has a gate connected to the control signal CTL line, a source connected to the power supply voltage VDD, and a drain connected to the drain of the n-channel transistor 402. The n-channel transistor 402 has a gate connected to the control signal CTL line and a source connected to the reference voltage VSS. The p-channel transistor 403 has a gate connected to the interconnection point of the drains of the transistors 401 and 402, a source connected to the power supply voltage VDD, and a drain connected to the line of the control signal CTL1. The n-channel transistor 404 has a gate connected to the interconnection point of the drains of the transistors 401 and 402, a drain connected to the line of the control signal CTL1, and a source connected to the reference voltage VSS.

  The transistor 403 has a higher driving capability than the transistor 404. Specifically, the transistor 403 is larger in size (gate width) than the transistor 404. Since a large current flows through the transistor 403, the transistor 403 can set the control signal CTL1 to the high level at high speed. On the other hand, since a small current flows through the transistor 404, the transistor 404 sets the control signal CTL1 to a low level at a low speed. As a result, as shown in FIG. 3, the control signal CTL1 has a shorter rise delay time and a longer fall delay time than the control signal CTL.

  The same result can be obtained even when the driving capability of the transistor 402 is made larger than that of the transistor 401. That is, the drive capability of the transistors 402 and / or 403 for setting the control signal CTL1 to the high level may be increased, and the drive capability of the transistors 401 and / or 404 for setting the control signal CTL1 to the low level may be decreased. In addition, although the example in which the delay circuit 102 is configured by two-stage inverters has been described, the number of inverter stages may be any number. In the case of two stages, the first stage inverter is composed of transistors 401 and 402, and the second stage inverter is composed of transistors 403 and 404.

  FIG. 5 is a circuit diagram showing another configuration example of the delay circuit 102, and FIG. 6 is a timing chart for explaining its operation. The delay circuit 102 includes a logic circuit and a delay element. The negation circuit 501 logically inverts the control signal CTL and outputs a signal S511. The delay element (buffer) 502 delays the output signal S511 of the negation circuit 501 by a delay time T and outputs a signal S512. A negative logical product (NAND) circuit 503 outputs a negative logical product of the signals S511 and S512 as the control signal CTL1.

  FIG. 7 is a circuit diagram showing another configuration example of the delay circuit 102, and FIG. 8 is a timing chart for explaining the operation thereof. The delay circuit 102 includes a logic circuit and a delay element. The delay element 701 delays the control signal CTL by a delay time T and outputs a signal S711. A logical sum (OR) circuit 702 outputs a logical sum of the signal S711 and the control signal CTL as the control signal CTL1.

  The case where the output of the tristate output circuit 101 is in the high impedance state when the control signal CTL1 is at the high level and the low impedance state when the control signal CTL1 is at the low level has been described above. Conversely, the output of the tristate output circuit 101 may be in a low impedance state when the control signal CTL1 is at a high level, and may be in a high impedance state when the control signal CTL1 is at a low level. The operation of the delay circuit 102 in that case is shown in FIG.

  FIG. 9 is a timing chart for explaining the operation of the delay circuit 102. At time t1, the control signal CTL changes from low level to high level. At time t2, the control signal CTL1 changes from the low level to the high level. At time t3, the control signals CTL and CTL1 transition from the high level to the low level. A period from time t1 to t2 is a delay time T. When the control signal CTL rises, the delay circuit 102 outputs the control signal CTL1 with a delay of a predetermined delay time T. When the control signal CTL falls, the delay circuit 102 outputs the control signal CTL1 with almost no delay time.

  Also in this case, the delay circuit 102 can be configured by the circuit of FIG. On the contrary, the driving capability of the transistors 402 and / or 403 for setting the control signal CTL1 to the high level is reduced, and the driving capability of the transistors 401 and / or 404 for setting the control signal CTL1 to the low level is increased. That's fine.

  FIG. 10 is a circuit diagram showing a configuration example of the delay circuit 102 that generates the control signal CTL1 of FIG. 9, and FIG. 11 is a timing chart for explaining its operation. The delay circuit 102 includes a logic circuit and a delay element. The negation circuit 1001 logically inverts the control signal CTL and outputs a signal S1011. The delay element 1002 delays the output signal S1011 of the negation circuit 1001 by a delay time T and outputs a signal S1012. A negative logical sum (NOR) circuit 1003 outputs a negative logical sum of the signals S1011 and S1012 as a control signal CTL1.

  FIG. 12 is a circuit diagram showing another configuration example of the delay circuit 102 that generates the control signal CTL1 of FIG. 9, and FIG. 13 is a timing chart for explaining the operation thereof. The delay circuit 102 includes a logic circuit and a delay element. The delay element 1201 delays the control signal CTL by a delay time T and outputs a signal S1211. A logical product (AND) circuit 1202 outputs a logical product of the signal S1211 and the control signal CTL as the control signal CTL1.

  As described above, the delay circuit 102 receives the control signal CTL, and has a high impedance with respect to the delay time (for example, 0) of the timing of the control signal CTL that switches the tristate output circuit 101 from the low impedance state to the high impedance state. The control signal CTL is delayed and the control signal CTL1 is output to the tristate output circuit 101 so that the delay time T of the timing of the control signal CTL for switching from the state to the low impedance state becomes longer.

  FIG. 14 corresponds to FIG. 18 and is a diagram showing a level transition of the control signal CTL1 according to the present embodiment and a range ST in which the level of the input signal IN can be transitioned accordingly. The upper part of the figure shows the case where the control signal CTL1 changes from the low level (low impedance state) to the high level (high impedance state), and the lower part of the figure shows that the control signal CTL1 changes from the high level (high impedance state) to the low level (low impedance state). (Impedance state).

  As shown in the upper part of the figure, when the control signal CTL changes from a low level (low impedance state) to a high level (high impedance state), the control signal CTL1 is generated with almost no delay.

  On the other hand, as shown in the lower part of the figure, when the control signal CTL changes from a high level (high impedance state) to a low level (low impedance state), the control signal CTL1 is generated with a predetermined delay time T. . Thereby, in FIG. 14, the period T12 from the time t12 to t13 can be lengthened compared with FIG. The period T12 is a period in which the noise is low and the level of the input signal IN can be changed. By extending the period T12, the delay adjustment timing window is narrow and the power supply noise can be removed, so that it is possible to remove the noise. The delay adjustment for becomes very easy.

  As an example, in the timing diagram of FIG. 18, when the level transition time of the control signal CTL is 0, time t11 is −3 ns, time t12 is −30 ps, time t13 is +30 ps, and time t14 is +3 ns. That is, consider the tri-state output circuit 101 in which the signal change timing of the control signal CTL and the input signal IN must be close to within ± 30 ps or separated by ± 3 ns or more in order to suppress power supply noise.

  In this circuit, when delay adjustment between the input signal IN and the control signal CLT is performed to suppress power supply noise, the delay adjustment window T12 for the input signal IN is only 60 ps. If it cannot enter this region T12, it must enter the region T11 or T13 separated by 3 ns or more. This delay adjustment window T12 is narrow in consideration of a large number of tristate output circuits (I / O cells) 101 to be adjusted, such as a multi-bit bidirectional I / O bus, and delay variations. And delay adjustment is very difficult. In this state, power supply noise increases and delay adjustment on the scale of 3 ns is performed, leading to malfunctions and delay deterioration.

  Next, consider the case where the delay circuit 102 is inserted as shown in FIG. The delay circuit 102 assumes that the delay time when the control signal CTL transitions from the high impedance state to the low impedance state is 270 ps, and the delay time when the control signal CTL transitions from the low impedance state to the high impedance state is 30 ps. CTL1 is generated.

  In this case, in FIG. 14, time t11 is −2.97 ns, time t12 is 0, time t13 is 300 ps, and time t14 is +3.27 ns. A period T12 from time t12 to t13 is 300 ps. The delay adjustable range T12 at the time of simultaneous switching of the control signal CTL1 and the input signal IN extends from 60 ps to 300 ps as compared with the case of FIG. Thereby, if the delay adjustment of the input signal IN is performed and the input signal IN is adjusted so as to be close to the center of the window T12, it becomes easy to suppress the power supply noise even in the case of considering the multi-bit adjustment and the delay variation.

  According to this embodiment, delay degradation due to power supply noise of the tri-state output circuit 101 and deterioration of delay performance due to significant delay adjustment (separate the transition timing between the input signal IN and the control signal CTL) to avoid power supply noise are prevented. Delay performance can be improved. Further, it is possible to reduce power supply noise caused by simultaneous switching by the input signal IN and the control signal CTL of the tri-state output circuit 101.

  By generating the control signal CTL1 obtained by delaying the control signal CTL, the timing for switching from the high impedance state to the low impedance state can be delayed. Thereby, the time range in which the transition between the high level state and the low level state can be made can be expanded, and noise can be prevented. In addition, malfunction due to noise can be prevented. This embodiment can be applied to a semiconductor integrated circuit, and can reduce power supply noise of an input / output circuit.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

  The embodiment of the present invention can be applied in various ways as follows, for example.

(Appendix 1)
A high impedance state, a high level state, and a low level state can be output, and the high level state and the low level state are low impedance states, and the high impedance state and the low impedance state according to a first control signal A tri-state output circuit for switching between,
The second control signal is inputted and the second control signal is switched from the high impedance state to the low impedance state with respect to a delay time of the timing of the second control signal to switch from the low impedance state to the high impedance state. An output circuit comprising: a delay circuit that delays the second control signal and outputs the first control signal to the tri-state output circuit so that a delay time of the timing of the control signal is increased. .
(Appendix 2)
The tri-state output circuit receives an input signal and outputs the high level state or the low level state according to the input signal when the low impedance state is instructed by the first control signal. The output circuit according to supplementary note 1, which is characterized.
(Appendix 3)
The delay circuit includes a first transistor that generates the first control signal for setting the tristate output circuit to the high impedance state, and the first transistor for setting the tristate output circuit to the low impedance state. A second transistor for generating one control signal,
The output circuit according to claim 1, wherein the first transistor has a driving capability larger than that of the second transistor.
(Appendix 4)
The output circuit according to claim 3, wherein the first transistor is larger in size than the second transistor.
(Appendix 5)
The output circuit according to claim 1, wherein the delay circuit includes a logic circuit and a delay element.
(Appendix 6)
The tristate output circuit outputs the high impedance state when the first control signal is at a high level, and outputs the low impedance state when the first control signal is at a low level. The output circuit according to 1.
(Appendix 7)
The delay circuit includes a first transistor for setting the first control signal to a high level, and a second transistor for setting the first control signal to a low level,
The output circuit according to appendix 6, wherein the first transistor has a driving capability larger than that of the second transistor.
(Appendix 8)
The output circuit according to appendix 7, wherein the first transistor is larger in size than the second transistor.
(Appendix 9)
The output circuit according to appendix 6, wherein the delay circuit includes a logic circuit and a delay element.
(Appendix 10)
The delay circuit includes a negative circuit for logically inverting the second control signal, a delay element for delaying an output signal of the negative circuit, and a negative logical product of the negative circuit and the output signal of the delay element The output circuit according to claim 9, further comprising a NAND circuit for outputting
(Appendix 11)
The delay circuit includes a delay element for delaying the second control signal, and an OR circuit for outputting a logical sum of the output signal of the delay element and the second control signal. The output circuit according to appendix 9.
(Appendix 12)
The tri-state output circuit outputs the high impedance state when the first control signal is at a low level, and outputs the low impedance state when the first control signal is at a high level. The output circuit according to 1.
(Appendix 13)
The delay circuit includes a first transistor for setting the first control signal to a high level, and a second transistor for setting the first control signal to a low level,
The output circuit according to appendix 12, wherein the second transistor has a driving capability larger than that of the first transistor.
(Appendix 14)
14. The output circuit according to appendix 13, wherein the second transistor is larger in size than the first transistor.
(Appendix 15)
13. The output circuit according to appendix 12, wherein the delay circuit includes a logic circuit and a delay element.
(Appendix 16)
The delay circuit includes a negative circuit for logically inverting the second control signal, a delay element for delaying an output signal of the negative circuit, and a negative logical sum of the negative circuit and output signals of the delay element The output circuit according to claim 15, further comprising: a negative OR circuit for outputting
(Appendix 17)
The delay circuit includes a delay element for delaying the second control signal, and an AND circuit for outputting a logical product of the output signal of the delay element and the second control signal. The output circuit according to appendix 15.

It is a figure which shows the output circuit by embodiment of this invention. It is a circuit diagram which shows the structural example of a tri-state output circuit. 2 is a timing chart showing control signals of the circuit of FIG. It is a circuit diagram which shows the structural example of a delay circuit. It is a circuit diagram which shows the other structural example of a delay circuit. 6 is a timing chart for explaining the operation of the circuit of FIG. 5. It is a circuit diagram which shows the other structural example of a delay circuit. FIG. 8 is a timing chart for explaining the operation of the circuit of FIG. 7. FIG. 6 is a timing chart for explaining the operation of the delay circuit. It is a circuit diagram which shows the other structural example of a delay circuit. It is a timing chart for demonstrating operation | movement of the circuit of FIG. It is a circuit diagram which shows the other structural example of a delay circuit. 13 is a timing chart for explaining the operation of the circuit of FIG. 12. It is a figure which shows the level transition of the level of the control signal by this embodiment, and the level transition range of the input signal accompanying it. It is a figure which shows a tristate output circuit. 16 is a timing chart for explaining the operation of the circuit of FIG. 6 is a timing chart illustrating a case where power supply noise occurs in the tri-state output circuit. It is a figure which shows the level transition of the level transition of a control signal, and the level transition of an input signal accompanying it.

Explanation of symbols

101 Tri-state output circuit 102 Delay circuit CTL, CTL1 Control signal IN Input signal OUT Output signal

Claims (10)

A high impedance state, a high level state, and a low level state can be output, and the high level state and the low level state are low impedance states, and the high impedance state and the low impedance state according to a first control signal A tri-state output circuit for switching between,
The second control signal is inputted and the second control signal is switched from the high impedance state to the low impedance state with respect to a delay time of the timing of the second control signal to switch from the low impedance state to the high impedance state. An output circuit comprising: a delay circuit that delays the second control signal and outputs the first control signal to the tri-state output circuit so that a delay time of the timing of the control signal is increased. .   The tri-state output circuit receives an input signal and outputs the high level state or the low level state according to the input signal when the low impedance state is instructed by the first control signal. The output circuit according to claim 1. The delay circuit includes a first transistor that generates the first control signal for setting the tristate output circuit to the high impedance state, and the first transistor for setting the tristate output circuit to the low impedance state. A second transistor for generating one control signal,
The output circuit according to claim 1, wherein the first transistor has a driving capability larger than that of the second transistor.   The output circuit according to claim 1, wherein the delay circuit includes a logic circuit and a delay element.   The tri-state output circuit outputs the high impedance state when the first control signal is at a high level, and outputs the low impedance state when the first control signal is at a low level. The output circuit according to Item 1. The delay circuit includes a first transistor for setting the first control signal to a high level, and a second transistor for setting the first control signal to a low level,
The output circuit according to claim 5, wherein the first transistor has a driving capability larger than that of the second transistor.   6. The output circuit according to claim 5, wherein the delay circuit includes a logic circuit and a delay element.   The tri-state output circuit outputs the high impedance state when the first control signal is at a low level, and outputs the low impedance state when the first control signal is at a high level. The output circuit according to Item 1. The delay circuit includes a first transistor for setting the first control signal to a high level, and a second transistor for setting the first control signal to a low level,
9. The output circuit according to claim 8, wherein the second transistor has a driving capability larger than that of the first transistor.   9. The output circuit according to claim 8, wherein the delay circuit includes a logic circuit and a delay element.

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