JP2007206972A - Reference voltage generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit for operating on a voltage power supply and supplying a stable reference voltage with low output impedance. <P>SOLUTION: The reference voltage generating circuit 30 has its source connected to the gate of a depression type transistor M3. While the transistor M3 and the source of an enhancement type transistor M4 are grounded, the gate voltage of the transistor M4 is used as a reference voltage VrefH that is an output voltage. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit that can operate at a low voltage and has excellent temperature characteristics.

  Japanese Unexamined Patent Application Publication No. 2001-284464 (Patent Document 1) is a prior art document of a circuit that generates a reference voltage with good temperature characteristics using a MOS transistor. Here, an invention is disclosed in which MOS transistors having different threshold voltages are manufactured using the work function difference of the gate electrode, and the difference between the threshold voltages is taken as a reference voltage.

  Specifically, a VPTAT voltage source having a positive temperature coefficient by a pair MOS transistor having a semiconductor gate having the same conductivity type and a different impurity concentration, and a different conductivity between the pair MOS transistors with the same substrate and channel dope concentration. A desired reference voltage Vref = VPN + VPTAT is generated by combining a VPN voltage source having a negative temperature coefficient with a pair MOS transistor having a semiconductor gate of a type.

  FIG. 1 shows the reference voltage generating circuit disclosed in FIG. Transistors M31, M32, M33, and M34 in FIG. 1 are NMOS transistors, and are formed in the p-well of an n-type substrate having the same substrate concentration and channel dope impurity concentration, and the substrate potential between the transistors is the source potential. It is equal to. Further, the channel width and channel length of each transistor are also equal.

  The transistor M31 is a depletion type transistor having a high concentration n-type gate, and a gate and a source are connected to form a constant current source. The transistor 12 has a low-concentration n-type gate, and is given a gate potential by a source ground circuit 15 including a transistor M34 and a resistor R31. The transistor M33 is an enhancement type transistor having a p-type gate, the gate and drain are connected, and the source is grounded.

  Since the same current flows through the transistor M31 and the transistor M33, which are paired MOS transistors, the gate-source voltage V2 of the transistor M33 is a voltage source VPN having a negative temperature coefficient.

  Similarly, since the same current flows through the pair MOS transistors M31 and M32, the gate-source voltage Vgs of the transistor M32 is a voltage source VPTAT having a positive temperature coefficient.

  Since the output voltage V3 is the sum of the gate-source voltage V2 of the transistor M33 and the gate-source voltage Vgs of the transistor M32, V3 = VPN + VPTAT. At this time, the temperature characteristics of each transistor can be arbitrarily set by changing the impurity concentration of the high-concentration n-type gate, the low-concentration n-type gate, and the p-type gate.

  FIG. 2 shows another reference voltage generation circuit disclosed in FIG. 22 of the publication. Transistors M21, M22, M23, and M24 in FIG. 2 are NMOS transistors having the same substrate and channel-doped impurity concentration, formed in a p-well of an n-type substrate, and the substrate potential between the transistors being the source potential. Are equal. Further, the ratio of the channel width to the channel length is equal in the transistors M21 and M22, and the ratio of the channel width to the channel length is equal in the transistors M23 and M24.

  The transistor M21 is a depletion type transistor having a high-concentration n-type gate, and the gate and the source are connected to form a constant current source. The transistor M22 has a high-concentration p-type gate, and is given a gate potential by a source ground circuit 25 configured by an NMOS transistor M25, a resistor R21, and a resistor R22.

  The transistor M23 is a depletion type transistor having a high concentration n-type gate, and the transistor M24 is a depletion type transistor having a low concentration n-type gate. The gate and source of the transistor M24 are connected to form a constant current source.

  Since the same current flows through the transistor M21 and the transistor M22 which are pair MOS transistors, the gate-source voltage V1 of the transistor M22 becomes a voltage source VPN having a negative temperature characteristic.

  Further, since the same current flows through the pair MOS transistors M23 and M24, the gate-source voltage Vgs of the transistor M23 becomes a voltage source VPTAT having a positive temperature coefficient.

The output voltage V3 is the sum of the voltage V1 obtained by dividing the gate-source voltage V1 of the transistor M22 by the resistors R21 and R22 and the gate-source voltage Vgs of the transistor M23, so that the output voltage V3 = VPN × R22 / (R21 + R22) + VPTAT. At this time, the temperature characteristics of each transistor can be arbitrarily set by changing the impurity concentration of the high-concentration n-type gate, the low-concentration n-type gate, and the high-concentration p-type gate.
JP 2001-284464 A

  However, the conventional example shown in FIG. 1 requires a voltage obtained by adding the gate-source voltage of the transistor M14 and the source-drain voltage of the transistor M11 to the output voltage V3 as the power supply voltage. There is a problem that it must be raised.

  Further, in the conventional example shown in FIG. 2, since the output voltage V3 itself is a low voltage, the power supply voltage can also be a low voltage. However, the power supply voltage requires a voltage obtained by adding the gate-source voltage of the transistor M23, the source-drain voltage of the transistor M25, and the voltage drop across the resistor R21 to the output voltage V3.

  In the example shown in FIG. 2, since the output impedance of the output voltage V3 is high, the output voltage V3 cannot be divided by a resistor to obtain an arbitrary voltage.

  The present invention has been made in view of these points, and has been made to solve these problems. The reference voltage generating circuit is operable with a low-voltage power supply, has a low output impedance, and can supply a stable reference voltage. The purpose is to provide.

  In order to achieve the above object, the reference voltage generating circuit of the present invention employs the following configuration.

  The reference voltage generation circuit of the present invention is a current mirror circuit composed of two MOS transistors having the same characteristics, and a first transistor connected to the output side of one of the two MOS transistors. A depletion type transistor, a pair MOS transistor composed of an enhancement type transistor which is a second transistor connected to the output side of the other of the two MOS transistors, and the first transistor or the second transistor A third transistor connected to the output side of the third transistor and a load of the third transistor connected to the output side of the third transistor, and the connection of the third transistor and the load The voltage output from the point is the second transistor The gate voltage of the first transistor and the gate voltage of the second transistor when the drain current of the first transistor and the drain current of the second transistor are the same when applied to the gate In a reference voltage generation circuit for outputting a difference as an output voltage, the gate and source of the first transistor are connected, the sources of the first transistor and the second transistor are grounded, and the gate voltage of the second transistor is It can be set as the structure made into an output voltage.

  As a result, the reference voltage generating circuit of the present invention has a small difference between the input voltage and the output voltage, and can operate with a low power supply voltage. Furthermore, the output impedance is lowered.

  In order to achieve the above object, the reference voltage generating circuit of the present invention is further configured such that each channel is formed of the same conductivity type in each of the first transistor and the second transistor, and each gate is It is possible to adopt a configuration in which the gate sizes of the respective gates are different, which are formed of different conductivity type impurities.

  As a result, in the reference voltage generating circuit of the present invention, variations in output voltage due to variations in the manufacturing process of each transistor are reduced.

  In order to achieve the above object, the reference voltage generation circuit according to the present invention further sets the ratio Sd between the channel width Wd and the channel length Ld of the first transistor to Sd = Wd / Ld, and the second transistor When the ratio Se between the channel width We and the channel length Le is Se = We / Le, and the ratio between Se and Sd is Se / Sd, the Se / Sd is 0.3 to 0.67. It can be.

  As a result, the temperature characteristics of each transistor are reduced, and a stable output voltage is output.

  Furthermore, in the reference voltage generating circuit of the present invention, in order to achieve the above object, the MOS transistor constituting the current mirror circuit can be a low threshold voltage transistor.

  As a result, the reference voltage generation circuit of the present invention can operate with a low power supply voltage.

  Further, in order to achieve the above object, the reference voltage generating circuit of the present invention is further configured such that the current mirror circuit is constituted by a circuit in which two sets of two MOS transistors having different threshold voltages are connected in series. In the above circuit, the MOS transistor having the higher threshold voltage may be arranged on the power supply voltage side.

  This improves the accuracy of the current mirror circuit and improves the mirror current accuracy.

  In order to achieve the above object, the reference voltage generation circuit of the present invention further includes a circuit that makes the drain voltage of the first transistor and the drain voltage of the second transistor substantially the same potential. It can be.

  Thereby, the influence of the channel length modulation effect in the first transistor M1 which is the depletion type transistor and the second transistor M2 which is the enhancement type transistor is reduced.

  In order to achieve the above object, the reference voltage generation circuit according to the present invention further includes a circuit that sets the drain voltage of the first transistor and the drain voltage of the second transistor to substantially the same potential. A fourth transistor disposed between the drain of one transistor and the output side of one of the MOS transistors constituting the current mirror circuit; the other comprising the drain of the second transistor and the current mirror circuit; A fifth transistor disposed between the output side of the MOS transistor and the gates of the fourth transistor and the fifth transistor are connected in common. A voltage at a connection point between the third transistor and the load or a voltage proportional to the voltage can be applied.

  Thereby, the influence of the channel length modulation effect in the first transistor M1 which is the depletion type transistor and the second transistor M2 which is the enhancement type transistor is reduced.

  In order to achieve the above object, the reference voltage generation circuit of the present invention can be configured such that the fourth transistor and the fifth transistor are low threshold voltage transistors.

  In order to achieve the above object, the reference voltage generating circuit of the present invention can be configured such that the fourth transistor and the fifth transistor are depletion type transistors.

  In order to achieve the above object, the reference voltage generation circuit of the present invention can be configured such that the fourth transistor and the fifth transistor are transistors each having a conductive impurity gate.

  As a result, the reference voltage generation circuit of the present invention can operate with a low power supply voltage.

  In the reference voltage generating circuit of the present invention, in order to achieve the above object, the third transistor has the same characteristics as those of the MOS transistor constituting the current mirror circuit. The load current flowing through the load may be equal to the drain current of the first transistor.

  This improves the accuracy of the current mirror circuit and improves the mirror current accuracy.

  In order to achieve the above object, the reference voltage generating circuit according to the present invention can be further configured to have a constant current source for the load of the third transistor.

  As a result, the load current of the third transistor is made the same as that of the first transistor.

  In order to achieve the above object, the reference voltage generation circuit of the present invention further includes a gate of the third transistor connected to the pair of MOS transistors via a sixth transistor having a load as a constant current source. It can be set as the structure connected to one output side.

  Thereby, the drain voltages of the transistors constituting the current mirror circuit are equalized, and the mirror current accuracy is improved.

  In order to achieve the above object, the reference voltage generation circuit of the present invention further includes a gate of the sixth transistor connected to one of the pair MOS transistors via the third transistor having a load as a resistance. It can be set as the structure connected to the output side.

  This makes the load current of the third transistor the same as the drain current of the first transistor.

  In order to achieve the above object, the reference voltage generation circuit according to the present invention further includes a configuration in which the reference voltage generation circuit uses a voltage proportional to a voltage at a connection point between the third transistor and the load as an output voltage. It can be.

  As a result, the reference voltage generation circuit of the present invention can acquire a low-voltage reference voltage.

  In order to achieve the above object, the reference voltage generation circuit according to the present invention is further connected to the third transistor or the sixth transistor to form a current mirror circuit. A transistor may be provided to output the drain current of the seventh transistor.

  As a result, the reference voltage generation circuit of the present invention can output a reference voltage and a constant current.

  According to the reference voltage generating circuit of the present invention, it is possible to operate with a low power supply voltage, and further, it is possible to supply a stable reference voltage by reducing the output impedance.

  The reference voltage generating circuit according to the present invention is such that the gate and source of a depletion type transistor are connected, and the gate voltage of the enhancement type transistor is used as an output voltage in a state where the source of the depletion type transistor and the enhancement type transistor is grounded. It is. Embodiments of the present invention will be described below in detail with reference to the drawings.

  FIG. 3 is a circuit diagram showing Example 1 of the reference voltage generating circuit of the present invention. The reference voltage generating circuit 30 shown in FIG. 1 includes transistors M1, M2, M5 and M6, transistors M3 and M4 which are paired MOS transistors manufactured using a work function difference between gate electrodes, and resistors R1 and R2. ing. Here, the transistors M1, M2, M5, and M6 are PMOS transistors having the same characteristics. The transistor M3 is a depletion type NMOS transistor having an n-type gate, and the transistor M4 is an enhancement type NMOS transistor having a p-type gate.

  The transistors M1 and M2 have their sources and gates connected in common, and the power supply voltage Vin is applied to the commonly connected sources. The commonly connected gates are connected to the drain of the transistor M2, forming a current mirror circuit.

  The drain of the transistor M3 is connected to the drain of the transistor M1. The drain of the transistor M4 is connected to the drain of the transistor M2. The gate and the source of the transistor M3 are connected and grounded to constitute a constant current source. The source of the transistor M4 is grounded, and the gate of the transistor M4 is connected to the connection point between the drain of the transistor M5 and the resistor R1.

  The drain of the transistor M5 is connected to one end of the resistor R1, and is grounded via the resistors R1 and R2 connected in series. The source voltage Vin is applied to the source of the transistor M5, and the gate is connected to the drain of the transistor M1. Here, the transistor M5, the resistor R1, and the resistor R2 constitute a source grounding circuit 35 that uses the resistor R1 and the resistor R2 as a load of the transistor M5.

  The power supply voltage Vin is applied to the source of the transistor M6, and the gate of the transistor M6 is commonly connected to the gate of the transistor M5. The drain of the transistor M6 is connected to the current output terminal PBIAS.

  Next, the operation of the reference voltage generation circuit 30 shown in FIG. 3 will be described.

  The drain current I1 of the transistor M1 is equal to the drain current I4 of the transistor M4. Here, the transistors M1 and M2 have the same characteristics, and their drain currents I1 and I2 are equal. Since I1 = I3 and I2 = I4, the drain current I4 of the transistor M4 is equal to the drain current I3 of the transistor M3.

  The drain of the transistor M3 is connected to the gate of the transistor M5 constituting the common source circuit 35. The output of the common source circuit 35 is connected to the gate of the transistor M4 to form a negative feedback loop for supplying the gate voltage of the transistor M4 so that the drain current I4 of the transistor M4 becomes equal to the drain current I3 of the transistor M3. . As a result, the gate voltage of the transistor M4 is set to a voltage determined by the drain current I3 of the transistor M3 constituting the constant current source. The gate voltage of the transistor M4 becomes the reference voltage VrefH that is the output voltage of the reference voltage generation circuit 30.

  At this time, the power supply voltage Vin is the higher of the reference voltage VrefH and the sum of the source-drain voltage of the transistor M5 or the sum of the gate-source voltage of the transistor M2 and the drain-source voltage of the transistor M4. It becomes.

  Here, regarding the latter voltage, if a transistor having a low threshold voltage is adopted as the transistor M1 and the transistor M2, the latter voltage can be easily reduced. Therefore, the power supply voltage Vin in this embodiment is the sum of the reference voltage VrefH and the source-drain voltage of the transistor M5. Note that the low threshold voltage described here is about 0.2 to 0.5V.

  At this time, the source-drain voltage of the transistor M5 can be set to 0.3 V or less. Therefore, in the reference voltage generation circuit 30, the power supply voltage Vin can be made low. Further, the power supply voltage Vin (input voltage) and the reference voltage VrefH (output voltage) are extremely close to each other, and the difference between the input voltage and the output voltage is reduced, so that the power supply efficiency can be improved.

  Furthermore, since the reference voltage VrefH is output as the output voltage of the source ground circuit 35, the output impedance is lowered. Therefore, the reference voltage VrefH can be divided by the resistors R1 and R2, and a voltage proportional to the reference voltage VrefH and lower than the reference voltage VrefH can be supplied as the reference voltage VrefL.

  The transistor M5 is a transistor having the same characteristics as the transistors M1 and M2 constituting the current mirror circuit, and the resistances of the resistors R1 and R2 are set so that the drain current I5 of the transistor M5 is equal to the drain current I1. Value is set. For this reason, the gate voltage of the transistor M5 is equal to the gate voltages of the transistors M1 and M2.

  Here, the drain of the transistor M1 and the gate of the transistor M5 are connected, and the drain voltage of the transistor M1 and the gate voltage of the transistor M5 are at the same potential. The drain of the transistor M2 is connected to the gates of the commonly connected transistors M1 and M2, and the drain voltage of the transistor M2 has the same potential as the gate voltages of the transistors M1 and M2. That is, the drain voltage of the transistor M2 is the same potential as the gate voltage of the transistor M5.

  Therefore, the drain voltage of the transistor M1 and the drain voltage of the transistor M2 are the same potential. Thereby, in the transistor M1 and the transistor M2, the error of the drain current caused by the difference in drain voltage can be eliminated. That is, the error of the mirror current due to the channel length modulation effect can be eliminated, and the accuracy of the current mirror circuit can be improved.

  Further, if the accuracy of the current mirror circuit is improved, the fluctuation of the drain current of the transistor M3 is reduced, and the gate voltage (reference voltage VrefH) of the transistor M4 determined by the drain current I3 is stabilized. Therefore, the reference voltage generation circuit 30 can generate a stable reference voltage VrefH.

  The gates and sources of the transistors M5 and M6 are connected in common, and the power supply voltage Vin is applied to the commonly connected sources. The commonly connected gates are connected to the drain of the transistor M1.

  Since the drain current I5 of the transistor M5 is set to be equal to the drain current I1, the drain voltage of the transistor M5 is the same potential as the drain voltage of the transistor M1. Therefore, the transistors M5 and M6 form a current mirror circuit, and the drain current I6 of the transistor M6 becomes a constant current equal to the drain current I5 of the transistor M5.

  Here, by connecting the drain of the transistor M6 to the current output terminal PBIAS, the drain current I6 of the transistor M6, which is a constant current, is obtained as the output current. At this time, it is preferable that the temperature characteristics of the resistors R1 and R2 are small. The smaller the temperature characteristics, the more stable constant current that does not affect the temperature change can be obtained.

  In this embodiment, an example using a pair MOS transistor manufactured by using a work function difference of the gate electrode is shown, but the present invention is not limited to this. For example, the transistor M3 is a depletion type transistor. A similar function can be realized if M4 is an enhancement type transistor.

  Next, the temperature characteristics of the reference voltage generation circuit 30 will be described.

  FIG. 4 is a diagram showing the relationship between the drain current Id and the gate-source voltage Vgs of the depletion type transistor and the enhancement type transistor.

  The drain current when the gate and source of the depletion type transistor are connected is Id1 shown in FIG. The gate voltage of the enhancement type transistor when this drain current Id1 is provided to the enhancement type transistor is VrefH shown in FIG.

  Here, the transistor M3 in the reference voltage generation circuit 30 shown in FIG. 3 is a depletion type transistor, and the transistor M4 is an enhancement type transistor. Therefore, if the relationship shown in FIG. 4 is applied to the reference voltage generation circuit 30, the reference voltage VrefH of the reference voltage generation circuit 30 shown in FIG. 3 is the gate voltage when the drain currents in the transistors M3 and M4 match. It makes a difference.

  In the case of a normal depletion type transistor, in the case of an NMOS transistor, a channel region is doped with an impurity to form an n channel in advance, and a drain current flows even when the gate-source voltage Vgs is 0V. On the other hand, in the case of a normal enhancement type NMOS transistor, when the gate-source voltage Vgs becomes the threshold voltage, an n-channel is formed in the channel region and a drain current flows out.

  As described above, in the depletion type transistor and the enhancement type transistor, if the manufacturing process of the channel region is different, each gate voltage varies independently due to the variation of the manufacturing process. As a result, the difference between the gate voltage of the depletion type transistor and the gate voltage of the enhancement type transistor varies greatly.

  Therefore, the manufacturing process of the substrate and the channel region is the same for both the depletion type transistor and the enhancement type transistor, and the depletion type transistor and the enhancement type transistor are manufactured by changing the conductivity type and concentration of the impurity doped in the gate. It is known that the difference between the gate voltage of the depletion type transistor and the gate voltage of the enhancement type transistor hardly fluctuates even if fluctuates.

  However, the depletion type transistor M3 and the enhancement type transistor M4 in the reference voltage generation circuit 30 in FIG. 3 have the same channel width and channel length. In this case, the difference between the gate voltage of the transistor M3 and the gate voltage of the transistor M4 has temperature characteristics.

  FIG. 5 is a diagram showing experimental data of temperature characteristics at each gate size ratio. Here, the gate size ratio is when the ratio Sd between the channel width Wd and the channel length Ld of the depletion type transistor is Wd / Ld, and the ratio Se between the channel width We and the channel length Le of the enhancement type transistor is We / Le. The ratio Se / Sd of Sd and Se is shown. FIG. 5 shows the temperature characteristics when the gate size ratio is 1.0, 0.67, 0.5, and 0.45 at the center temperature of 25 degrees.

  From the experimental data shown in FIG. 5, when the gate size ratio is 1.0, the temperature coefficient is -545 ppm, when the gate size ratio is 0.67, the temperature coefficient is -191 ppm, and when the gate size ratio is 0.5. It was found that the temperature coefficient was +60 ppm, and the temperature coefficient when the gate size ratio was 0.45 was +154 ppm.

  FIG. 6 is a diagram showing the relationship between each gate size ratio and the temperature coefficient. In FIG. 6, the solid line is experimental data, and the alternate long and short dash line is a straight line connecting the temperature coefficient when the gate size ratio is 1.0 and the temperature coefficient when the gate size ratio is 0.45.

  5 and 6, there is a minimum point of the temperature coefficient between the gate size ratios of 0.5 and 0.67. By analogy, the temperature coefficient is minimum between 0.54 and 0.58. The temperature coefficient was found to be about 40 ppm.

  Therefore, in the reference voltage generation circuit 30, when the ratio Sd3 of the channel width Wd3 and the channel length Ld3 of the transistor M3 is Wd3 / Ld3 and the ratio Se4 of the channel width We4 and the channel length Le4 of the transistor M4 is We4 / Le4, By setting the ratio Se3 / Sd4 between Sd3 and Se4 between 0.5 and 0.67, and more preferably between 0.54 and 0.58, the temperature characteristics of the output reference voltage VrefH can be improved.

  FIG. 7 is a circuit diagram showing the reference voltage generating circuit 40 according to the second embodiment of the present invention. The reference voltage generation circuit 40 of the second embodiment differs from the reference voltage generation circuit 30 of the first embodiment in that transistors M7 and M8 are added to the current mirror circuit, and the drains and currents of the transistors M3 and M4 are current. A transistor M9 and a transistor M10 are added between the mirror circuit. Here, the transistor M7 and the transistor M8 are PMOS transistors having the same characteristics, and the transistor M9 and the transistor M10 are NMOS transistors.

  In the second embodiment, the transistors M1 and M2 are low threshold voltage transistors, and the threshold voltages of the transistors M7 and M8 are higher than the threshold voltages of the transistors M1 and M2.

  Only the difference between the reference voltage generation circuit 40 of the second embodiment and the reference voltage generation circuit 30 of the first embodiment will be described below.

  The sources of the transistors M7 and M8 are connected in common, and the power supply voltage Vin is applied to the sources. The transistor M7 and the transistor M1 are connected in series, and the drain of the transistor M7 is connected to the source of the transistor M1. The transistor M8 and the transistor M2 are connected in series, and the drain of the transistor M8 is connected to the source of the transistor M2. The gates of the transistor M1, the transistor M2, the transistor M7, and the transistor M8 are connected in common, and the gate is connected to the drain of the transistor M2.

  In the current mirror circuit of this embodiment, since the transistor M7 and the transistor M8 are transistors having the same characteristics, the drain voltage of the transistor M7 and the drain voltage of the transistor M8 have the same potential. Therefore, even when the power supply voltage Vin varies, the transistor M7 and the transistor M8 can absorb the variation. Therefore, the drain voltages of the transistors M1 and M2 are the same potential without being affected by the fluctuation of the power supply voltage Vin.

  For this reason, the current mirror circuit of the present embodiment can eliminate a mirror current error due to the channel length modulation effect, and can be a highly accurate current mirror circuit. Further, if the accuracy of the current mirror circuit is improved, the fluctuation of the drain current of the transistor M3 is reduced, and the gate voltage (reference voltage VrefH) of the transistor M4 determined by the drain current I3 is stabilized. Therefore, the reference voltage generation circuit 40 can generate a stable reference voltage VrefH. At this time, if the transistors M7 and M8 are low threshold voltage transistors, the power supply voltage Vin hardly increases or can be slightly increased.

  The transistor M9 is connected between the drain of the transistor M1 and the drain of the transistor M3. The transistor M10 is connected between the drain of the transistor M2 and the drain of the transistor M4. The gates of the transistors M9 and M10 are commonly connected to the gate of the transistor M4, and the gate voltages of the transistors M9 and M10 are supplied from the output of the source ground circuit 35.

  According to the reference voltage generation circuit 40 of the present embodiment, the drain voltage of the transistor M3 is a voltage obtained by subtracting the gate-source voltage of the transistor M9 from the reference voltage VrefH, and the drain voltage of the transistor M4 is changed from the reference voltage VrefH to the transistor. This is a voltage obtained by subtracting the gate-source voltage of M10. As a result, even when the power supply voltage Vin varies, the drain voltages of the transistors M3 and M4 hardly vary. For this reason, the influence by the channel length modulation effect in the transistors M3 and M4 can be improved.

  That is, in the transistor M3, the drain current does not change, and the gate voltage (reference voltage VrefH) of the transistor M4 determined by the drain current of the transistor M3 does not change. For this reason, it is possible to generate a reference voltage VrefH that is more stable against fluctuations in the power supply voltage Vin.

  In addition, by using the transistors M9 and M10 as low threshold voltage transistors, the drain voltages of the transistors M3 and M4 can be further increased.

  Further, when depletion type transistors are used for the transistors M9 and M10, the drain voltages of the transistors M3 and M4 can be further increased. In this case, in order to suppress an increase in the power supply voltage Vin, the gates of the transistors M9 and M10 may be set to a potential lower than the reference voltage VrefH. For example, as shown in FIG. 7, a voltage VrefL obtained by dividing the reference voltage VrefH by the resistors R1 and R2 may be applied to the gates of the transistors M9 and M10.

  Further, the transistor M9 and the transistor M10 may be transistors having a conductive impurity gate. In the present embodiment, if the gates of the transistors M9 and M10 are high-concentration n-type, the transistors M9 and M10 are depletion type transistors.

  FIG. 8 is a circuit diagram showing the reference voltage generating circuit 50 according to the third embodiment of the present invention. The reference voltage generation circuit 50 according to the third embodiment is different from the reference voltage generation circuit 30 according to the first embodiment in that the load of the transistor M5 is a transistor M12 instead of the resistors R1 and R2 connected in series. is there. The transistor M12 is a depletion type NMOS transistor having an n-type gate.

  The transistor M12 preferably has the same characteristics as the transistor M3. The drain of the transistor M12 is connected to the drain of the transistor M5, and the source of the transistor M12 is grounded. The transistor M12 has a gate connected to the drain to form a constant current source, and the drain current of the transistor M12 generated here is equal to the drain current of the transistor M3.

  Further, since the transistor M5 has the same characteristics as the transistors M1 and M2 constituting the current mirror circuit, it becomes equal to the drain current of the transistor M5 and the drain current of the transistors M1 and M2. As a result, as described in the first embodiment, the drain voltages of the transistor M1 and the transistor M2 become the same potential, the channel length modulation effect can be suppressed, and the mirror current accuracy can be improved. Therefore, a more stable reference voltage VrefH can be generated.

  FIG. 9 is a circuit diagram showing the reference voltage generation circuit 60 according to the fourth embodiment of the present invention. The reference voltage generation circuit 60 according to the fourth embodiment is different from the reference voltage generation circuit 30 according to the first embodiment in that an inverting amplifier circuit 65 including a transistor M13 and a transistor M14 is interposed between the current mirror circuit and the source ground circuit 35. Is added.

  The transistor M13 is a PMOS transistor having the same characteristics as the transistors M1 and M2 constituting the current mirror circuit, and uses the transistor M14 as a load. The transistor M14 is a depletion type transistor having an n-type gate having the same characteristics as the transistor M3. The gate and source of the transistor M14 are connected and grounded to constitute a constant current source.

  The drain of the transistor M2 which is the output of the current mirror circuit in this embodiment is connected to the gate of the transistor M13 which is the input of the inverting amplifier circuit 65. Further, the drain of the transistor M13 which is the output of the inverting amplifier circuit 65 is connected to the gate of the transistor M5 which is the input of the common source circuit 35. Here, the transistors M1, M2, M5, and M13 have the same characteristics, and their drain voltages have the same potential.

  The drain of the transistor M5, which is the output of the common source circuit 35, is connected to the gate of the transistor M4. In the transistor M4, the gate voltage is supplied by the output of the common source circuit 35 so that the drain current I4 becomes equal to the drain current I3 of the transistor M3.

  As described above, the output of the current mirror circuit is supplied to the gate of the transistor M4 via the two-stage amplifier circuit having a transistor having the same characteristics as those of the transistors constituting the current mirror circuit. Therefore, even if the power supply voltage Vin varies, the variation is absorbed by these amplifier circuits, and the drain voltages of the transistors M1 and M2 are not affected by the variation of the power supply voltage Vin and are at the same potential. It becomes.

  As a result, as described in the third embodiment, the channel length modulation effect in the current mirror circuit can be suppressed and the mirror current accuracy can be improved. Therefore, a more stable reference voltage VrefH can be generated.

  In this embodiment, of the inverting amplifier circuit 65 and the source grounded circuit 35, the inverting amplifier circuit 65 is the first stage amplifier circuit, but the source grounded circuit 35 may be the first stage amplifier circuit (not shown). )

  In that case, the drain of the transistor M2 that is the output of the current mirror circuit is connected to the gate of the transistor M5 that is the input of the common source circuit 35, and the drain of the transistor M5 that is the output of the common source circuit 35 is the inverting amplifier circuit 65. Is connected to the gate of the transistor M13.

  The drain of the transistor M13, which is the output of the inverting amplifier circuit 65, is connected to the gate of the transistor M4. In the transistor M4, the gate voltage is supplied by the output of the inverting amplifier circuit 65 so that the drain current I4 becomes equal to the drain current I3 of the transistor M3.

  FIG. 10 is a circuit diagram showing a reference voltage generating circuit 70 according to the fifth embodiment of the present invention. The reference voltage generation circuit 70 according to the fifth embodiment is a combination of the reference voltage generation circuit 60 according to the fourth embodiment and the high-accuracy current mirror circuit described in the second embodiment.

  For this reason, also in the reference voltage generation circuit 70 of Example 5, the effect similar to the effect demonstrated in Example 2 and Example 4 can be acquired. That is, the reference voltage generation circuit 70 can suppress the channel length modulation effect in the current mirror circuit, improve the mirror current accuracy, and generate a stable reference voltage VrefH.

  As described above, according to the present invention, it is possible to provide a reference voltage generation circuit operable with a low power supply voltage. In addition, according to the present invention, it is possible to provide a reference voltage generation circuit having a very small voltage difference between an input voltage (power supply voltage) and an output voltage (reference voltage) and high power supply efficiency. In addition, according to the present invention, it is possible to provide a reference voltage generation circuit having a small output impedance.

  Furthermore, according to the present invention, it is possible to provide a reference voltage generation circuit capable of generating a stable reference voltage VrefH by suppressing the channel length modulation effect and improving the mirror current accuracy.

  As described above, the present invention has been described based on the respective embodiments, but the present invention is not limited to the requirements shown here, such as the shapes given in the above embodiments and combinations with other elements. With respect to these points, the present invention can be changed within a range that does not detract from the gist of the present invention, and can be appropriately determined according to the application form.

  The present invention is a reference voltage generation circuit that can operate at a low voltage and can supply a stable reference voltage, and can be applied to a circuit that generates a constant voltage.

This is a reference voltage generating circuit disclosed in FIG. 18 of Japanese Patent Laid-Open No. 2001-284464. This is the reference voltage generating circuit disclosed in FIG. 22 of Japanese Patent Laid-Open No. 2001-284464. 1 is a circuit diagram illustrating a first embodiment of a reference voltage generating circuit according to the present invention. FIG. It is the figure which showed the relationship between the drain current Id of a depletion type transistor and an enhancement type transistor, and the gate-source voltage Vgs. It is the figure which showed the temperature characteristic in each gate size ratio. It is the figure which showed the relationship between each gate size ratio and a temperature coefficient. It is a circuit diagram which shows the reference voltage generation circuit 40 of Example 2 of this invention. It is a circuit diagram which shows the reference voltage generation circuit 50 of Example 3 of this invention. It is a circuit diagram which shows the reference voltage generation circuit 60 of Example 4 of this invention. It is a circuit diagram which shows the reference voltage generation circuit 70 of Example 5 of this invention.

Explanation of symbols

15, 25, 35 Common source circuit 30, 40, 50, 60, 70 Reference voltage generation circuit 65 Inverting amplifier circuits M1-M14, M21-M25, M31-M34 Transistors R1, R2, R21, R22, R31 Resistance

Claims (16)

A current mirror circuit composed of two MOS transistors having the same characteristics;
Of the two MOS transistors, a depletion type transistor that is a first transistor connected to the output side of one transistor, and a second transistor that is connected to the output side of the other transistor of the two MOS transistors, A pair MOS transistor composed of an enhancement type transistor,
A third transistor connected to the output side of the first transistor or the second transistor;
A load of the third transistor connected to the output side of the third transistor,
A voltage output from a connection point between the third transistor and the load is applied to a gate of the second transistor;
The output voltage is the difference between the gate voltage of the first transistor and the gate voltage of the second transistor when the drain current of the first transistor and the drain current of the second transistor are the same. In the reference voltage generation circuit,
A gate and a source of the first transistor are connected;
A reference voltage generating circuit, wherein sources of the first transistor and the second transistor are grounded, and a gate voltage of the second transistor is used as an output voltage.   In the first transistor and the second transistor, each channel is formed with the same conductivity type, each gate is formed with a different conductivity type impurity, and the gate size of each gate is different. The reference power generation circuit according to claim 1. The ratio Sd between the channel width Wd and the channel length Ld of the first transistor is Sd = Wd / Ld, the ratio Se between the channel width We and the channel length Le of the second transistor is Se = We / Le, and the Se And the ratio of Sd is Se / Sd,
3. The reference voltage generation circuit according to claim 1, wherein Se / Sd is 0.3 to 0.67.   4. The reference voltage generation circuit according to claim 1, wherein the two MOS transistors constituting the current mirror circuit are low threshold voltage transistors.   The third transistor has the same characteristics as the MOS transistor constituting the current mirror circuit, and a load current flowing through a load of the third transistor is equal to a drain current of the first transistor. The reference voltage generation circuit according to claim 1.   6. The reference voltage generation circuit according to claim 1, further comprising a circuit that makes the drain voltage of the first transistor substantially the same as the drain voltage of the second transistor. . The circuit for setting the drain voltage of the first transistor and the drain voltage of the second transistor to substantially the same potential is disposed between the drain of the first transistor and one output side of the current mirror circuit. A fourth transistor,
A fifth transistor disposed between the drain of the second transistor and the other output side of the current mirror circuit;
The gates of the fourth transistor and the fifth transistor are connected in common;
7. The reference voltage generation circuit according to claim 6, wherein a voltage at a connection point between the third transistor and the load or a voltage proportional to the voltage is applied to the commonly connected gates. .   8. The reference voltage generation circuit according to claim 7, wherein the fourth transistor and the fifth transistor are low threshold voltage transistors.   8. The reference voltage generating circuit according to claim 7, wherein the fourth transistor and the fifth transistor are depletion type transistors.   The reference voltage generation circuit according to claim 7, wherein the fourth transistor and the fifth transistor are transistors having a conductive impurity gate. The current mirror circuit is constituted by a circuit in which two sets of two MOS transistors having different threshold voltages are connected in series, instead of being constituted by two MOS transistors having the same characteristics,
11. The reference voltage generation circuit according to claim 1, wherein in the two sets of circuits, the MOS transistor having the higher threshold voltage is arranged on a power supply voltage side.   12. The reference voltage generating circuit according to claim 1, wherein a load of the third transistor is a constant current source.   13. The gate of the third transistor is connected to one output side of the pair MOS transistor via a sixth transistor having a load as a constant current source. The reference voltage generation circuit according to one item.   14. The gate of the sixth transistor is connected to one output side of the pair MOS transistor through the third transistor having a load as a resistance. The reference voltage generation circuit described.   The reference voltage generation circuit uses a voltage proportional to a voltage at a connection point between the third transistor and the load or a voltage proportional to a voltage at a connection point between the sixth transistor and the load as an output voltage. The reference voltage generation circuit according to claim 1. The reference voltage generation circuit includes a seventh transistor connected to the third transistor or the sixth transistor and constituting a current mirror circuit,
16. The reference voltage generation circuit according to claim 1, wherein a drain current of the seventh transistor is output.

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