JP2007299528A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device of which the ground potential can be stably held even when a plurality of wordlines are driven at once. <P>SOLUTION: In the semiconductor device equipped with a plurality of memory cell arrays, a plurality of wordlines connected to the above memory cell arrays and a row decoder connected with the plurality of wordlines, such a precharge controller is furnished that all of the plurality of wordlines connected to one memory cell array among the plurality of memory cell arrays are selected by the row decoder at a first mode to precharge the selected all wordlines and all of the wordlines connected to the plurality of memory cell arrays are selected by the row decoder at a second mode to precharge all wordlines connected to a memory cell array different from the one selected at the first mode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a word line precharge of a semiconductor memory device such as a DRAM (Dynamic Random Access Memory).

  Semiconductor memory devices such as DRAMs are shipped after various tests are performed. There is a stress test as a test for detecting an initial failure of a semiconductor memory device. The stress test is also called an acceleration test, and tests the semiconductor memory device by setting the electric field and temperature to a higher value than the actual environment.

  In a stress test of a semiconductor memory device, a voltage higher than usual is applied to each memory cell to inspect for the presence of an initial failure. At this time, as in the normal operation, if the word line is selected / precharged (reset) one by one, the stress test takes a long time. Therefore, a word line multiple selection test has been proposed.

  In the word line multiple selection test mode, a plurality of word lines are sequentially selected at a time, and then one precharge command is given to the semiconductor memory device from the outside, so that all of the selected plurality of word lines are pre-applied at once. Charge.

  However, in the above word line multiple selection test, since a large number of word lines are precharged at one time just by giving a precharge command once, the peak current during precharge increases, and the ground potential VSS becomes positive. Floating in the direction of the power supply voltage VDD. When the ground potential VSS rises, the device test result becomes defective. In this case, it is impossible to determine whether the device is an original failure, that is, an initial failure, or is caused by precharging the word lines at once.

  Accordingly, an object of the present invention is to solve the above-mentioned problems of the prior art and to provide a semiconductor memory device capable of stably holding a ground potential even when a plurality of word lines are driven at a time.

  The present invention provides a semiconductor device including a plurality of memory cell arrays, a plurality of word lines connected to the memory cell array, and a row decoder to which the plurality of word lines are connected, in the first mode, the plurality of In the second mode, all the plurality of word lines connected to one memory cell array are selected by the row decoder, and all the selected word lines are precharged. A precharge controller that selects all word lines connected by the row decoder and precharges all word lines connected to a memory cell array different from that selected in the first mode; This is a featured semiconductor device. For example, N word lines are precharged by N / n in a time-sharing manner (N, n is an integer and N> n). As a result, the precharge current consumed at a time can be reduced and the ground potential can be prevented from floating.

  According to the present invention, it is possible to provide a semiconductor memory device capable of stably holding a ground potential even when a plurality of word lines are driven at a time.

  FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention. The illustrated semiconductor memory device includes two memory cell arrays 10 a and 10 b and a precharge controller 12.

  The two memory cell arrays 10a and 10b are connected to the row decoder 14 as shown in FIG. Each memory cell array 10a, 10b includes a plurality of memory cells MC arranged in a matrix. Each memory cell MC includes, for example, one transistor and one capacitor. The memory cell MC is connected to a word line WL extending from the row decoder 14. The memory cell MC is connected to the bit line BL. Each bit line BL is composed of a pair of bits, and read / write data D and / D are input / output. Since the memory cell array is divided into two memory cell arrays 10a and 10b, the word lines WL to be precharged at once are divided into two groups.

  Returning to FIG. 1, the precharge controller 12 receives the signals prez, psprz, dprex, tes14z, and sttz, and generates signals wlrpxa and wlrpxb for precharging the word lines WL of the memory cell arrays 10a and 10b, respectively. The signal prez is a precharge command (hereinafter referred to as an external precharge command) obtained by decoding an external control signal. In this embodiment, the signal psprz is a precharge command (hereinafter referred to as an internal precharge command) that is automatically generated in the semiconductor memory device after the read and ride operations without the precharge command prez. Signals dprex and tes14z are signals obtained by decoding an external control signal, and are related to the test mode. The signal sttz is a starter signal that initializes latch circuits (47, 29), (48, 30), and (31, 32) of FIG. 3 to be described later after the power is turned on, and is a pulse signal that becomes H when the power is turned on. is there. The signals wlrpxa and wlrpxb are signals that instruct the memory cell arrays 10a and 10b to precharge the word line WL, and are generated and output by the precharge controller 12.

  The precharge controller 12 can perform three controls regarding the precharge of the word line WL. The first control is control during normal operation (normal mode). The word line WL is selected and precharged (reset) one by one by an internal precharge command psprz. The second control is a test mode in which one word line WL of each of the memory cell arrays 10a and 10b is precharged one by one by an external precharge command prez. The third control precharges the word lines WL of the memory cell arrays 10a and 10b in a time division manner with an external precharge command prez and a signal pre2z described later in the word line multiple selection test mode of the present invention. For example, all the word lines WL of the memory cell array 10a are precharged at a time, and then all the word lines WL of the memory cell array 10b are precharged at a time. In the prior art, since all the word lines WL of the memory cell arrays 10a and 10b are precharged all at once, a large peak current flows and the ground potential floats. Since the word lines WL are driven by time division, the peak current at the time of precharging can be dispersed and the problem that the ground potential is floated can be solved.

  When the test mode signals dprex and tes14z are H (high level) and L (low level), respectively, the normal mode is indicated. When L and L, the test mode using the external precharge command prez is indicated. Time indicates the word line multiple selection test mode.

  FIG. 3 is a circuit diagram of the precharge controller 12. The precharge controller 12 includes inverters 21 to 31, NAND gates 41 to 47, an OR gate 48, transfer gates 51 to 53, and a transistor 55. The NAND gate 47 and the inverter 29, the NOR gate 48 and the inverter 30, and the inverters 31 and 32 constitute a latch circuit, respectively.

  4, 5 and 6 are timing charts showing the operation of the precharge controller 12 shown in FIG. 4 is in the normal mode, FIG. 5 is in the test mode using the external precharge command prez, and FIG. 6 is in the word line multiple selection test mode. 4 to 6, a signal pre2z is an output signal of the inverter 33.

  First, in the normal operation shown in FIG. 4, the external precharge signal prez is set to L (ground potential VSS), the test signal dprex is set to H, and the test signal tes14z is set to L. Note that the starter signal sttz, which is not shown in FIG. When the pulsed internal precharge signal psprz is applied to the NAND gate 42 of the precharge controller 12 (changes from L to H), the output of the NAND gate 42 changes from H to L. Just before this change, the outputs of NAND gates 43 and 44 are H. Therefore, when the internal precharge command psprz changes from L to H, the output of the NAND gate 45 changes from L to H, and the precharge signal wlrpxb changes from H to L. Further, since the output of the NAND gate 41 changes from L to H, the precharge signal wlrpxa changes from H to L. When the internal precharge signal psprz returns to L, the precharge signals wlrpxa and wlrpxb return from L to H. In response to the pulse-shaped precharge signals wlrpxa and wlrpxb generated in this way, one word line of each of the memory cell arrays 10a and 10b is precharged by the row decoder 14 shown in FIG.

  Next, in the test mode in which the external precharge command prez shown in FIG. 5 is used, the external precharge command prez is given to the precharge controller 12 as shown. At this time, the test signal dprex is set to H, and tes14z is set to L. Since the test signal dprex is H, even if the internal precharge command psprz becomes H, the output of the NAND gate 42 remains L, and the internal precharge command psprz is masked. When the external precharge command prez becomes H, the NAND gate 43 changes from H to L, and the output of the NAND gate 45 changes from L to H. Accordingly, the precharge signals wlrpxa and wlrpxb are generated in response to the external precharge command prez.

  Further, in the word line multiple selection mode shown in FIG. 6, the external precharge command prez and the internal precharge command psprz are given to the precharge controller 12 as shown. In the word line multiple selection mode, the test signal dprex is set to L and tes14z is set to H. Since the transfer gate 53 is OFF, the output of the inverter 33 remains L. Therefore, even if the test signal tes14z changes to H, the output of the NAND gate 44 remains H. As a result, the precharge signals wlrpxa and wlrpxb remain H.

  Next, the internal precharge command psprz changes from L to H. Since the test signal dprex is L, the output of the NAND gate 42 remains H. Accordingly, the precharge signals wlrpxa and wlrpxb remain at H.

  Further, an external precharge command prez is given. When the external precharge command prez changes from L to H, the output of the NAND gate 46 changes from H to L, the transfer gate 51 turns ON, and the signal tes14z is H, so the output of the NAND gate 47 becomes L. Further, the transfer gate 52 is turned off from on, and the transfer gate 53 is turned on from off. The output of the NOR gate 48 remains L in the initial state and passes through the transfer gate 53 and is latched by the latch circuit composed of the inverters 31 and 32. The output pre2z of the inverter 33 remains L. Therefore, the output of the NAND gate 44 remains H and the output of the NAND gate 45 remains L. Accordingly, the precharge signal wlrpxb remains H. Therefore, the word line WL of the memory cell array 10b is not precharged. When the external precharge command prez returns from H to L, the transfer gates 51 and 53 are turned OFF and the transfer gate 52 is turned ON. Then, the output L of the NAND gate 47 is input to the NOR gate, and the output is latched to H.

  On the other hand, when the external precharge command prez changes from L to H, the output of the NAND gate 41 changes from L to H. As a result, the precharge signal wlrpxa changes from H to L. In response to the change of the precharge signal wlrpxa, the row decoder 14 shown in FIG. 2 precharges all the selected word lines WL of the memory cell array 10a at a time.

  Next, the internal precharge command psprz is again supplied to the precharge controller 12, but the precharge signals wlrpxa and wlrpxb do not change.

  When the next external precharge command prez is given, the transfer gate 53 is turned on from OFF, so the output H of the NOR gate 48 is input to the inverter 31 and the output is latched to L. As a result, the output pre2z of the inverter 33 changes from L to H. In response to this change, the output of the NAND gate 44 changes from H to L, and the output of the NAND gate 45 changes from L to H. As a result, both precharge signals wlrpxa and wlrpxb change from H to L. In response to changes in the precharge signals wlrpxa and wlrpxb, the row decoder 14 shown in FIG. 2 precharges all the selected word lines WL in the memory cell arrays 10a and 10b at a time. In this case, since the word line WL of the memory cell array 10a is already precharged, only the word line WL of the memory cell array 10b is precharged. When the external precharge command prez returns from H to L, each latch circuit (47, 29), (48, 30), (31, 32) returns to the initial state, and the external precharge command has been input once. (The next external precharge command prez (third time) is regarded as the first time).

  Thus, all the selected word lines WL of the memory cell array 10a are precharged by the first external precharge command prez, and all the selected word lines of the memory cell array 10b are selected by the second external precharge command prez. Since WL is precharged, the peak current at the time of precharging can be dispersed and the ground potential can be prevented from floating.

  FIG. 7 is a block diagram showing the overall configuration of the semiconductor memory device 60 according to one embodiment of the present invention. The illustrated semiconductor memory device includes an address latch / decoder 61, a row decoder 62, a memory cell array 63, an input / output buffer 64, an input data latch / controller 65, a sense / switch 66, a column decoder 67, an output data controller 68, an address latch / A decoder 69, gates 70 to 75, a power controller 76, a power supply circuit 77, a test mode circuit 78, and a timing controller 79 are included.

  The precharge controller 12 shown in FIG. 1 is provided in the timing controller 79. The gate circuits 70 to 75 receive a control signal from the outside and supply a logic output to each unit. Control signals from the outside are chip enable signals / CE1, CE2, write enable signal / WE, lower and upper data mask signals / LB, / UB, and output enable signal / OE. The logic outputs of the gate circuits 71 to 75 are supplied to the test mode circuit 78. The test mode circuit 78 decodes various commands defined by the combination of these logic outputs and outputs signals corresponding to the timing controller 79 and the address latch / decoder 61. The signals output to the timing controller 79 are the aforementioned external precharge command prez and test signals dprex and tes14z.

  The timing controller 79 internally generates an internal precharge command psprz and outputs it to the precharge controller 12. The precharge controller 12 generates the precharge signals wlrpxa and wlrpxb as described above, and outputs them to the row decoder 62. The row decoder 14 shown in FIG. 2 corresponds to the row decoder 62 shown in FIG. The memory cell array 63 corresponds to the memory cell arrays 10a and 10b shown in FIGS.

  In the word line multiple selection test mode, the address signals A0 to A19 are continuously supplied, and the word lines of the memory cell arrays 10a and 10b are selected in multiple via the address latch / decoder 61 and the row decoder 62. In response to the precharge signals wlrpxa and wlrpxb, all the selected word lines WL are precharged (reset) at a time.

  FIG. 8 shows a configuration in which a negative voltage generating circuit 80 is provided in the power supply circuit 77 in the configuration of FIG. The configuration of FIG. 7 is a configuration in which the word line WL is precharged to the ground potential VSS, whereas the configuration of FIG. 8 is a configuration in which the word line WL is precharged to a negative potential lower than the ground potential VSS. As a voltage source for this purpose, the negative voltage generation circuit 80 generates a negative voltage for precharging the word line WL to a negative potential. The negative voltage generation circuit 80 includes, for example, a negative charge pump.

  The reason why the word line WL is precharged to a negative potential is to cope with the recent decrease in the power supply voltage. As the voltage is lowered, the threshold voltage of the cell transistor is decreasing. If the word line WL is reset to a negative potential, the dynamic range of operation can be increased.

  In the configuration in which the word lines are set to a negative potential in the conventional word line multiple selection test mode, a negative voltage generating circuit having a large current capacity must be used to drive all the word lines at once. In contrast, according to the present invention, the word lines WL of the memory cell array 63 are precharged in a time division manner in units of the memory cell arrays 10a and 10b. Therefore, in principle, the negative voltage generating circuit 80 having the configuration shown in FIG. As a result, power consumption and circuit area can be reduced.

  The embodiments of the present invention have been described above. In the above embodiment, the memory cell array 63 is divided into two parts. Moreover, although the said Example was a semiconductor memory device, various semiconductor devices containing DRAM are included.

1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a diagram showing a connection relationship between two memory cell arrays and a row decoder shown in FIG. 1. FIG. 2 is a circuit diagram of a configuration example of a precharge controller shown in FIG. 1. FIG. 4 is an operation timing chart during normal operation of the precharge controller shown in FIG. 3. FIG. 4 is an operation timing chart in a test mode in which an external precharge command of the precharge controller shown in FIG. 3 is used. FIG. 4 is an operation timing chart in the word line multiple selection test mode of the precharge controller shown in FIG. 3. 1 is a block diagram illustrating a configuration example of an entire semiconductor memory device according to an embodiment of the present invention. It is a block diagram which shows another structural example of the whole semiconductor memory device of one Example of this invention.

Explanation of symbols

10a, 10b Memory cell array 12 Precharge controller 14 Row decoder

Claims (5)

A plurality of memory cell arrays;
A plurality of word lines connected to the memory cell array;
In a semiconductor device comprising a row decoder to which the plurality of word lines are connected,
In the first mode, all the plurality of word lines connected to one memory cell array among the plurality of memory cell arrays are selected by the row decoder, all the selected word lines are precharged,
In the second mode, all word lines connected to the plurality of memory cell arrays are selected by the row decoder, and all word lines connected to a memory cell array different from that selected in the first mode are selected. A semiconductor device comprising: a precharge controller for performing precharge.   2. The semiconductor device according to claim 1, wherein all word lines connected to the same memory cell array are precharged simultaneously.   2. The semiconductor device according to claim 1, further comprising a test mode circuit that outputs a test control signal to the precharge controller based on an external control signal.   2. The semiconductor device according to claim 1, wherein the first and second modes are test modes. One word line connected to one memory cell array of the plurality of memory cell arrays and a third mode for precharging one word line connected to another memory cell array are provided. The semiconductor device according to claim 1.

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