JP2007293369A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that when a signal potential of a signal line in an unselected state falls owing to application of a signal potential from a select signal line to a non-select signal line, a contrast deficiency and lateral luminance variance occur to cause a decrease in image quality. <P>SOLUTION: In an active matrix type liquid crystal display device which uses time-division driving by time-division switches 30-1 to 30-k as a supply system for signal potentials to signal lines 12-1 to 12-n of a liquid crystal panel 14, low-level side potentials of select pulses S1 to S3, and XS1 to XS3 supplied from a select pulse generating circuit 36 to CMOS analog switches of the time-division switches 30-1 to 30-k are set lower than the threshold voltage of an NchMOS transistor for signal potentials output from TABIC(1) 28-1 to TABIC(k) 28-k of a horizontal driving circuit 22. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a liquid crystal display (LCD), and more particularly to an active matrix liquid crystal display device using a time-division driving method as a method of supplying a signal potential to a signal line of a liquid crystal display panel.

  A liquid crystal display device used for a personal computer, a word processor, or the like is mainly an active matrix type. This active matrix type liquid crystal display device is excellent in response speed and image quality, and has become an optimal liquid crystal display device for colorization in recent years. In this type of liquid crystal display device, a non-linear element such as a transistor or a diode is used for each pixel of the liquid crystal display panel. Specifically, a thin film transistor (TFT) is formed on a transparent insulating substrate (for example, a glass substrate).

  By the way, in a particularly large liquid crystal display device, a driver IC, which is a horizontal drive circuit that sequentially applies a signal potential to each pixel in a row unit, is placed on an external circuit substrate that is separate from the transparent insulating substrate that constitutes the liquid crystal display panel. The provided structure is adopted. The output of the external driver IC and the signal line of the liquid crystal display panel usually have a one-to-one correspondence. That is, the signal potential from each output terminal of the driver IC is directly applied to the corresponding signal line.

  On the other hand, in order to reduce the size of the driver IC, a so-called time-division driving method is known as a driving method of a liquid crystal display panel that can reduce the number of output pins (output terminals) of the driver IC. . In this time-division driving method, a plurality of signal lines are set as one unit (block), and signal potentials applied to the plurality of signal lines in the one block are output from the driver IC in time series, while the liquid crystal display panel has This is a driving method in which a time division switch is provided with a plurality of signal lines as a unit, and a time series signal potential output from the driver IC is time-divided by these time division switches and sequentially applied to the plurality of signal lines ( For example, see Patent Document 1).

JP-A 64-84297

  In an active matrix liquid crystal display device using this time-division driving method, a 1H inversion driving method in which the polarity of image data given to each pixel is inverted every 1H (H is a horizontal scanning period) with respect to a common voltage VCOM, or 1H In addition to the inversion drive, when the 1H common (VCOM) inversion drive method in which the common voltage VCOM is AC-inverted every 1H is adopted, the write potential of the signal potential jumps from the selected signal line to the non-selected signal line. Variation cannot be ignored. The reason will be described below with reference to FIG. 12 showing the configuration of the time division switch.

  In FIG. 12, a time division switch 101 is composed of a CMOS analog switch in which an Nch MOS transistor and a Pch MOS transistor are connected in parallel, and a common signal line 102 for transmitting a signal voltage output from a driver IC (not shown) and a liquid crystal display panel. It is connected to the upper signal line 103. The time division switch 101 is configured to transmit the signal voltage from the driver IC to the signal line 103 by applying the select pulse S and its inverted pulse XS to each gate of the Nch and PchMOS transistors.

  Here, when the writing potential fluctuates due to the jump of the signal potential from the selection signal line to the non-selection signal line, the signal potential of the signal line in the non-selection state is set to the ground potential (0 V) as shown in FIG. Become lower. Then, the gate potential of the NchMOS transistor has a positive potential relationship with respect to the potential of the signal line, that is, the source potential of the NchMOS transistor. Since this potential relationship satisfies the condition for turning on (conducting) the Nch MOS transistor, the Nch MOS transistor is turned on.

  Then, the signal charge flows out from the non-selected signal line through the NchMOS transistor in the on state. As a result, the signal potential of the unselected signal line is lowered. As described above, when the signal potential of the non-selected signal line decreases due to the jump of the signal potential from the selection signal line to the non-selection signal line, the image has insufficient contrast and luminance variation in the horizontal direction. It causes the quality to deteriorate.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to generate insufficient contrast or lateral luminance variation due to jumping of a signal potential from a selected signal line to a non-selected signal line. It is an object of the present invention to provide a liquid crystal display device capable of obtaining a stable image quality.

In order to achieve the above object, the present invention provides a display unit in which pixels are formed at intersections of a plurality of rows of gate lines and a plurality of columns of signal lines wired in a matrix on a transparent insulating substrate, A vertical driving circuit that is provided on a transparent insulating substrate and drives the gate lines for the plurality of rows;
A horizontal drive circuit that outputs a time-series signal potential corresponding to a predetermined number of time divisions and a CMOS transistor, and a time-series signal potential output from the horizontal drive circuit is time-divided so as to A time-division switch to be supplied to a corresponding signal line, and a select pulse generation circuit for generating a select pulse for turning on the time-division switch. The output signal potential is set to be lower than the threshold voltage of the NchMOS transistor of the CMOS transistor.

  In the liquid crystal display device having the above configuration, when the signal potential jumps from the selection signal line to the non-selection signal line, the potential of the signal line in the non-selection state changes in a decreasing direction. As a result, if a CMOS transistor is used as the time division switch, the source potential of the NchMOS transistor is lowered. However, since the potential on the low level side of the select pulse applied to the gate of the NchMOS transistor is lower than the threshold voltage of the NchMOS transistor with respect to the potential on the low level side of the signal potential, the source potential of the NchMOS transistor is at its gate. It does not drop below the potential, and the Nch MOS transistor is not turned on. Therefore, the charge of the non-selected signal line does not flow through the NchMOS transistor, and the potential of the non-selected signal line is held at the initial signal potential.

  According to the present invention, in an active matrix liquid crystal display device using a time division driving method as a signal potential supply method to a signal line of a liquid crystal display panel, a low level side of a select pulse for turning on a time division switch is provided. The potential is set lower than the threshold voltage of the NchMOS transistor with respect to the signal potential output from the horizontal drive circuit, and thus the signal potential jumps from the selection signal line to the non-selection signal line. However, the charge of the non-selected signal line does not flow out through the time division switch, and the potential of the non-selected signal line is maintained at the initial signal potential, so that the signal potential jumps from the selected signal line to the non-selected signal line. There will be no contrast shortage and no horizontal brightness variation due to image quality, and stable image quality will be obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic configuration diagram showing an active matrix liquid crystal display device according to an embodiment of the present invention. In FIG. 1, m rows of gate lines 11-1 to 11-m and n columns of signal lines 12-1 to 12-n are wired in a matrix on a transparent insulating substrate, for example, a glass substrate (not shown). Then, unit pixels 13 for m rows and n columns are formed at the intersections to constitute a liquid crystal display panel (display unit) 14.

  As is apparent from FIG. 2, the unit pixel 13 includes a thin film transistor (pixel transistor) 15, an additional capacitor 16, and a liquid crystal capacitor 17. The thin film transistor 15 has its gate electrode connected to the gate lines 11-1, 11-2, 11-3,... And its source electrode connected to the signal lines 12-1, 12-2, 12-3,. ing.

  In this pixel structure, the liquid crystal capacitance 17 means a capacitance generated between a pixel electrode formed by the thin film transistor 15 and a counter electrode formed opposite to the pixel electrode. The potential held in the pixel electrode is written as an “H” level or “L” level potential. It is assumed here that a predetermined DC potential is set as the common voltage VCOM commonly applied to the counter electrode via the Cs lines 29-1, 29-2, 29-3,.

  In the unit pixel 13, when the thin film transistor 15 is turned on, the light transmittance of the liquid crystal changes and the additional capacitor 16 is charged. Even if the thin film transistor 15 is turned off by this charging, the light transmittance state in the liquid crystal due to the charging voltage of the additional capacitor 16 is maintained until the thin film transistor 15 is turned on next time. With this method, the image quality of the display image on the liquid crystal display panel 14 can be improved.

  On the same substrate as the liquid crystal display panel 14, a vertical drive circuit 18 is formed by a thin film transistor. The vertical driving circuit 18 applies vertical scanning to the gate lines 11-1 to 11-m, each of which is connected to the output end of each row, in order to select each pixel 13 in units of vertical scanning. I do. For example, as shown in FIG. 3, the vertical drive circuit 18 includes a shift register 19, a level shifter 20, and a buffer 21.

  On the other hand, a horizontal drive circuit 22 that applies signal potentials corresponding to image data to the signal lines 12-1 to 12-n is formed on a circuit board separate from the substrate of the liquid crystal display panel 14, as will be described later. Provided as an external circuit. In the horizontal drive circuit 22, when it is assumed that a digital signal is input, it is necessary to convert the digital signal into an analog signal and output it in order to drive the liquid crystal.

  For this purpose, the horizontal drive circuit 22 has a configuration including a shift register 23, a level shifter 24, a data latch 25, a D / A converter 26, and a buffer 27 as shown in FIG. For example, digital image data capable of displaying 512 colors or more with 8 gradations or more is input to the horizontal drive circuit 22.

  For example, in order to realize 3-time division driving corresponding to R (red), G (green), and B (blue), the signal lines 12-1 to 12-n for n columns correspond to the number of time divisions. When the number (in this example, three corresponding to three time divisions) is divided as one unit (block), the horizontal drive circuit 22 corresponds to the divided number k as is apparent from FIG. It is composed of k driver ICs, that is, ICs using a TAB (Tape Automated Bonding) system (hereinafter referred to as TABIC) (1) 28-1 to TABIC (k) 28-k as a mounting system.

  These TABIC (1) 28-1 to TABIC (k) 28-k are mounted on an external circuit substrate (not shown) separate from the substrate of the liquid crystal display panel 14 and are mounted in a plurality of blocks in one divided block. In order to realize the signal potential applied to the signal line in time series and the 1H inversion driving described above, the polarity is inverted with respect to the common voltage VCOM every 1H and output. Correspondingly, k time-division switches 30-1 to 30-k are provided at the input stage of the signal lines 12-1 to 12-n for n columns.

  In order to realize the three time division, the time division switch 30-1 has three CMOS analog switches (transmission switches) 31, 32 in which PchMOS transistors and NchMOS transistors are connected in parallel, as is apparent from FIG. , 33 and formed on the same substrate as the liquid crystal display panel 14 by thin film transistors. The other time division switches 30-2 to 30-k have the same configuration as the time division switch 30-1.

  For example, in the time division switch 30-1, the input terminals of the three analog switches 31, 32, 33 are connected in common, and the common connection point is the output of the TABIC 28-1 via the common signal line 34-1. Connected to the end. As a result, a signal potential having an amplitude of, for example, 0 to 5 V output in time series from the TABIC (1) 28-1 is supplied to each of the three analog switches 31, 32, and 33 via the common signal line 34-1. Given to the input. The output ends of these analog switches 31, 32, 33 are connected to the respective ends of the three signal lines 12-1, 12-2, 12-3.

  A time-series signal potential is supplied from the TABIC (2) 28-2 to the time division switch 30-2 via the common signal line 34-2. Similarly, a time-series signal potential is supplied from the TABIC (k) 28-k to the time division switch 30-k via the common signal line 34-k. In this example, for the sake of simplicity, a configuration in which one common signal line is provided for each TABIC is shown. However, in practice, a plurality of common signal lines are associated with a plurality of output pins of the TABIC. Will be arranged.

  On the same substrate as the liquid crystal display panel 14, two control lines 35-1 to 35-6, two for each analog switch, are provided along the wiring direction of the gate lines 11-1 to 11-m. Are wired. For example, in the time division switch 30-1, the two control input terminals (that is, the gates of the Nch and PchMOS transistors) of the analog switch 31 are connected to the control lines 35-1 and 35-2 and the analog switch 32 is connected. Two control input terminals are connected to control lines 35-3 and 35-4, and two control input terminals of the analog switch 33 are connected to control lines 35-5 and 35-6, respectively.

  Here, the connection relationship of the three analog switches 31 to 33 of the time division switch 30-1 to the six control lines 35-1 to 35-6 has been described, but the other time division switches 30-2 to 30-2 are described. 30-k has the same connection relationship.

  The six control lines 35-1 to 35-6 have select pulses S1 to S3 and XS1 to XS3 for selecting the three analog switches 31 to 33 of the time division switches 30-1 to 30-k. It is supplied from an external select pulse generation circuit 36. Here, the select pulses XS1 to XS3 are inverted pulses of the select pulses S1 to S3. The select pulses S1 to S3, XS1 to XS3 are synchronized with the time-series signal potentials output from the TABICs 28-1 to 28-k, and each of the three time-division switches 30-1 to 30-k. This is a signal for sequentially turning on the analog switches 31-33.

  The selection pulses S1 to S3 and XS1 to XS3 are input to the liquid crystal display panel 14 at, for example, a plurality of locations from the horizontal drive circuit 22 side, that is, from the upper side of the liquid crystal display panel 14. Specifically, six control lines 37-1 to 37-k are mounted with TABICs 28-1 to 28-k from the select pulse generation circuit 36 for every k time-division switches 30-1 to 30-k. The six control lines 35-1 to 35-6 on the liquid crystal display panel 14 are wired through an external circuit board (not shown).

  The control lines 37-1 to 37-k are wired using, for example, TAB low expansion tape. Of the six control lines 37-1 to 37-k, the control line 37-1 has the select pulse S1, the control line 37-2 has the select pulse XS1, the control line 37-3 has the select pulse S2, The control line 37-4 transmits the select pulse XS2, the control line 37-5 transmits the select pulse S3, and the control line 37-6 transmits the select pulse XS3.

  The above configuration for inputting the select pulses S1 to S3 and XS1 to XS3 to the liquid crystal display panel 14 is merely an example, and the present invention is not limited to this.

  The select pulse generation circuit 36 has select signal pulses S1 to S3 and XS1 to XS3, while the signal potential output from the TABICs 28-1 to 28-k has a low level potential of 0 V (ground potential). Generates a pulse having an amplitude of -2V to 9V, for example, a low-level potential is lower than the ground potential and a high-level potential is higher than the high-level potential of the signal potential (5V in this example). Is configured to do.

Here, the reason why the low-level potentials of the select pulses S1 to S3 and XS1 to XS3 are set lower than the ground potential will be described with reference to FIG. 5 taking, for example, the operation of the time division switch 30-1. .

  As shown in FIG. 5A, when the select pulse S1 is at a high level, the select pulse XS1 is at a low level, and the analog switch 31 is turned on (conductive), the signal potential supplied from the common signal line 34-1 Is written to the left signal line 12-1 among the three signal lines 12-1, 12-2, 12-3 corresponding to three time divisions. Thereafter, as shown in FIG. 5B, when the select pulse S2 is at a high level, the select pulse XS2 is at a low level, and the analog switch 32 is turned on, a signal potential is written to the middle signal line 12-2.

  At this time, the left signal line 12-1 is not selected and is almost in a floating state. At this time, the signal potential of the middle signal line 12-2 jumps into the gate line 11 and the Cs line 29 wired in the horizontal direction. Thereafter, the potential jumping into the gate line 11 and the Cs line 29 jumps into the left signal line 12-1 in the non-selected state via the gate line 11 and the Cs line 29.

In the state of 1H inversion driving, the jump of the signal potential acts in the direction of increasing the amplitude potential of the Cs line 29 and the non-selected signal line 12-1. The fluctuation of the Cs line 29 and the potential of the non-selected signal line 12-1 are shown in the waveform diagram of FIG. As is apparent from this waveform diagram, the jump potential ΔVspike to the Cs line 29 causes the potential of the unselected signal line 12-1 to vary by about 1.78V to the negative side of the ground potential (0V). This is based on simulation results.

  In this state, the signal line 12-1 side of the analog switch 31 is negative. At this time, if the low-level potential of the select pulse S1 is the ground potential, the gate-source voltage Vgs of the Nch TFT becomes equal to or higher than the threshold voltage Vth, and the Nch TFT side is turned on.

  As a result, the signal charge held in the signal line 12-1 flows out to the common signal line 34-1 through the ON-state Nch TFT. As a result, the signal potential of the signal line 12-1 is lower than the signal potential written first. This reduced signal potential lowers the pixel potential, which causes image quality degradation in TN (Twisted Nematic) liquid crystal.

However, in the present embodiment, as shown in FIG. 7, by adopting a configuration in which the low-level potentials of the select pulses S1 to S3 and XS1 to XS3 are set to, for example, -2V, Even if the potential of the non-selected signal line 12-1, that is, the source potential of the NchTET fluctuates by about 1.78V from the ground potential as shown in FIG. 8, the gate potential of the NchTFT I.e., no lower than -2V.

  Therefore, since the gate-source voltage Vgs of the Nch TFT maintains a negative state and does not exceed the threshold voltage Vth, the Nch TFT is not turned on. If the Nch TFT is not turned on, the signal charge held in the signal line 12-1 through the Nch TFT does not flow out to the common signal line 34-1, so that the potential of the unselected signal line 12-1 is Thus, the signal potential written first is held.

  As described above, setting the low-level potentials of the select pulses S1 to S3 and XS1 to XS3 lower than the ground potential is related to the leakage voltage (the leakage amount of the signal potential) with respect to the threshold voltage Vth of the Nch TFT. As shown in FIG. 9, it is equivalent to using Vth in a region that is higher than the operating region of Vth when set to the ground potential, and even if the Vth of the Nch TFT varies depending on the process, It can be seen that the leakage voltage can be sufficiently suppressed.

  As a result, stable image quality can be obtained without being affected by variations in transistor characteristics. As described above, when the low-level potentials of the select pulses S1 to S3 and XS1 to XS3 are set to, for example, -2V, the leakage potential of the signal potential is less than 50 mV, as is apparent from FIG. Therefore, the level is hardly judged as an image.

  In this example, it is assumed that the low-level potential of the signal potential supplied from TABIC (1) 28-1 to TABIC (k) 28-k is 0 V (ground potential). The potential on the low level side of S3, XS1 to XS3 is set lower than the ground potential. However, if the potential on the low level side of the signal potential can be raised to the positive side, for example, 2 V, select pulses S1 to S3, XS1 It is also possible to set the low-level potential of .about.XS3 to the ground potential.

  Also, the high level side potentials of the select pulses S1 to S3, XS1 to XS3 are set to 9V, for example, on the assumption that the high level side potential of the signal potential is 5V. By setting the potential on the high level side of S1 to S3 and XS1 to XS3 higher than the potential on the high level side of the signal potential, the leakage potential related to the Pch TFT of the analog switches 31, 32, and 33 can be suppressed.

  Further, in this example, the case where the polarity of the image data given to each pixel is applied to the 1H inversion driving method in which the polarity of the image data is inverted every 1H with respect to the common voltage VCOM has been described, but in addition to the 1H inversion driving, the common voltage VCOM is set to 1H. The present invention can be similarly applied to a 1H common (VCOM) inversion driving method in which AC inversion is performed every time. In the case of the 1H common inversion driving method, as shown in FIG. 10, the potential (a) of the Cs line and the signal potential (b) of the unselected signal line have waveforms inverted every 1H.

  Next, the operation of the time division switches 30-1, 30-2, 30-3 in the active matrix liquid crystal display device according to the present embodiment having the above-described configuration will be described with reference to the timing chart of FIG. In FIG. 1, the time division switch 30-3 and the corresponding TABIC (3) are omitted.

  Also, in this example, the case of application to three time division driving corresponding to R, G, B is taken as an example, so TABIC (1) 28-1, TABIC (2) 28-2, TABIC ( 3) From 28-3, signal potentials for three pixels of R, G, and B are sequentially output in time series, and the time division switch 30-1, 30-2 and 30-3.

  Specifically, as shown in the timing chart of FIG. 11, the signal potentials of the pixels R1, G1, and B1 from the TABIC (1) 28-1 to the time division switch 30-1 are changed to TABIC (2) 28-. 2 to the time division switch 30-2, the signal potentials of the R2, G2, and B2 pixels, and the TABIC (3) 28-3 to the time division switch 30-3, the signal potentials of the R3, G3, and B3 pixels. But ... On the other hand, select pulses S1, XS1, S2, XS2, S3, and XS3 synchronized with the time-series signals are applied to the time division switches 30-1, 30-2, and 30-3.

  Thus, when the select pulse S1 is at a high level, the analog switch 31 is turned on, and the signal potentials of the pixels R1 and R3 are applied to the corresponding signal lines of the signal lines 12-1 to 12-n, respectively. When the select pulse S2 is at a high level, the analog switch 32 is turned on to apply the signal potential of the G2 pixel to the corresponding signal lines of the signal lines 12-1 to 12-n. When the select pulse S3 is at a high level, the analog switch 33 is turned on, and the signal potentials of the pixels B1 and B3 are applied to the corresponding signal lines of the signal lines 12-1 to 12-n, respectively.

  In the above embodiment, the horizontal drive circuit 22 that drives the signal lines 12-1 to 12-n is applied to a liquid crystal display device having a configuration in which the horizontal drive circuit 22 is disposed on one side (in this example, the upper side) of the liquid crystal display panel 14. However, the horizontal drive circuit 22 is divided into two parts based on the common voltage VCOM, for example, and the two horizontal drive circuits are arranged above and below the liquid crystal display panel 14 in the same manner. It is possible to apply.

1 is a schematic configuration diagram illustrating an active matrix liquid crystal display device according to an embodiment of the present invention. It is an enlarged view of the principal part of FIG. It is a block diagram which shows an example of a structure of a vertical drive circuit. It is a block diagram which shows an example of a structure of a horizontal drive circuit. It is explanatory drawing about the jump of the signal potential from a selection signal line to a non-selection signal line. It is a wave form diagram which shows the electric potential fluctuation | variation of the electric potential (a) of Cs line in the case of 1H inversion drive, and signal electric potential (b). It is a figure which shows the relationship between the analog switch which concerns on this embodiment, and a selection pulse. It is a wave form chart of signal potential of a signal line in this embodiment. It is a characteristic view showing the relationship between the threshold voltage Vth of the Nch TFT and the leakage potential of the signal potential. It is a wave form diagram which shows the electric potential fluctuation | variation of the electric potential (a) of the Cs line in the case of 1H common (VCOM) inversion drive, and signal electric potential (b). It is a timing chart of each signal in the case of three division driving. It is a figure which shows the relationship between the analog switch which concerns on a prior art example, and a selection pulse. It is a wave form chart of signal potential of a signal line in a conventional example.

Explanation of symbols

  11-1 to 11-m: gate lines, 12-1 to 12-n: signal lines, 13: unit pixels, 14: liquid crystal display panels, 15: thin film transistors, 16: additional capacitors, 17: liquid crystal capacitors, 18: vertical Drive circuit, 22 ... horizontal drive circuit, 28-1 to 28-k ... TABIC (1) to TABIC (k), 29-1 to 29-m ... Cs line, 30-1 to 30-k ... time division switch, 31-33 ... Analog switches, 34-1 to 34-k ... Common signal lines, 35-1 to 35-k, 37-1 to 37-k ... Control lines, 36 ... Select pulse generation circuit

Claims (7)

A display unit in which pixels are formed at intersections of a plurality of rows of gate lines and a plurality of columns of signal lines wired in a matrix on a transparent insulating substrate;
A vertical driving circuit provided on the transparent insulating substrate and driving the gate lines for the plurality of rows;
A horizontal drive circuit that outputs a time-series signal potential corresponding to a predetermined number of time divisions;
A time-division switch comprising a CMOS transistor and supplying a time-series signal potential output from the horizontal drive circuit to a corresponding signal line among the signal lines corresponding to the plurality of columns;
A select pulse generating circuit for generating a select pulse for turning on the time division switch,
The liquid crystal display device, wherein the potential on the low level side of the select pulse is set lower than the threshold voltage of the NchMOS transistor of the CMOS transistor with respect to the signal potential output from the horizontal drive circuit. The liquid crystal display device according to claim 1, wherein the horizontal driving circuit outputs a signal potential whose polarity is inverted every horizontal scanning period with respect to a common voltage commonly applied to the counter electrode of the pixel. The liquid crystal display device according to claim 2, wherein the common voltage is AC inverted every horizontal scanning period. The liquid crystal display device according to claim 1, wherein a low-level potential of a signal potential output from the horizontal drive circuit is a ground potential. The liquid crystal display device according to claim 1, wherein a potential on a high level side of the select pulse is higher than a potential on a high level side of a signal potential output from the horizontal drive circuit. The liquid crystal display device according to claim 1, wherein the number of time divisions by the time division switch is three. The liquid crystal display device according to claim 1, wherein the time division switch includes three analog switches corresponding to the number of time divisions.

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