JP2007267230A - Gateway device - Google Patents

Abstract

An object of the present invention is to provide a gateway device that can quickly detect an abnormality of a software processing means, stop the operation of the hardware processing means quickly, and prevent an increase in the load on the software processing means. With the goal.
Hardware processing means for receiving data frames from a plurality of communication lines, performing signal processing by hardware, and sending the data frames to the plurality of communication lines; and receiving data frames from the hardware processing means and processing by software A gateway device having software processing means for performing and supplying to hardware processing means, wherein the hardware processing means is configured to measure the time when a certain period of time has elapsed since the exchange of data frames between the hardware processing means and the software processing means. Time measuring means for stopping the operation of the hardware processing means.
[Selection] Figure 8

Description

  The present invention relates to a gateway device, and more particularly to a gateway device that relays communication data.

  For example, in a vehicle, an electronic control unit (hereinafter referred to as “ECU”) of each part of the vehicle communicates as a node via a communication network called an in-vehicle LAN (Local Area Network). Each ECU, which is a node, performs control in accordance with the value of the sensor and the operating state of the in-vehicle device, and exchanges data with other nodes as necessary. When the number of ECUs connected to the in-vehicle LAN increases, in order to reduce the load on the communication line, the communication line is divided, each communication line is connected to the gateway device, and the communication data is relayed by the gateway device. .

  The data supplied to the gateway device from the communication line includes the general data that the gateway device only transfers from one communication line to the other communication line, and the data received from one communication line and processed inside the gateway device, And processing data to be transferred to the other communication line.

  As shown in FIG. 1, the conventional general gateway device (GW) 1 is composed of only a CPU, and the CPU determines whether the received data is general data or processed data, and the general data is transferred as it is. The processed data is processed by the CPU and transferred later. Note that the processing here refers to format conversion, communication speed conversion, and the like.

  Further, as shown in FIG. 3, it has a CPU 3 and a hardware relay circuit 4, and the relay circuit 4 determines whether the received data is general data or processed data. However, in the case of processed data, there is a gateway device 5 that is transferred from the relay circuit 4 to the CPU 3, processed by the CPU 3 and transferred later.

  Note that Patent Document 1 describes a vehicle-mounted gateway that connects a plurality of LANs and mediates commands and data between the connected networks, and that the junction block unit and the gateway unit are connected and integrated by in-device wiring. Has been.

Patent Document 2 describes a device that can stop power supply to itself according to the content of the abnormality by monitoring and detecting an abnormality of the CPU using a watchdog timer.
JP 2003-175781 A JP-A-9-170931

  In the gateway device shown in FIG. 1, when an abnormality occurs in the CPU, all data is not transferred by the gateway device 1 regardless of whether it is general data or processed data as shown in FIG. In the ECU (electronic control unit), it is possible to detect abnormality of the gateway device by detecting that general data supplied at a high frequency is not transferred.

  In the gateway device 5 shown in FIG. 3, when an abnormality occurs in the CPU 3 and the relay circuit 2 is normal, the processing data supplied at a low frequency is not transferred by the CPU 3 as shown in FIG. However, since the general data supplied with high frequency is transferred by the normal relay circuit 4, the ECU 6 to which only the general data is transferred from the gateway device 5 cannot detect the abnormality of the gateway device. there were.

  Further, as shown in FIG. 5, the CPU 3 and the relay circuit 4 of the gateway device 5 are connected from the network manager (NM) 7 which is standard equipment in CAN (Controlling Area Network) which is a standard protocol of in-vehicle LAN standardized by ISO 11898 or the like. If the operation is confirmed by accessing, an abnormality of the gateway device 5 can be detected.

  However, the access from the network manager 7 to the CPU 3 and the relay circuit 4 has a long cycle of about 1 second, and it is impossible to quickly detect that an abnormality has occurred and stop the operation of the gateway device immediately. there were.

  Furthermore, a watchdog timer function is provided in the relay circuit 4, and as shown in FIG. 6, when the relay circuit 4 is periodically accessed from the CPU 3 of the gateway device and the access from the CPU 3 does not exceed a predetermined time. An abnormality of the CPU 3 can be detected by the relay circuit 4. However, if the frequency of accessing the relay circuit 4 from the CPU 3 to increase the detection time is increased, there is a problem that the load on the CPU 3 increases.

  The present invention has been made in view of the above points. It is possible to quickly detect an abnormality in the software processing means, to quickly stop the operation of the hardware processing means, and to increase the load on the software processing means. It is an object of the present invention to provide a gateway device that can prevent the above.

The gateway device of the present invention is a hardware processing means for receiving data frames from a plurality of communication lines, performing signal processing with hardware, and sending them to the plurality of communication lines;
A gateway apparatus having software processing means for supplying a data frame to the hardware processing means after being supplied with a data frame from the hardware processing means,
The hardware processing means includes a time measuring means for stopping the operation of the hardware processing means when a predetermined period of time has elapsed from the exchange of data frames between the hardware processing means and the software processing means. It is possible to detect an abnormality of the processing means as soon as possible and stop the operation of the hardware processing means as soon as possible, and to prevent an increase in the load on the software processing means.

In the gateway device,
The time measuring means sets a fixed value to a count value by exchanging data frames between the hardware processing means and the software processing means, decreases the count value by a clock signal, and counts the predetermined period. Can be configured.

  According to the present invention, it is possible to quickly detect an abnormality in the software processing means, stop the operation of the hardware processing means immediately, and prevent the load on the software processing means from increasing.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Embodiment of Gateway Device>
FIG. 7 shows a system configuration diagram of an embodiment of a communication system using the gateway device of the present invention. In the figure, ECUs 11 and 12 are connected to a communication line 13, and ECUs 14 and 15 are connected to a communication line 16. The communication lines 13 and 16 are connected to a gateway device (GW) 20.

<Configuration of gateway device>
FIG. 8 shows a configuration diagram of an embodiment of the gateway device 20 of the present invention. In the figure, the gateway device 20 includes a relay circuit 21 that performs signal processing by hardware, a CPU 22 that performs signal processing by software, and a hardware clock generation unit 23. The relay circuit 21 and the CPU 22 include a clock generation unit. The operation is performed in synchronization with the clock supplied from 23.

  The relay circuit 21 includes reception units 30A and 30B, a distribution unit 31, a counter 32, a transfer unit 33, and transmission units 34A and 34B. Each of the receiving units 30A and 30B receives data frames supplied from the communication lines 13 and 16 and supplies the data frames to the distributing unit 31.

  The distribution unit 31 determines whether each data frame is a general data frame or a processed data frame based on the header information of each data frame supplied from the receiving units 30A and 30B, and transfers the general data frame to the transfer unit 33. And the processed data frame is supplied to the CPU 22. Further, a set signal is supplied to the counter 32 at the same time as the processed data frame is supplied to the CPU 22.

  The CPU 22 includes a ROM 21a and a RAM 21b, and performs processing such as format conversion and communication speed conversion on the processing data frame by executing a program stored in the ROM 21a. In this processing, the RAM 21b is used as a work area. The CPU 22 supplies the processed data frame after processing to the transfer unit 33 in the relay circuit 21. Further, the processed data frame is supplied to the transfer unit 33 and at the same time, a set signal is supplied to the counter 32.

  When a set signal is supplied from the distribution unit 31 or the CPU 22, the counter 32 sets a preset initial value (fixed value), and performs a down-count every time a clock pulse is supplied from the clock generation unit 23. .

  When the count value becomes 0, a stop signal is generated and supplied to the transfer unit 33. The initial value corresponds to a value larger than the maximum value of the interval for transmitting and receiving the processed data frame, for example, several milliseconds.

  The transfer unit 33 supplies the general data frame supplied from the distribution unit 31 or the processed data frame supplied from the CPU 22 to the transmission units 34A and 34B. The transfer unit 33 supplies the data frame received by the receiving unit 30A to the transmitting unit 34A, and supplies the data frame received by the receiving unit 30B to the transmitting unit 34B.

  Further, when the transfer unit 33 is supplied with a stop signal from the counter 32, the transfer unit 33 stops its operation. Each of the transmission units 34A and 34B transmits the data frame supplied from the transfer unit 33 to the communication lines 13 and 16.

<Flowchart of processing executed by gateway device>
FIG. 9 shows a flowchart of processing executed by the gateway device 20. In the figure, in step S1, it is determined whether or not a processed data frame is transmitted / received, that is, whether or not a data frame is exchanged between the relay circuit 21 and the CPU 22. When the processed data frame is transmitted / received, an initial value is set in the counter 32 in step S2.

  When the processed data frame is not transmitted or received or when step S2 is completed, the count value of the counter 32 is subtracted (down-counted) in step S3. Next, in step S4, it is determined whether or not the count value of the counter 32 is 0. If the count value is not 0, the process waits in step S5 until a clock pulse is supplied, and the process proceeds to step S1.

  On the other hand, if the count value is 0, a stop signal is generated in step S6, the operation of the transfer unit 33 is stopped, and this processing cycle ends.

  In this way, the abnormality of the CPU 22 can be detected immediately, and the operation of the relay circuit 21 can be stopped immediately. Further, since it is not necessary to periodically access the relay circuit 21 from the CPU 22, it is possible to prevent the load on the CPU 22 from increasing.

  The relay circuit 21 corresponds to the hardware processing means described in the claims, the CPU 22 corresponds to the software processing means, and the counter 32 corresponds to the time measuring means.

It is a figure for demonstrating the conventional gateway apparatus. It is a figure for demonstrating the conventional gateway apparatus. It is a figure for demonstrating the conventional gateway apparatus. It is a figure for demonstrating the conventional gateway apparatus. It is a figure for demonstrating the conventional gateway apparatus. It is a figure for demonstrating the conventional gateway apparatus. It is a system configuration figure of one embodiment of a communication system using a gateway device of the present invention. It is a block diagram of one Embodiment of the gateway apparatus of this invention. It is a flowchart of the process which a gateway apparatus performs.

Explanation of symbols

11, 12, 14, 15 ECU
13, 16 Communication line 20 Gateway device 21 Relay circuit 22 CPU
23 clock generation unit 30A, 30B reception unit 31 distribution unit 32 counter 33 transfer unit 34A, 34B transmission unit

Claims (2)

Hardware processing means for receiving data frames from a plurality of communication lines, performing signal processing in hardware and sending the data frames to the plurality of communication lines;
A gateway apparatus having software processing means for supplying a data frame to the hardware processing means after being supplied with a data frame from the hardware processing means,
The hardware processing means has time measuring means for stopping the operation of the hardware processing means when a certain period of time has elapsed from the exchange of data frames between the hardware processing means and the software processing means. Gateway device. The gateway device according to claim 1, wherein
The time measuring means sets a fixed value to a count value by exchanging data frames between the hardware processing means and the software processing means, decreases the count value by a clock signal, and counts the predetermined period. The gateway apparatus characterized by comprising.

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