JP2007258747A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming stable contact holes, free from the density of gate electrodes. <P>SOLUTION: This method of forming contact holes comprises the steps of: depositing a boron phosphous-doped silicon glass (BPSG) film on a semiconductor substrate on which a transistor is formed, flattening the BPSG film, depositing an insulating layer on the BPSG film, and forming the contact holes which reaches the semiconductor substrate through the BPSG film and the insulating layer, in the cases where gate electrodes are dense in some areas and sparse in other areas. This procedure allows an etching rate between contact holes to be uniform since a BPSG thickness from the substrate becomes uniform regardless of the density of gate electrode formation regions, and the contact holes having a reduced fluctuation in contact resistances and leakage current values to be formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for forming a contact hole. More specifically, the present invention relates to a method for forming a contact hole in a region where gate electrodes are formed densely and a region where gate electrodes are formed sparsely. It is an invention relating to the forming method.

  In recent years, with the high integration of semiconductor devices, the width and pitch of gate electrodes have been reduced. Specifically, in the rule of 0.18 μm or less, the minimum space between adjacent gate electrodes is very narrow, about 0.3 μm or less. When an interlayer insulating film is embedded between such narrow gate electrodes, there is a problem that voids are generated in the interlayer insulating film between the gate electrodes.

  Therefore, heat treatment is performed on the interlayer insulating film in order to eliminate voids generated between the gate electrodes. The heat treatment is a process of heating the interlayer insulating film and reflowing the interlayer insulating film. As a result, voids generated between the gate electrodes can be released to the outside of the interlayer insulating film.

  Here, it is desirable to use a material that softens at a low temperature as a material of the interlayer insulating film subjected to the heat treatment. This is to prevent the characteristics of the transistor from being impaired by the high temperature around the transistor during heat treatment. Therefore, a BPSG film that reflows at about 800 ° C. is used for the interlayer insulating film. The BPSG film is an insulating film in which boron (B) and phosphorus (P) are doped in a silicon oxide film.

  Hereinafter, a conventional contact hole forming method in a semiconductor device using the BPSG film as an interlayer insulating film will be described with reference to the drawings. FIG. 5 is a diagram showing a cross-sectional structure of a semiconductor device in each step when a contact hole is opened in a semiconductor device in which a transistor is formed on a silicon substrate and an interlayer insulating film is further formed thereon. is there. Note that the cross-sectional structure illustrated in FIG. 5 is obtained by extracting part of a semiconductor device having a function as a switching element used in a memory or the like.

  First, a MOS transistor is formed on the silicon substrate 1. Specifically, after forming a gate oxide film (not shown), a gate electrode 2 (for example, a polysilicon film) and a sidewall 3 (for example, a TEOS film), a source region (not shown) and a drain region (see FIG. (Not shown).

  Next, a BPSG film 4 is deposited on the gate electrode 2 as an interlayer insulating film. Thereafter, the BPSG film 4 is heat-treated to reflow the BPSG film 4. As a result, voids generated between adjacent gate electrodes 2 are released to the outside of the BPSG film 4. Through the above steps, the semiconductor device has a cross-sectional structure shown in FIG. When the heat treatment is completed, a non-doped oxide film 5 such as a TEOS film is deposited on the BPSG film 4.

Here, the reason why the non-doped oxide film 5 is deposited on the BPSG film 4 will be described. The BPSG film 4 has high hygroscopicity. Specifically, when the BPSG film 4 is exposed to the atmosphere, B or P inside thereof reacts with moisture in the air, and B and P such as BPO ₄ , B ₂ O ₃ or PO ₄ A compound with O is generated and deposited on the BPSG film 4. These compounds become foreign matter on the BPSG film 4 and cause a significant decrease in yield in subsequent semiconductor device manufacturing. Therefore, a non-doped oxide film 5 as a protective film is deposited on the BPSG film 4 so that the BPSG film 4 is not exposed to the atmosphere.

  When the deposition of the non-doped oxide film 5 is completed, as shown in FIG. 5B, the surface of the non-doped oxide film 5 is planarized by chemical mechanical polishing (CMP). The planarization process here is a process performed to enable a photoresist to be accurately formed on the non-doped oxide film 5 in a subsequent process.

  Next, a photoresist 6 having an opening region 7 is formed on the planarized non-doped oxide film 5 by photolithography. As a result, the semiconductor device has a cross-sectional structure shown in FIG.

  Next, as shown in FIG. 5D, the non-doped oxide film 5 and the BPSG film 4 are dry-etched using the photoresist 6 as a mask to open contact holes 8. Thereafter, a metal (for example, tungsten) is buried in the contact hole 8 to complete the formation of the contact for connecting the transistor on the silicon substrate 1 and the wiring (not shown) formed in the upper layer.

In addition to the above contact hole forming method, the invention shown in Patent Document 1 also exists.
JP-A-9-266252

  By the way, the gate electrodes 2 of the transistors on the silicon substrate 1 are not always formed at equal intervals. Therefore, a region where the gate electrodes 2 are densely formed and a region where the gate electrodes 2 are formed sparsely exist on the silicon substrate 1. Thus, the inventors of the present application have found that the following problems exist when there are regions where the gate electrodes 2 are formed densely and regions where the gate electrodes 2 are formed sparsely. Hereinafter, the problems discovered by the inventor will be specifically described with reference to the drawings. FIG. 6 is a diagram showing a cross-sectional structure of a semiconductor device having a region where the gate electrodes 2 are densely formed and a region where the gate electrodes 2 are sparsely formed.

  First, as described in FIG. 5A, the BPSG film 4 is formed on the silicon substrate 1 and then subjected to heat treatment and reflowed. At this time, voids in the BPSG film 4 are removed and the surface of the BPSG film 4 is flattened.

  However, if there are a region where the gate electrode 2 is formed densely and a region where the gate electrode 2 is formed sparsely, even after the heat treatment, the surface of the BPSG film 4 is as shown in FIG. It has an uneven shape depending on the density of the gate electrode 2. Specifically, in the region where the gate electrodes 2 are densely formed, the film thickness De of the BPSG film 4 is thick, and in the region where the gate electrodes 2 are formed sparsely, the film thickness Df of the BPSG film 4 is thin. . As a result, the surface of the BPSG film 4 is planarized in a local region such as a region where the gate electrodes 2 are densely formed or a region where the gate electrodes 2 are formed sparsely by heat treatment. The whole is not flattened. When the non-doped oxide film 5 is deposited on the BPSG film 4 that has not been flattened globally and further planarized by CMP, the total thickness of the BPSG film 4 and the non-doped oxide film 5 is uniform. However, a phenomenon occurs in which the film thickness ratio between the BPSG film 4 and the non-doped oxide film 5 is not uniform.

When the above-described variation in the film thickness ratio occurs, the following problem occurs when the contact hole is opened. Specifically, the contact holes are opened by dry etching using a C _x F _y -based gas (for example, C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ ) and non-doped oxidation. This is done by removing the film 5. Here, the BPSG film 4 has a property that the etching rate is higher than that of the non-doped oxide film 5. Therefore, when the film thickness ratio between the BPSG film 4 and the non-doped oxide film 5 varies for each region in the semiconductor device, the interlayer insulating film (both the BPSG film 4 and the non-doped oxide film 5 are formed in each region in the semiconductor device. Etching rate varies). As a result, the contact hole opening state varies in each region in the semiconductor device.

  Specifically, referring to FIG. 6, the opening state of the contact hole 8e formed in the region where the gate electrodes 2 are formed densely and the contact formed in the region where the gate electrodes 2 are formed sparsely. A comparison is made with the open state of the hole 8f. It is assumed that the thickness of the BPSG film 4 in the region where the gate electrodes 2 are densely formed is De, and the thickness of the non-doped oxide film 5 is de. On the other hand, the thickness of the BPSG film 4 in the region where the gate electrodes 2 are formed sparsely is Df, and the thickness of the non-doped oxide film 5 is df. Moreover, the relationship of De> Df and de <df is materialized between each film thickness.

  As shown in FIG. 6, in the region where the gate electrodes 2 are formed densely, the non-doped oxide film 5 having a relatively small etching rate is thinner than the region where the gate electrodes 2 are formed sparsely, and The film thickness of the BPSG film 4 having a relatively high etching rate is increased. Therefore, the region where the gate electrodes 2 are densely formed has a higher etching rate of the interlayer insulating film than the region where the gate electrodes 2 are formed sparsely. Thereby, when the contact holes 8e and 8f are simultaneously opened, the bottom of the contact hole 8e reaches the silicon substrate 1 before the bottom of the contact hole 8f. As a result, the silicon substrate 1 is etched in the region where the transistors are densely formed. Thus, when the silicon substrate 1 is etched, a leak current is generated, causing a malfunction of the semiconductor device. On the other hand, in the region where the gate electrode 2 is formed sparsely, the bottom of the contact hole does not easily reach the silicon substrate 1, and contact open defects are likely to occur.

  Further, the contact hole has a gentle taper from the opening toward the bottom. Therefore, if the depth of the contact hole varies, the area of the bottom of the contact hole also varies, and as a result, the variation in contact resistance increases.

  Here, the silicon substrate 1 in which the region where the gate electrodes 2 are formed sparsely and the region where the gate electrodes 2 are formed is described. However, the same problem occurs when the wiring is formed on the silicon substrate 1. Will occur. Specifically, in the region where the distance between the wirings is narrow, like the region where the gate electrodes 2 are formed densely, in the region where the contact holes are formed deeply and the distance between the wirings is wide, Similar to the region where the gate electrode 2 is formed sparsely, the contact hole is formed shallow. Further, regarding the wiring, not only the distance between the wirings but also the width of the wiring affects the depth of the contact hole. Specifically, in the region where the wide wiring is formed, like the region where the gate electrode 2 is densely formed, the contact hole is formed deeply, and in the region where the narrow wiring is formed, the gate electrode The contact hole is formed shallow as in the region where 2 is formed sparsely.

  Therefore, in the present invention, when there are a region where transistors are densely formed and a region where transistors are formed sparsely, or when a region where the distance between wirings is narrow and a region where the distance is wide are present, Another object of the present invention is to provide a method for forming a stable contact hole in a two-layer insulating film having different etching rates even when the wiring width varies depending on the region in the semiconductor device.

In the present invention, after depositing the first insulating film on a semiconductor substrate having a region where the gate electrodes are formed densely and a region where the gate electrodes are formed sparsely, the first insulating film is planarized. Then, a second insulating film having a different etching rate from that of the first insulating film is deposited on the planarized first insulating film, and contacts are made to the first insulating film and the second insulating film. A hole is formed. In the case where the first insulating film is deposited on a semiconductor substrate having a densely distributed gate electrode, the thickness of the first insulating film does not become uniform depending on the densely distributed gate electrode. As described above, when the second insulating film having a different etching rate is deposited on the first insulating film having no uniform film thickness, the total etching rate of the first insulating film and the second insulating film is obtained. There is a problem that it varies depending on the location of the semiconductor device. Therefore, it becomes difficult to form a contact hole having a uniform opening state over the entire semiconductor device. Therefore, in the present invention, by flattening the first insulating film, the thickness of the first insulating film and the thickness of the second insulating film are made uniform over the entire semiconductor device, so that the first insulating film And the second insulating film are made uniform over the entire semiconductor device. As a result, it is possible to form a contact hole having a uniform opening state.

  Since the second insulating film is deposited on the planarized first insulating film, it can be deposited to have a uniform film thickness, but by planarizing the upper surface, It has a more uniform film thickness.

  For example, a BPSG film is used for the first insulating film. The BPSG film dissolves at a relatively low temperature of about 800 ° C. Therefore, when the void generated in the first insulating film is removed by heat treatment, there is no possibility that the transistor is in a high temperature state and is damaged.

  Here, it is desirable to deposit the second insulating film after the first insulating film is planarized and before the precipitate is generated on the surface of the first insulating film. This is because the precipitate inhibits the second insulating film from being uniformly deposited. Specifically, it is desirable to deposit the second insulating film within 24 hours after the first insulating film is planarized.

  On the other hand, if deposits are generated on the surface of the first insulating film before the second insulating film is deposited, the deposits may be removed. Even in this case, the second insulating film can be deposited uniformly.

  Further, the contact hole may be formed so as to reach the semiconductor substrate, or may be formed so as to reach the gate electrode.

  Further, the present invention provides a contact hole for a semiconductor device having a region where wirings are densely formed and a region where wirings are sparsely formed, or a semiconductor device where a plurality of wirings having different widths are formed. The present invention can also be applied to the formation.

  Note that the present invention is directed not only to a method for forming a contact hole but also to a semiconductor device manufactured using the method for forming a contact hole.

  According to the present invention, when contact holes are formed for two or more types of interlayer insulating films having different etching rates, the surface of each interlayer insulating film is planarized and then deposited on the gate electrode. Since the variation in the thickness of the insulating film due to the density of the formation region can be suppressed, the etching rate of contact holes existing in each place can be made constant regardless of the density of the gate electrode formation region.

As a result, the etching amount when forming the contact hole, the area of the bottom of the contact hole, and the like can be made uniform. Therefore, it is possible to provide a semiconductor device that has a small variation in contact resistance value and leakage current value, high yield, high performance, and high quality.

(First embodiment)
The contact hole forming method according to the first embodiment of the present invention will be described below with reference to the drawings. In the contact hole forming method according to this embodiment, a contact hole is opened to a semiconductor device in which an interlayer insulating film including a BPSG film and a non-doped oxide film is deposited on a silicon substrate. In the contact hole forming method, the BPSG film and the non-doped film deposited on the silicon substrate are flattened to obtain a region where the gate electrodes of the transistor are formed densely and a region where the gate electrodes are formed sparsely. Even if it exists in the semiconductor device, it has a feature in that a contact hole having a uniform opening state can be opened. Here, FIG. 1 shows a cross-sectional structure of a semiconductor device in each step when a contact hole is opened in a semiconductor device in which a transistor is formed on a silicon substrate and an interlayer insulating film is further formed thereon. It is a figure. Note that the cross-sectional structure illustrated in FIG. 1 is obtained by extracting a part of a semiconductor device having a function as a switching element used in a memory or the like.

  First, a MOS transistor is formed on the silicon substrate 1. Specifically, a gate oxide film (not shown) and a gate electrode 2 (for example, a polysilicon film having a thickness of about 200 nm) are formed. Next, after depositing a TEOS film (with a film thickness of about 200 nm), the TEOS film is subjected to an etch back method to form sidewalls 3. Thereafter, a source region (not shown) and a drain region (not shown) are formed.

  Next, a BPSG film 4 serving as an interlayer insulating film is deposited on the substrate on which the transistor is formed by a CVD (chemical vapor deposition) method. The BPSG film 4 is deposited so that the film thickness is about 1000 nm, the boron (B) concentration is about 3.0 wt%, and the phosphorus (P) concentration is about 5.0 wt%.

  Thereafter, the BPSG film 4 is reflowed by heat treatment. As a result, voids generated between the adjacent gate electrodes 2 are released out of the BPSG film 4. The heat treatment is performed, for example, by heating the semiconductor device to about 800 ° C. for about 30 minutes. As a result, the semiconductor device has the structure shown in FIG.

  Next, as shown in FIG. 1B, the surface of the BPSG film 4 is planarized by CMP. In the CMP, various conditions such as processing time are adjusted so that the film thickness of the BPSG film 4 after planarization is about 600 nm. With this process, the surface of the BPSG film 4 is globally flattened over the entire region, and has a uniform film thickness regardless of the presence or absence of the gate electrode 2 on the silicon substrate 1. In addition, this process is a process used as the characteristic part of this invention.

Next, as shown in FIG. 1C, a non-doped oxide film 5 is deposited on the surface of the BPSG film 4 planarized by CMP. Specifically, a TEOS film (film thickness of about 50 nm) is deposited by a CVD method. Here, when the surface of the BPSG film 4 is exposed to the atmosphere, B or P in the BPSG film 4 reacts with moisture in the atmosphere, and a compound such as BPO ₄ , B ₂ O ₃ , PO _4, etc. It is generated and deposited on the surface of the BPSG film 4. The compound becomes a foreign substance on the surface of the BPSG film 4 and causes a significant decrease in yield in the subsequent manufacture of the semiconductor device. Therefore, a non-doped oxide film 5 as a protective film is deposited on the BPSG film 4.

Incidentally, as described above, the BPSG film 4 when exposed to the atmosphere, to the BPSG film 4 surface foreign object by _{BPO 4, B 2 O 3,} PO compounds such as ₄ precipitated. Therefore, the non-doped oxide film 5 should be deposited immediately after the BPSG film 4 is planarized by CMP. In view of the above, a time restriction from when the surface of the BPSG film 4 is flattened to when the non-doped oxide film 5 is deposited will be described with reference to the drawings. Here, FIG. 2 shows the result of investigating the relationship between the standing time of the wafer and the number of foreign matters on the entire surface of the wafer when an 8-inch wafer is left in the environment of a normal clean room for manufacturing a semiconductor device. It is a figure. Specifically, the horizontal axis indicates the time that the wafer is left after the BPSG film 4 is planarized. The vertical axis represents the number of foreign matters per wafer.

  According to FIG. 2, after about 48 hours have passed since the BPSG film 4 was planarized, the number of foreign matters on the wafer has increased rapidly. Therefore, in this embodiment, in consideration of a certain margin, a non-doped oxide film 5 (for example, a TEOS film) is deposited within about 24 hours after the BPSG film 4 is planarized by CMP. Thereby, it is possible to prevent foreign matters from being generated on the flattened BPSG film 4 and to deposit the non-doped oxide film 5 more uniformly.

  After the non-doped oxide film 5 is deposited, a photoresist 6 having an opening region 7 in a predetermined region as shown in FIG. 1D is formed on the non-doped oxide film 5 by photolithography.

Next, as shown in FIG. 1E, using the photoresist 6 as a mask, a dry etching process is performed to open a contact hole 8 that penetrates each of the BPSG film 4 and the non-doped oxide film 5 and reaches the silicon substrate 1. To do. The dry etching process includes C ₄ F ₈ , C ₅
A C _x F _y gas such as F ₈ or C ₄ F ₆ is used.

  Thereafter, ashing or the like is performed to remove the photoresist 6. Then, a metal (for example, tungsten) is embedded in the contact hole 8. Specifically, after the metal is buried in the contact hole 8 by the CVD method or the plating method, the metal protruding from the contact hole 8 is removed by CMP. Thereby, a contact for electrically connecting a wiring or the like (not shown) formed in the upper layer and a transistor or the like formed on the silicon substrate 1 is formed.

  Here, an effect obtained by planarizing the BPSG film 4, which is a characteristic part of the contact hole forming method according to the present embodiment, will be described with reference to the drawings. FIG. 3 is a view showing a cross-sectional structure of a semiconductor device in which contact holes are formed in the interlayer insulating film by the contact hole forming method according to the present embodiment.

As described above, in this embodiment, after the BPSG film 4 is flattened, a non-doped oxide film 5 is deposited on the flattened BPSG film 4, and the non-doped oxide film 5 is further flattened. Therefore, regardless of the density of the distribution of the gate electrode 2 of the transistor formed on the silicon substrate 1, as shown in FIG. 3, the BPSG film 4 and the non-doped oxide film 5 having a uniform film thickness over the entire region of the semiconductor device are formed. Can be formed. Specifically, the film thickness Da of the BPSG film 4 in the region where the gate electrode 2 is densely formed is equal to the film thickness Db of the BPSG film 4 in the region where the gate electrode 2 is formed sparsely, and the gate The film thickness da of the non-doped oxide film 5 in the region where the electrodes 2 are densely formed is equal to the film thickness db of the non-doped oxide film 5 in the region where the gate electrodes 2 are formed sparsely. Thereby, the etching rate of the interlayer insulating film (in this case, the insulating film including both the BPSG film 4 and the non-doped oxide film 5) can be made equal over the entire region of the semiconductor device. As a result, a uniform depth is obtained in all regions of two or more types of insulating films deposited on the silicon substrate 1 having regions where the gate electrodes 2 are formed sparsely and regions formed densely. It is possible to open a plurality of contact holes having a dry etching. Therefore, according to the contact hole forming method according to the present embodiment, the etching rate is increased in the region where the gate electrodes 2 are densely formed, so that the etching proceeds to the substrate and current leakage occurs, or Since the etching rate is reduced in the region where the gate electrode 2 is formed sparsely, it is possible to prevent a phenomenon that a contact hole open failure occurs due to insufficient etching of the interlayer insulating film.

  Further, when the etching rate is uniform, the etching time and contact hole depth of each contact hole formed in the semiconductor device are uniform, so that the variation in the area of the bottom of the contact hole is reduced and the variation in contact resistance can be suppressed. . As a result, it is possible to form a contact hole having a stable opening state over the entire region of the semiconductor device regardless of the density of the gate electrode 2.

(Second Embodiment)
A contact hole forming method according to the second embodiment of the present invention will be described below with reference to the drawings. The contact hole forming method according to the second embodiment is different from the contact hole forming method according to the first embodiment in that it further includes a cleaning step. Specifically, in this embodiment, after the surface of the BPSG film 4 is planarized (FIG. 1B) and before the non-doped oxide film 5 is deposited (FIG. 1C), the planarization is performed. The surface of the converted BPSG film 4 is cleaned using a chemical solution such as an acid. In addition, about processes other than the said washing | cleaning process, 2nd Embodiment is the same as that of 1st Embodiment. Hereinafter, a contact hole forming method according to this embodiment will be described with reference to the drawings.

  First, a MOS transistor is formed on the silicon substrate 1. Specifically, a gate oxide film (not shown) and a gate electrode 2 (for example, a polysilicon film having a thickness of about 200 nm) are formed. Next, after depositing a TEOS film (with a film thickness of about 200 nm), the TEOS film is subjected to an etch back method to form sidewalls 3. Thereafter, a source region (not shown) and a drain region (not shown) are formed.

  Next, a BPSG film 4 serving as an interlayer insulating film is deposited on the substrate on which the transistor is formed by a CVD (chemical vapor deposition) method. The BPSG film 4 is deposited so that the film thickness is about 1000 nm, the boron (B) concentration is about 3.0 wt%, and the phosphorus (P) concentration is about 5.0 wt%.

  Thereafter, the BPSG film 4 is reflowed by heat treatment. As a result, voids generated between the adjacent gate electrodes 2 are released out of the BPSG film 4. The heat treatment is performed, for example, by heating the semiconductor device to about 800 ° C. for about 30 minutes. As a result, the semiconductor device has the structure shown in FIG. The steps so far are the same as those in the first embodiment.

  Next, as shown in FIG. 1B, the surface of the BPSG film 4 is planarized by CMP. In the CMP, various conditions such as processing time are adjusted so that the film thickness of the BPSG film 4 after planarization is about 600 nm. With this process, the surface of the BPSG film 4 is globally flattened over the entire region, and has a uniform film thickness regardless of the presence or absence of the gate electrode 2 on the silicon substrate 1. This process is also the same as that in the first embodiment.

  When CMP is completed, the surface of the BPSG film 4 is washed with a chemical solution such as an acid to remove impurities. Specifically, the surface of the BPSG film 4 is cleaned by immersing the semiconductor device in sulfuric acid at about 110 ° C. Then, the sulfuric acid adhering to the semiconductor device is washed away using water, and the semiconductor device is further dried.

Here, the said washing | cleaning process is demonstrated in detail. As shown in FIG. 2, after the surface of the BPSG film 4 is planarized, a non-doped oxide film 5 is deposited in the next step (FIG. 1C).
In the case where 24 hours or more elapses before that, B or P in the BPSG film 4 reacts with oxygen in the air, and a compound such as BPO ₄ , B ₂ O ₃ , PO ₄ or the like reacts with the surface of the BPSG film 4. May form and precipitate in large quantities. Therefore, if the above compound is deposited on the surface of the BPSG film 4 after the surface of the BPSG film 4 is planarized until the non-doped oxide film 5 is deposited, the compound must be removed. Therefore, in this embodiment, BPO ₄ , B ₂ O ₃ , P
By using a chemical such as an acid to dissolve the compound of O ₄ or the like, and cleaning the surface of the BPSG film 4.
In addition to sulfuric acid, for example, hydrochloric acid, nitric acid, or hydrofluoric acid exists as an acid that dissolves the above compound.

  Furthermore, by performing cleaning under conditions that dissolve only the precipitated compound and not the BPSG film 4, even if the surface of the BPSG film 4 is repeatedly cleaned, the BPSG film 4 can be reduced without impurities. Only certain compounds can be removed. Therefore, although the surface of the BPSG film 4 is once cleaned, the BPSG film 4 can be reduced even if a long time elapses until the non-doped oxide film 5 is deposited in the next step and the compound is re-deposited. Re-cleaning can be performed without consideration. Thereby, the yield of the semiconductor substrate can be further improved.

When the cleaning of the surface of the BPSG film 4 is completed, a non-doped oxide film 5 is deposited on the surface of the BPSG film 4 as shown in FIG. Specifically, a TEOS film (film thickness of about 50 nm) is deposited by a CVD method. Here, when the surface of the BPSG film 4 is exposed to the atmosphere, B or P in the BPSG film 4 reacts with moisture in the atmosphere, and a compound such as BPO ₄ , B ₂ O ₃ , PO _4, etc. It is generated and deposited on the surface of the BPSG film 4. The compound becomes a foreign substance on the surface of the BPSG film 4 and causes a significant decrease in yield in the subsequent manufacture of the semiconductor device. Therefore, a non-doped oxide film 5 as a protective film is deposited on the BPSG film 4. This step is the same as that in the first embodiment.

  After the non-doped oxide film 5 is deposited, a photoresist 6 having an opening region 7 in a predetermined region as shown in FIG. 1D is formed on the non-doped oxide film 5 by photolithography. This step is the same as that in the first embodiment.

Next, as shown in FIG. 1E, using the photoresist 6 as a mask, a dry etching process is performed to open a contact hole 8 that penetrates each of the BPSG film 4 and the non-doped oxide film 5 and reaches the silicon substrate 1. To do. The dry etching process includes C ₄ F ₈ , C ₅
A C _x F _y gas such as F ₈ or C ₄ F ₆ is used. This step is the same as that in the first embodiment.

  Thereafter, ashing or the like is performed to remove the photoresist 6. Then, a metal (for example, tungsten) is embedded in the contact hole 8. Specifically, after the metal is buried in the contact hole 8 by the CVD method or the plating method, the metal protruding from the contact hole 8 is removed by CMP. Thereby, a contact for electrically connecting a wiring or the like (not shown) formed in the upper layer and a transistor or the like formed on the silicon substrate 1 is formed.

As described above, according to the contact hole forming method according to the present embodiment, when a time (for example, 24 hours or more) has elapsed since the BPSG film 4 is planarized, the compound is deposited on the surface of the BPSG film 4. Even if it exists, since the compound deposited on the surface of the BPSG film 4 can be removed, the non-doped oxide film 5 can be deposited uniformly. That is, foreign matter on the surface of the BPSG film 4 can be reliably removed, so that it is not necessary to manage the elapsed time after the BPSG film 4 is flattened. Therefore, contact holes with uniform depth can be formed even when there is a standing time enough for the compound to precipitate after the BPSG film 4 is deposited and before the non-doped oxide film 5 is deposited. It is possible to prevent a decrease in yield in manufacturing a semiconductor device.

  The non-doped oxide film 5 in the first and second embodiments is a film other than the TEOS film as long as it is an insulating film that does not contain impurities such as B and P or an insulating film having a very low impurity concentration. Also good. An example of such an insulating film is a silicon nitride film.

  Further, the interlayer insulating film deposited on the silicon substrate 1 in the first and second embodiments is not limited to the BPSG film. The interlayer insulating film may be a film in which the uneven shape of a transistor or the like formed on the silicon substrate 1 is reflected on the surface shape. Examples of such an interlayer insulating film include a coating oxide film formed by coating, a low dielectric constant film, a PSG film in which silicon oxide film is doped with phosphorus, or a BSG film in which silicon oxide film is doped with boron. Can be mentioned. Examples of the low dielectric constant film include a SiOC film, an organic film, and a porous film.

  In the first and second embodiments, the BPSG film 4 is planarized by CMP, but may be planarized by an etch back method instead of CMP. Specifically, a resist having an etching rate substantially equal to that of the BPSG film 4 is applied to the surface of the BPSG film 4 to be planarized so that the surface becomes flat. Thereafter, dry etching is performed on the resist and the surface of the BPSG film 4 using the resist as a sacrificial film. Thereby, the entire resist and a part of the BPSG film 4 are removed. Since the resist and BPSG have substantially the same etching rate, the BPSG film 4 having a flat surface is exposed by the etch back method. Note that the non-doped oxide film 5 can be planarized by etch-back as with the BPSG film 4.

  In the first and second embodiments, the contact hole is opened between the gate electrode of the transistor, but the location of the contact hole is not limited to this. For example, the contact hole may be opened on the gate electrode or on the gate electrode wiring 12 as shown in FIG. Here, the gate electrode wiring 12 is a wiring formed on the STI (Shallow Trench Isolation) type insulating film 11 formed on the silicon substrate 1 and connected to the gate electrode of the transistor. Even in such a gate electrode wiring 12, there are a densely formed region and a sparsely formed region on the silicon substrate 1, and the same problem as in the case of the gate electrode 2 occurs. Therefore, a contact hole having a stable depth can be opened on the gate electrode wiring 12 by the contact hole forming method according to the present invention.

  The contact hole forming method according to the present invention includes a region where transistors are formed densely and a region where transistors are formed sparsely, or a region where the distance between wirings is narrow and a region where the distance is wide Even if the wiring width varies depending on the region in the semiconductor device, a stable contact hole can be formed on the two-layer insulating films having different etching rates. This is useful for applications such as forming contact holes in densely formed regions and sparsely formed regions of gate electrodes.

Process sectional drawing of the 1st Embodiment of this invention A diagram showing the relationship between substrate leaving time and the number of foreign objects generated Sectional view after contact hole formation of the present invention Sectional view after contact hole formation of the present invention Process cross section of conventional method Sectional view after contact hole formation by conventional method

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Polysilicon 3 Side wall spacer 4 BPSG film 5 Non-doped oxide film 6 Photoresist 7 Opening region 8 Contact hole

Claims (12)

A substrate having a region where gate electrodes are formed densely and a region where gate electrodes are formed sparsely;
A first insulating film formed on the substrate and having a surface planarized by CMP over a region where the gate electrodes are densely formed and a region where the gate electrodes are sparsely formed When,
A second insulating film formed on the planarized surface of the first insulating film and having an etching rate different from that of the first insulating film;
The first insulating film comprises one film selected from a BPSG film, a PSG film, a BSG film, an oxide film formed by a coating method, a low dielectric constant film, an organic film, and a porous film,
In both the region where the gate electrode is densely formed and the region where the gate electrode is sparsely formed, a contact hole of the same depth penetrating the first insulating film and the second insulating film is formed. A semiconductor device. A substrate having a region where wiring is densely formed and a region where wiring is sparsely formed;
A first insulating film formed on the substrate and having a surface subjected to planarization by CMP over a region where the wiring is densely formed and a region where the wiring is sparsely formed;
A second insulating film formed on the planarized surface of the first insulating film and having an etching rate different from that of the first insulating film;
The first insulating film comprises one film selected from a BPSG film, a PSG film, a BSG film, an oxide film formed by a coating method, a low dielectric constant film, an organic film, and a porous film,
A contact hole having the same depth penetrating the first insulating film and the second insulating film is formed in both the densely formed region and the sparsely formed region. , Semiconductor devices. A substrate on which a plurality of wirings having different widths are formed;
A first insulating film having a surface formed on the substrate and planarized by CMP over the entire region where the plurality of wirings having different widths are formed;
A second insulating film formed on the planarized surface of the first insulating film and having an etching rate different from that of the first insulating film;
The first insulating film comprises one film selected from a BPSG film, a PSG film, a BSG film, an oxide film formed by a coating method, a low dielectric constant film, an organic film, and a porous film,
A semiconductor device, wherein a contact hole having the same depth penetrating through the first insulating film and the second insulating film is formed in a region where the plurality of wirings having different widths are formed.   The semiconductor device according to claim 1, wherein the second insulating film is subjected to a planarization process.   The semiconductor device according to claim 1, wherein all the contact holes are connected to the substrate, or all the contact holes are connected to the gate electrode.   4. The semiconductor device according to claim 2, wherein all the contact holes are connected to the substrate, or all the contact holes are connected to the wiring.   2. The semiconductor device according to claim 1, wherein in a region where the gate electrodes are formed densely, a minimum interval between the adjacent gate electrodes is 0.3 μm or less.   The semiconductor device according to claim 2, wherein in a region where the wirings are densely formed, a minimum interval between the adjacent wirings is 0.3 μm or less.   The height of the upper surface of the first insulating film is higher than the height of the upper surface of the gate electrode over the region where the gate electrode is densely formed and over the region where the gate electrode is sparsely formed. The semiconductor device according to claim 1.   The height of the upper surface of the first insulating film is higher than the height of the upper surface of the wiring over the region where the wiring is formed densely and over the region where the wiring is formed sparsely. A semiconductor device according to 1.   4. The semiconductor device according to claim 3, wherein the height of the upper surface of the first insulating film is higher than the height of the upper surface of the wiring over the entire region where the plurality of wirings having different widths are formed.   The semiconductor device according to claim 1, wherein the second insulating film is a TEOS film or a silicon nitride film.

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