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JP2007253304A - Forming method of insulating separation structure - Google Patents

Forming method of insulating separation structure Download PDF

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Publication number
JP2007253304A
JP2007253304A JP2006084226A JP2006084226A JP2007253304A JP 2007253304 A JP2007253304 A JP 2007253304A JP 2006084226 A JP2006084226 A JP 2006084226A JP 2006084226 A JP2006084226 A JP 2006084226A JP 2007253304 A JP2007253304 A JP 2007253304A
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insulating
forming
separation structure
layer
active layer
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Takaaki Yoshihara
孝明 吉原
Hiroshi Noge
宏 野毛
Kiyohiko Kono
清彦 河野
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To form an insulating separation structure by a simple manufacturing process. <P>SOLUTION: A linear hole structure 15 is formed by forming a hole arriving at an insulating layer 12 on an active layer 13 at every predetermined interval. The active layer 13 existing between adjacent holes is oxidized by an oxidization process. The insulating separation structure is formed by removing a supporting layer 11 and the insulating layer 12 existing at the lower part of the hole structure 15 by an etching treatment. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、支持層と活性層により絶縁層を挟持することにより形成されたSOI(Silicon On Insulator)基板の活性層を少なくとも2つの領域に絶縁分離するための絶縁分離構造の形成方法に関する。   The present invention relates to a method for forming an insulating isolation structure for insulating and isolating an active layer of an SOI (Silicon On Insulator) substrate formed by sandwiching an insulating layer between a support layer and an active layer into at least two regions.

近年、可動部を有する部品の微細化,高精度化への要求が高まるにつれてマイクロマシン技術が発達してきている。このようなマイクロマシンとしては、静電力等によって微小なミラー部を揺動させることによりレーザ等の光ビームを走査するチルトミラー素子が知られており、光通信分野やバーコードリーダ,レーザリーダ,エリアセンサ,投写型ディスプレイ,光スイッチ等の光学機器分野において広く利用されている(非特許文献1参照)。
"Large deflection Micromechanical Scanning Mirrors for Linear Scans and Pattern Generation, IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL.6, NO.5, P.715
In recent years, micromachine technology has been developed as the demand for miniaturization and higher precision of parts having movable parts has increased. As such a micromachine, a tilt mirror element that scans a light beam such as a laser by oscillating a minute mirror portion by an electrostatic force or the like is known, and is used in the field of optical communication, barcode reader, laser reader, area, etc. Widely used in the field of optical equipment such as sensors, projection displays, and optical switches (see Non-Patent Document 1).
"Large deflection Micromechanical Scanning Mirrors for Linear Scans and Pattern Generation, IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL.6, NO.5, P.715

ところで、ミラー部を2軸方向に揺動させるチルトミラー素子では基板表面を少なくとも2つ以上の領域に分離するための絶縁分離構造の形成が必要となる。しかしながら、このような絶縁分離構造を形成するためには、基板表面に溝構造を形成し、溝構造に対し酸化処理を施し、LPCVD(Low Pressure Chemical Vopar Deposition)法によって溝構造にポリシリコン膜を埋め戻し、化学的機械研磨処理を行うことによりポリシリコン膜を除去するという非常に煩雑な工程を行わなければならない。このため、従来の絶縁分離構造の形成方法によれば、チルトミラー素子を大量生産することが困難であった。   By the way, in the tilt mirror element that swings the mirror portion in the biaxial direction, it is necessary to form an insulating separation structure for separating the substrate surface into at least two regions. However, in order to form such an isolation structure, a groove structure is formed on the substrate surface, the groove structure is oxidized, and a polysilicon film is formed on the groove structure by LPCVD (Low Pressure Chemical Vopar Deposition) method. A very complicated process of removing the polysilicon film by backfilling and chemical mechanical polishing must be performed. For this reason, according to the conventional method for forming an insulating isolation structure, it is difficult to mass-produce tilt mirror elements.

本発明は、上述した実情に鑑みて提案されたものであり、その目的は、簡単な製造プロセスによって絶縁分離構造を形成することが可能な絶縁分離構造の形成方法を提供することにある。   The present invention has been proposed in view of the above-described circumstances, and an object of the present invention is to provide a method for forming an insulating isolation structure capable of forming an insulating isolation structure by a simple manufacturing process.

上記課題を解決するために、本発明に係る絶縁分離構造の形成方法の特徴は、支持層と活性層により絶縁層を挟持することにより形成されたSOI基板の活性層を少なくとも2つの領域に絶縁分離する絶縁分離構造の形成方法であって、活性層に絶縁層に達する孔を所定間隔毎に形成することにより直線状の孔構造を形成する工程と、酸化工程によって隣接する孔間に存在する活性層を酸化する工程と、エッチング処理によって孔構造の下部に存在する支持層と絶縁層を除去する工程とを有することにある。   In order to solve the above-described problems, a feature of the method for forming an insulating isolation structure according to the present invention is that an active layer of an SOI substrate formed by sandwiching an insulating layer between a support layer and an active layer is insulated in at least two regions. A method for forming an insulating isolation structure for isolation, wherein a hole reaching the insulating layer is formed in an active layer at predetermined intervals, and a linear hole structure is formed between adjacent holes by an oxidation process. There is a step of oxidizing the active layer and a step of removing the support layer and the insulating layer existing under the hole structure by an etching process.

本発明に係る絶縁分離構造の形成方法によれば、半導体製造プロセスのみで絶縁分離構造を形成できるので、簡単な製造プロセスによって絶縁分離構造を形成することができる。   According to the method for forming an insulating isolation structure according to the present invention, the insulating isolation structure can be formed only by the semiconductor manufacturing process, and therefore the insulating isolation structure can be formed by a simple manufacturing process.

本発明は、例えば図1に示すような、ミラー部を2軸方向に揺動可能なチルトミラー素子に用いられている絶縁分離構造の形成に適用することができる。なお、図1に示すチルトミラー素子では、絶縁分離構造1,2によって活性層の領域3と領域4が絶縁分離された構造となっている。以下、図1の領域A内の絶縁分離構造1の形成方法を例として、本発明の実施形態となる絶縁分離構造の形成方法について説明する。   The present invention can be applied to, for example, the formation of an insulating separation structure used in a tilt mirror element that can swing a mirror portion in two axial directions as shown in FIG. The tilt mirror element shown in FIG. 1 has a structure in which the region 3 and the region 4 of the active layer are insulated and separated by the insulating separation structures 1 and 2. Hereinafter, the method for forming the insulating isolation structure according to the embodiment of the present invention will be described with reference to the method for forming the insulating isolation structure 1 in the region A of FIG.

図2は、図1に示す領域A内の絶縁分離構造1の上面図を示し、この絶縁分離構造1により基板表面は領域A1と領域A2とに絶縁分離されている。また、図3は、図2に示す線分X1Y1における断面図を示し、絶縁分離構造1下部の基板はエッチングにより除去されている。   FIG. 2 shows a top view of the insulating separation structure 1 in the region A shown in FIG. 1, and the insulating separation structure 1 insulates and separates the substrate surface into a region A1 and a region A2. FIG. 3 is a cross-sectional view taken along the line segment X1Y1 shown in FIG. 2, and the substrate under the insulating isolation structure 1 is removed by etching.

図2,3に示す絶縁分離構造を形成する際は、始めに、支持層11,絶縁層12,及び活性層13からなるSOI基板を用意し、図3(a)に示すように活性層13の表面に後述する孔構造15の形状に対応させてレジスト膜14をパターニングする。次に、図3(b)に示すようにD−RIE(Deep-Reactive Ion Etching)処理によって絶縁層12に到達するまでマスク14を介して活性層13をエッチングすることにより直線状の孔構造15を形成する。   When forming the insulating isolation structure shown in FIGS. 2 and 3, first, an SOI substrate including a support layer 11, an insulating layer 12, and an active layer 13 is prepared, and the active layer 13 is formed as shown in FIG. The resist film 14 is patterned on the surface of the substrate in accordance with the shape of the hole structure 15 described later. Next, as shown in FIG. 3B, the active layer 13 is etched through the mask 14 until the insulating layer 12 is reached by a D-RIE (Deep-Reactive Ion Etching) process, thereby forming a linear hole structure 15. Form.

なお、本実施形態では、孔構造15は活性層13に絶縁層12に達する孔を所定間隔毎に形成することにより形成されている。また、孔構造15は、中空構造にて構造体を支持することになるので、孔構造15を形成する孔の形状を周囲がテーパ形状になった方形形状又は円形形状にすることにより孔構造15の強度をより高くすることが望ましい。   In the present embodiment, the hole structure 15 is formed by forming holes reaching the insulating layer 12 in the active layer 13 at predetermined intervals. Further, since the hole structure 15 supports the structure with a hollow structure, the hole structure 15 is formed by changing the shape of the hole forming the hole structure 15 to a square shape or a circular shape with a tapered periphery. It is desirable to increase the strength of.

次に、図3(c)に示すようにレジスト膜14を除去した後、基板全体に対して熱酸化処理を施すことにより孔構造15を形成する孔間に存在する活性層11を酸化し、図3(d)に示すように基板の表面と裏面の双方に酸化膜16を形成する。上述の通り、孔構造15は中空構造にて構造体を支持することになるので、熱酸化処理によってより密な酸化膜16を形成する。   Next, after removing the resist film 14 as shown in FIG. 3 (c), the entire substrate is subjected to a thermal oxidation process to oxidize the active layer 11 existing between the holes forming the hole structure 15, As shown in FIG. 3D, an oxide film 16 is formed on both the front surface and the back surface of the substrate. As described above, since the hole structure 15 supports the structure with a hollow structure, a denser oxide film 16 is formed by thermal oxidation treatment.

なお、通常の酸化処理により形成される酸化膜の膜厚は酸化時間の2乗に比例し、基板表面側の酸化速度と基板内側の酸化速度の比は6対4程度となる。また、1100[℃]のパイロ酸化処理によって膜厚2[μm]の酸化膜を形成するためには10時間程度の酸化処時間が必要となる。従って、膜厚約1.5[μm]程度の活性層を全て酸化するためには約10時間弱の酸化処理が必要となり、これ以上の膜厚を酸化することは大量生産を考えると現実的ではない。従って、孔構造を形成する孔の間にある酸化膜16の膜厚は1.5[μm]以下にすることが望ましく、これにより、十分に実現可能な熱酸化時間で十分な絶縁耐圧を有する絶縁分離構造を形成することができる。   The film thickness of the oxide film formed by the normal oxidation treatment is proportional to the square of the oxidation time, and the ratio of the oxidation rate on the substrate surface side to the oxidation rate on the substrate inner side is about 6: 4. Further, in order to form an oxide film having a film thickness of 2 [μm] by a pyro-oxidation process at 1100 [° C.], an oxidation treatment time of about 10 hours is required. Therefore, in order to oxidize all the active layers having a thickness of about 1.5 [μm], an oxidation treatment of about 10 hours or less is required. is not. Therefore, it is desirable that the thickness of the oxide film 16 between the holes forming the hole structure is 1.5 [μm] or less, and thereby has a sufficient withstand voltage in a sufficiently realizable thermal oxidation time. An insulating isolation structure can be formed.

次に、図3(e)に示すように孔構造15の上にレジスト膜17をパターニングした後、図3(f)に示すようにレジスト膜17をマスクとしてエッチング処理によって基板表面側の酸化膜16を除去する。次に、図3(g)に示すようにレジスト膜17を除去した後、図3(h)に示すように孔構造16の下部領域部分を残して基板の裏面側にレジスト膜18をパターニングする。   Next, after patterning a resist film 17 on the hole structure 15 as shown in FIG. 3E, an oxide film on the substrate surface side is etched by using the resist film 17 as a mask as shown in FIG. 16 is removed. Next, after removing the resist film 17 as shown in FIG. 3 (g), the resist film 18 is patterned on the back side of the substrate leaving the lower region portion of the hole structure 16 as shown in FIG. 3 (h). .

次に、図3(i),(j)に示すようにレジスト膜18をマスクとしてエッチングすることにより孔構造16下部の酸化膜16と支持層11を順に除去した後、図3(k),(l)に示すように基板の裏面側のレジスト膜18,酸化膜16,及び絶縁層11を除去する。これにより、一連の形成工程は終了する。   Next, as shown in FIGS. 3 (i) and 3 (j), the oxide film 16 and the support layer 11 below the hole structure 16 are sequentially removed by etching using the resist film 18 as a mask. As shown in (l), the resist film 18, the oxide film 16, and the insulating layer 11 on the back side of the substrate are removed. Thereby, a series of formation processes is completed.

以上の説明から明らかなように、本発明の実施形態となる絶縁分離構造の形成方法では、活性層13に絶縁層12に達する孔を所定間隔毎に形成することにより直線状の孔構造15を形成し、酸化工程によって隣接する孔間に存在する活性層13を酸化し、エッチング処理によって孔構造15の下部に存在する支持層11及び絶縁層12を除去することにより絶縁分離構造を形成するので、半導体製造プロセスのみで絶縁分離構造を形成することが可能となり、簡単な製造プロセスによって絶縁分離構造を形成することができる。   As is clear from the above description, in the method for forming an insulating isolation structure according to the embodiment of the present invention, the linear hole structure 15 is formed by forming holes reaching the insulating layer 12 in the active layer 13 at predetermined intervals. The insulating separation structure is formed by oxidizing the active layer 13 existing between adjacent holes by an oxidation process and removing the support layer 11 and the insulating layer 12 existing below the hole structure 15 by an etching process. It is possible to form the insulation isolation structure only by the semiconductor manufacturing process, and the insulation isolation structure can be formed by a simple manufacturing process.

なお、別の実施形態として、図4(a),(b)に示すように、絶縁分離構造を形成する孔間及び酸化膜16の上面に、既存の半導体プロセスと整合性が良いCVD法を用いることにより形成されたポリシリコン膜,絶縁性の高いTEOS(テトラエトキシシラン)膜,簡便なスピンコート法により塗布可能な絶縁性を有するSOG(Spin On Glass)膜等の薄膜21を形成するようにしてもよい。このような構成によれば、絶縁分離構造の強度を高めることができる。図4(a),(b)に示す絶縁分離構造を形成する場合には、始めに、図5に示すように、図3(a)〜(d)と同様のパターニング処理,D−RIE処理,レジスト除去処理,及び熱酸化処理を行った後、図5(e)に示すように基板表面側に薄膜21を形成する。次に、図5(f)に示すように孔構造15に対応する位置にレジスト膜22をパターニングした後、図5(g),(h)に示すようにレジスト膜22をマスクとしてエッチング処理することにより孔構造15に対応する位置以外の薄膜21と酸化膜16を除去する。そして、図5(i)に示すようにエッチング処理によりレジスト22を除去した後、図3(h)〜図3(l)と同様の処理を行うことにより絶縁分離構造を形成することができる。   As another embodiment, as shown in FIGS. 4A and 4B, a CVD method having good consistency with an existing semiconductor process is formed between the holes forming the insulating isolation structure and the upper surface of the oxide film 16. A thin film 21 such as a polysilicon film formed by use, a highly insulating TEOS (tetraethoxysilane) film, and an insulating SOG (Spin On Glass) film that can be applied by a simple spin coating method is formed. It may be. According to such a configuration, the strength of the insulating separation structure can be increased. When forming the insulation isolation structure shown in FIGS. 4A and 4B, first, as shown in FIG. 5, patterning processing and D-RIE processing similar to those in FIGS. 3A to 3D are performed. Then, after performing the resist removal process and the thermal oxidation process, a thin film 21 is formed on the substrate surface side as shown in FIG. Next, after patterning the resist film 22 at a position corresponding to the hole structure 15 as shown in FIG. 5F, etching is performed using the resist film 22 as a mask as shown in FIGS. As a result, the thin film 21 and the oxide film 16 other than the position corresponding to the hole structure 15 are removed. Then, as shown in FIG. 5 (i), after removing the resist 22 by an etching process, an insulating separation structure can be formed by performing the same processes as in FIGS. 3 (h) to 3 (l).

また、別の実施形態として、図6に示すように絶縁分離構造1を多段に形成するようにしてもよい。このような絶縁分離構造によれば、工程を追加することなくパターンを変更するだけで容易に絶縁性を高めることができいる。また、孔の間隔を小さくしても十分な絶縁耐圧が得られるので、より容易に絶縁分離構造を形成することができる。また、本実施形態においても、絶縁分離構造を形成する孔間及び酸化膜の上面に薄膜を形成するようにしてもよい。   As another embodiment, the insulating isolation structure 1 may be formed in multiple stages as shown in FIG. According to such an insulating isolation structure, it is possible to easily increase the insulating property by simply changing the pattern without adding a process. In addition, since a sufficient withstand voltage can be obtained even if the space between the holes is reduced, an insulating isolation structure can be formed more easily. Also in this embodiment, a thin film may be formed between the holes forming the insulating separation structure and on the upper surface of the oxide film.

また、別の実施形態として、図7に示すように絶縁分離構造1を形成する孔を波形状(ジグザグ形状)に配列するようにしてもよい。このような絶縁分離構造1によれば、工程を追加することなくパターンを変更するだけで容易に絶縁分離構造1の強度を高めることができる。また、本実施形態においても、絶縁分離構造を形成する孔間及び酸化膜の上面に薄膜を形成するようにしてもよい。   As another embodiment, as shown in FIG. 7, the holes forming the insulating separation structure 1 may be arranged in a wave shape (zigzag shape). According to such an insulating separation structure 1, the strength of the insulating separation structure 1 can be easily increased only by changing the pattern without adding a process. Also in this embodiment, a thin film may be formed between the holes forming the insulating separation structure and on the upper surface of the oxide film.

以上、本発明者らによってなされた発明を適用した実施の形態について説明したが、この実施の形態による本発明の開示の一部をなす論述及び図面により本発明は限定されることはない。すなわち、上記実施の形態に基づいて当業者等によりなされる他の実施の形態、実施例及び運用技術等は全て本発明の範疇に含まれることは勿論であることを付け加えておく。   As mentioned above, although embodiment which applied the invention made by the present inventors was described, this invention is not limited by the description and drawing which make a part of indication of this invention by this embodiment. That is, it should be added that other embodiments, examples, operation techniques, and the like made by those skilled in the art based on the above-described embodiments are all included in the scope of the present invention.

本発明が適用されるチルトミラー素子の構成を示す上面図である。It is a top view which shows the structure of the tilt mirror element to which this invention is applied. 本発明の実施形態となる絶縁分離構造の構成を示す上面図及び断面図である。It is the top view and sectional drawing which show the structure of the insulation isolation | separation structure used as embodiment of this invention. 図2に示す絶縁分離構造の形成方法を示す断面工程図である。FIG. 3 is a cross-sectional process diagram illustrating a method for forming the insulating separation structure illustrated in FIG. 2. 図2に示す絶縁分離構造の応用例の構成を示す上面図及び断面図である。FIG. 3 is a top view and a cross-sectional view illustrating a configuration of an application example of the insulating separation structure illustrated in FIG. 2. 図4に示す絶縁分離構造の形成方法を示す断面工程図である。FIG. 5 is a cross-sectional process diagram illustrating a method for forming the insulating separation structure illustrated in FIG. 4. 図2に示す絶縁分離構造の応用例の構成を示す上面図及び断面図である。FIG. 3 is a top view and a cross-sectional view illustrating a configuration of an application example of the insulating separation structure illustrated in FIG. 2. 図2に示す絶縁分離構造の応用例の構成を示す上面図及び断面図である。FIG. 3 is a top view and a cross-sectional view illustrating a configuration of an application example of the insulating separation structure illustrated in FIG. 2.

符号の説明Explanation of symbols

1,2:絶縁分離構造
11:支持層
12:絶縁層
13:活性層
14,17,18:レジスト膜
15:孔構造
16:酸化膜
1, 2: Insulating isolation structure 11: Support layer 12: Insulating layer 13: Active layers 14, 17, 18: Resist film 15: Hole structure 16: Oxide film

Claims (5)

支持層と活性層により絶縁層を挟持することにより形成されたSOI基板の活性層を少なくとも2つの領域に絶縁分離する絶縁分離構造の形成方法であって、
前記活性層に絶縁層に達する孔を所定間隔毎に形成することにより直線状の孔構造を形成する工程と、
酸化工程によって直線状の孔構造間に存在する活性層を酸化する工程と、
エッチング処理によって孔構造の下部に存在する支持層と絶縁層を除去する工程と
を有することを特徴とする絶縁分離構造の形成方法。
A method for forming an insulating isolation structure for insulating and isolating an active layer of an SOI substrate formed by sandwiching an insulating layer between a support layer and an active layer into at least two regions,
Forming a linear hole structure by forming holes reaching the insulating layer at predetermined intervals in the active layer;
Oxidizing the active layer present between the linear pore structures by an oxidation process;
A method for forming an insulating isolation structure, comprising: a step of removing a support layer and an insulating layer existing under a hole structure by an etching process.
請求項1に記載の絶縁分離構造の形成方法であって、
前記孔構造上に薄膜を形成する工程を有することを特徴とする絶縁分離構造の形成方法。
A method for forming an insulating isolation structure according to claim 1,
A method for forming an insulating separation structure, comprising a step of forming a thin film on the hole structure.
請求項1又は請求項2に記載の絶縁分離構造の形成方法であって、
前記所定間隔は1.5[μm]以下であることを特徴とする絶縁分離構造の形成方法。
A method for forming an insulating separation structure according to claim 1 or 2,
The method for forming an insulating isolation structure, wherein the predetermined interval is 1.5 [μm] or less.
請求項1乃至請求項3のうち、いずれか1項に記載の絶縁分離構造の形成方法であって、
前記直線状の孔構造を多段に形成することを特徴とする絶縁分離構造の形成方法。
A method for forming an insulating separation structure according to any one of claims 1 to 3,
A method of forming an insulating separation structure, wherein the linear hole structure is formed in multiple stages.
請求項1乃至請求項4のうち、いずれか1項に記載の絶縁分離構造の形成方法であって、
前記孔構造を形成する孔を波状に配列することを特徴とする絶縁分離構造の形成方法。
A method for forming an insulating separation structure according to any one of claims 1 to 4,
A method for forming an insulating separation structure, wherein the holes forming the hole structure are arranged in a wavy pattern.
JP2006084226A 2006-03-24 2006-03-24 Forming method of insulating separation structure Pending JP2007253304A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008173719A (en) * 2007-01-19 2008-07-31 Canon Inc Structure body having plurality of conductive regions

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2715581B2 (en) * 1989-07-31 1998-02-18 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JP2004335568A (en) * 2003-05-01 2004-11-25 Fuji Electric Device Technology Co Ltd Method of manufacturing semiconductor device
US6879016B1 (en) * 2002-10-07 2005-04-12 Zyvex Corporation Microcomponent having intra-layer electrical isolation with mechanical robustness

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2715581B2 (en) * 1989-07-31 1998-02-18 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
US6879016B1 (en) * 2002-10-07 2005-04-12 Zyvex Corporation Microcomponent having intra-layer electrical isolation with mechanical robustness
JP2004335568A (en) * 2003-05-01 2004-11-25 Fuji Electric Device Technology Co Ltd Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008173719A (en) * 2007-01-19 2008-07-31 Canon Inc Structure body having plurality of conductive regions
US8596121B2 (en) 2007-01-19 2013-12-03 Canon Kabushiki Kaisha Structural member having a plurality of conductive regions

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