JP2007251983A - Image data output apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image data output apparatus which performs DMA transfer process at a high speed, even if compressed and uncompressed video image data are mixed, and which also can save memory. <P>SOLUTION: A CPU 8 stores location information of a video image data on a video image memory unit 2 and determination information of compression/uncompression in a descriptor region 1, when the video image data inputted from a video image data input unit 11 is compressed or uncompressed by a compression/expansion unit 7 and the data is stored in a video image memory unit 2 without changes, and also writes positional information of a chain location of divided video image data in the descriptor region 1, when video image data is compressed and the data are stored separately in a plurality of regions on the video image memory unit 2. A DMA controller 3 continuously outputs video image data, based on a predetermined information stored in the descriptor region 1, when transfer information from the CPU 8 is received. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image data output apparatus that performs DMA data transfer based on descriptor information stored in a descriptor area, and more particularly to an image data output apparatus that efficiently transfers compressed data and uncompressed data.

In recent years, with the advance of digital technology, opportunities to handle high-definition images appealing to human vision have increased. Recent digital copying machines also have a function called electronic sorting, in which image data for a plurality of originals is stored in a memory so that a specified number of copies can be obtained by one reading. In order to achieve such a demand, the amount of information to be handled has increased remarkably, and the memory capacity used for it has also increased remarkably. For this reason, the problem of memory cost and the problem of reduced processing speed have been greatly highlighted.
As one of the countermeasures, there is a great expectation for a compression process for compressing and handling image data. However, the compression rate varies greatly depending on the type of pixel data to be compressed, and depending on the image data, the compression rate exceeds 1, that is, the amount of data may expand due to compression. In such a case, the memory capacity can be reduced by storing the uncompressed pixel data in the memory without compressing the pixel data.

Further, with the recent demand for higher speed and higher efficiency of computer systems, more efficient data transfer has been required for DMA controllers that have been used for high-speed data block transfer. For this reason, a chain-type DMA controller is provided in which the data storage destination address and the number of words in the data transfer memory can be set in advance in the descriptor area of the external memory (Japanese Patent Laid-Open No. 6-103225). reference). This chain type DMA controller reads descriptor information necessary for the transfer operation stored in the descriptor area, and performs data transfer according to the information.
In Japanese Patent Laid-Open No. 9-300743, if it is determined that the image memory for storing the image data is larger than the input image data, the image data is DMA-transferred to the image memory without being compressed, and the printer engine is transferred from the image memory. Describes means for forming an image by DMA transfer. If it is determined that the image memory is smaller than the input image data, the compressed image data is DMA-transferred and stored in the image memory, decompressed from the image memory via the decompressing means, and then DMA-transferred to the printer engine. Thus, a means for forming an image is described.

However, in the above example, since image data is handled in units of one page, it is not considered even when uncompressed image data and compressed image data are mixed in a block unit in one page. It was. Further, when pixel data of a certain block cannot be stored continuously in the memory due to effective use of the memory, it may be necessary to divide and store the data in two or more memory locations.
At this time, there are various ways of compressing and storing. For example, as in the MR or MRR encoding method of a facsimile, the pixels in the target main scanning line and the pixels in the previous main scanning line are stored. In comparison, there is a case where processing is performed by “sequential processing encoding” in which the change is transmitted or “batch encoding” in which a block of pixels extending over two main scanning lines or three main scanning lines is considered. When decompressing image data that has been so processed and stored separately, the pixel data of the blocks that have been stored separately are not subjected to decompression processing by separately returning the decompression processing to the initial state, It is necessary to perform decompression processing as pixel data. That is, the processing method of the decompression means is changed between a block that can be stored in one continuous memory and a block that cannot be stored in one continuous memory but is divided and stored in two or more memory locations. There is a need.
JP-A-6-103225 Japanese Patent Laid-Open No. 9-300743

  Therefore, the problem to be solved by the present invention is that part of the descriptor information includes information indicating whether the image data to be DMA-transferred is non-compressed image data or compressed image data, and image data following the previous block. And storing information indicating whether or not the image data is handled, even if compressed image data and non-compressed image data are mixed, the DMA transfer is correctly processed at high speed, and the memory used An object of the present invention is to provide an image data output device that saves money.

  In order to solve the above-mentioned problem, according to the first aspect of the present invention, an image data input unit for inputting image data, a memory for storing image data, a compression / expansion unit for compressing or expanding image data, and image data A descriptor area for storing predetermined information for each, a DMA controller for transferring the image data, and a control unit, wherein the control unit compresses / decompresses the image data captured from the image data input unit When the image data is stored in the memory without being compressed or uncompressed, the position information of the image data on the memory and the compression / non-compression determination information are stored in the descriptor area, and the image data is compressed. When the memory is divided into a plurality of areas on the memory, the chain destination position information of the divided image data is stored in the descriptor area. The writing, the DMA controller was configured to continuously output the image data on the basis of the de-scripts region predetermined information stored in when receiving the transfer information from the control unit.

  According to the present invention, even when compressed data and non-compressed data are mixedly stored in the image memory, the data that is output after being decompressed and the data that is output without being decompressed are efficiently separated and processed. It is now possible to provide an image data output device that achieves the above.

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram showing the main part of an image data output apparatus of this embodiment provided with means for inputting image data. In FIG. 1, image data taken in through the image data input unit 11 is compressed by a compressor in the compression / decompression unit 7 and stored in the image memory unit 2 through the bus line 13 when compression is necessary. The
The CPU 8 stores in the descriptor area 1 the stored address and data amount of the image memory unit 2 and information indicating compressed data.
When the image data captured through the image data input unit 11 does not need to be compressed, it is stored in the image memory unit 2 without being compressed. Similarly, the address and data amount of the stored image memory unit 2 and information indicating that the image data is uncompressed image data are stored in the descriptor area 1.
By repeating such processing, all input image data is processed into compressed data or non-compressed data, and the storage information of the data at that time is stored in the descriptor area 1. Thereafter, when receiving an image data output command, the CPU 8 of the image data output apparatus transmits the information to a DMA controller (hereinafter referred to as DMAC 3) that performs DMA transfer. The DMAC 3 reads the descriptor information stored in the descriptor area 1 and checks whether the data block to be handled is compressed data or uncompressed data.

If it is a compressed data block, it is switched to the first path 4 by the path switching unit 6 under the instruction of the DMAC 3, and the data on the image memory unit 2 is read from the start address specified by the descriptor information. The data is transferred to the compression / decompression unit 7, subjected to the decompression process, and then output to the outside through the image data output unit 12.
If the data block to be handled is uncompressed data, it is switched to the second path 5 by the path switching unit 6 under the instruction of the DMAC 3 and the data on the image memory unit 2 from the start address specified by the descriptor information. Is output as it is from the image data output unit 12 without passing through the compression / decompression unit 7. In addition, the data is read out by the compression / expansion unit 7 in the first path 4 that reads the data on the image memory unit 2 and performs the decompression process and outputs the data to the outside through the image data output unit 12. Instead of outputting the image data immediately, the image data may be stored in the image memory unit 2 and then output to the outside through the image data output unit 12.
The ROM 10 mainly stores a program for the CPU 8, and the RAM 9 is used as a primary storage location for the calculation results of the CPU 8 and various data.
The descriptor area 1 for storing the descriptor information may be prepared independently, or a part of the image memory 2 or the RAM 9 can be used.

FIG. 2 is an explanatory diagram for explaining the main operation of the DMA transfer of the DMAC 3. Image data stored in the image memory 2 in FIG. 2 is divided into four bands.
Bands 1, 3 and 4 store compressed data encoded with a compression ratio of 1 or less, and band 2 assumes a case where the compression ratio exceeds 1 and expands. Band 4 is assumed to be divided and stored in a memory area specified by two descriptors at the time of compression. Thus, in the case of band 4, the free space in the memory is used effectively.
The DMAC 3 is mainly composed of a data transfer control unit 3 a that instructs data transfer and a descriptor storage register 3 b that instructs the location of the descriptor area 1. First, the chain destination address (a) is set in advance in the descriptor storage register 3b by the CPU 8, and the data transfer control unit 3a reads the descriptor 1 information in the descriptor area 1 from the chain destination address (a), and the descriptor storage register. Load to 3b.
The read contents are composed of, for example, 4 words as shown in FIG. 2, and a chain destination address indicating the storage address of the next descriptor information and a data storage destination address indicating the head address of the data to be transferred. There is a data transfer word number indicating the data amount of data to be transferred in word number, and format information indicating a transfer format.
Here, information indicating whether the data to be transferred is compressed data or non-compressed data is written in the least significant bit of the format information as the first predetermined bit.

That is, in this embodiment, uncompressed data is stored when the least significant bit of the format information is “1”, and compressed data is stored when the format information is “0”. In the example of this figure, the least significant bits of the five format information are “0” “1” “0” “0” “0” in order because only band 2 is uncompressed data. Therefore, in the above state, since the least significant bit of the format information is “0” in the first transfer data, the data transfer control unit 3a transfers the transfer data of band 1 corresponding to the storage destination address described in the descriptor 1 Is transferred to the compression / decompression unit 7 by DMA transfer, decompressed, and output to the outside through the image data output unit 12.
The image data output to the outside is stored as band 1 data in the designated external memory. Next, the data transfer control unit 3a recognizes the least significant bit “1” of the format information, and transfers the transfer data of band 2 corresponding to the storage destination address described in the descriptor 2 by the DMA transfer to the image data output unit 12 is output to the outside, and is stored as band 2 data in a designated external memory. In this way, all image data stored in the image memory is DMA-transferred to the external memory based on the descriptor information.

In addition, when the data to be transferred is compressed data, the second highest bit of the format information is a continuation of the data currently processed by the transfer data specified by the next descriptor information as the second predetermined bit. Information indicating whether or not is written.
That is, in this embodiment, when the most significant bit of the format information is “1”, it means that the next transfer data is a continuation of the currently processed data, and when it is “0”, the next transfer data is the next transfer. This means that the data and the data currently being processed are not continuous data.
In the example of FIG. 2, the most significant bits of the format information of the five descriptor information are “0” “0” “0” “1” “0” in order. Here, in the transfer of band 1 in which the most significant bit of the format information is “0”, the transfer data is sent to the compression / decompression unit 7 by DMA transfer, decompressed, and passed through the image data output unit 12 to be externally transmitted. Output to. When the transfer data has been sent, a code transfer end signal is sent out, and the compression / decompression unit 7 is returned to the initial state.

Next, in the band 2 transfer, the transfer data is output to the outside via the image data output unit 12 by DMA transfer without passing through the compression / decompression unit 7. In the subsequent band 3 transfer, the transfer data is sent by DMA transfer to the compression / decompression unit 7 which has been returned to the initial state at the end of the band 1 transfer, decompressed, and the transfer data is transferred to the image data output unit 12. Output to the outside. When the transfer data has been sent, a code transfer end signal is sent out, and the compression / decompression unit 7 is returned to the initial state.
Next, since only the most significant bit of the format information corresponding to the band 4-1 is “1”, the data transfer control unit 3 a sends the transfer data of the band 4-1 to the compression / decompression unit 7 by DMA transfer, After the decompression process, the image data is output to the outside through the image data output unit 12. When the transfer data of the band 4-1 has been sent, the code transfer end signal is not sent, and the compression / decompression unit 7 remains in the state of processing the last data of the band 4-1.
Therefore, the first transfer data of the next band 4-2 is decompressed in the state of the compression / decompression unit 7 that has processed the last data of the previous band 4-1, and is output to the outside through the image data output unit 12. . Thereafter, the transfer data of the band 4-2 is decompressed one after another and outputted to the outside through the image data output unit 12.
When the transfer data of the band 4-2 is sent, the compression / decompression unit 7 is returned to the initial state. In the above description, the least significant bit of the format information is described as the first predetermined bit, and the most significant bit of the format information is described as the second predetermined bit. However, the present invention is not limited to this. Absent.

FIG. 3 is a flowchart showing the main operation of the image data output apparatus of this embodiment.
First, the DMAC 3 serving as the DMA controller searches for the descriptor area 1 from the address set in the descriptor storage register 3b (step S1). Next, the first designated bit written in the descriptor information of the found descriptor area 1 is identified (step S2), and it is checked whether or not the first designated bit is “0” (step S3). If the first designation bit is “0” (Yes in step S3), the compressed data is stored in the image memory, and the read data is sent to the compression / decompression unit 7 by DMA transfer. (Step S4), the decompression process is performed, the data is output to the outside (Step S5), and this routine is terminated.
Returning to step S3, if the first designated bit is not “0” (No in step S3), the first designated bit is “1”, and it is assumed that uncompressed data is stored in the image memory. Then, without performing the decompression process, the data is directly output to the outside by DMA transfer (step S6), and this routine is terminated.

By configuring and operating as described above, in this embodiment, the DMA controller performs decompression processing on the compressed data stored in the image memory based on the descriptor information stored in the descriptor area, Since the first path for outputting and the second path for directly outputting the uncompressed data stored in the image memory are selected, the compressed data and the uncompressed data are mixed in the image memory. Even if the data is output after being decompressed, the data output without being decompressed can be efficiently separated and processed.
In this embodiment, the DMA controller selects the first path or the second path based on the identification of the first predetermined bit of the descriptor information, so that the compressed data is stored in the image memory. And uncompressed data can be easily and reliably processed efficiently.

  Also, in this embodiment, the DMA controller performs the identification of the second predetermined bit of the descriptor information when the first path is selected by the identification of the first predetermined bit of the descriptor information. Since it is determined whether or not the data of the next DMA transfer is continuous with the data currently being processed, the unit of the transfer amount indicated by the descriptor is also free, and the memory is efficient. Can be used well. In this embodiment, the DMA controller returns the decompression process to the initial state based on the determination as to whether or not the data of the next DMA transfer is continuous with the data currently being processed, Since it is selected whether the processing state remains processed, even if one image data is compressed and divided and stored in a plurality of locations, it can be correctly restored and output.

It is a block diagram which shows the principal part of the image data output device which shows an example of embodiment of this invention provided with the means to input image data. It is explanatory drawing explaining the main operation | movement of the DMA data transfer by a DMA controller. It is a flowchart which shows the main operation | movement of the image data output device which shows an example of embodiment of this invention.

Explanation of symbols

1 Descriptor area 2 Image memory section (image memory)
3 DMAC (DMA controller)
3a Data transfer control unit 3b Descriptor storage register 4 First path 5 Second path 6 Path switching unit 7 Compression / decompression unit 8 CPU
9 RAM
10 ROM
11 Image data input unit 12 Image data output unit

Claims (1)

An image data input unit for inputting image data;
A memory for storing image data;
A compression / decompression unit that compresses or decompresses image data;
A descriptor area for storing predetermined information for each image data;
A DMA controller for transferring the image data;
A control unit,
When the control unit stores the image data captured from the image data input unit in the memory while being compressed or uncompressed by the compression / decompression unit, the control unit and the position information of the image data on the memory and the compression / non-decompression are stored. The compression determination information is stored in the descriptor area, and when the image data is compressed and divided into a plurality of areas on the memory, the chain destination position information of the divided image data is stored in the descriptor area. Write to the area,
The image data output apparatus, wherein the DMA controller continuously outputs image data based on predetermined information stored in the script area when receiving transfer information from the control unit.

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