JP2007250906A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
【解決手段】基板1上には、ダイボンド剤4を介して第2半導体チップ3が搭載され、更にチップ電極3a及びバンプ5を介してフリップチップボンドにより第1半導体チップ2が搭載されている。第2半導体チップ3の電極3bと、基板1の電極1aに設けられたボール6とはワイヤ7にて接続されている。第2半導体チップ3及びワイヤ7は、封止樹脂9により一体的に封止されているが、第1半導体チップ2は封止樹脂9から完全に露出しており、また、第2半導体チップ3のチップ電極3aの表面(上面)は封止樹脂9から露出しており、ワイヤ7はチップ電極3aより低い位置にある。
【選択図】図1
Description
(付記1)基板上に複数の半導体チップを積層してあり、前記複数の半導体チップの中の最上段の半導体チップが残りの半導体チップ上にフリップチップボンドにより接続されている半導体装置において、前記残りの半導体チップは封止樹脂にて封止され、前記最上段の半導体チップは前記封止樹脂から露出していることを特徴とする半導体装置。
(付記2)前記最上段の半導体チップと接続される前記残りの半導体チップの電極の表面が前記封止樹脂から露出していることを特徴とする付記1記載の半導体装置。
(付記3)前記残りの半導体チップが前記基板とワイヤにて電気的に接続されており、前記ワイヤは、前記最上段の半導体チップと接続される前記残りの半導体チップの電極の表面より低いことを特徴とする付記1または2記載の半導体装置。
(付記5)前記最上段の半導体チップと前記残りの半導体チップとの間に、サーマルバンプを設けてあることを特徴とする付記1乃至4の何れかに記載の半導体装置。
(付記6)前記最上段の半導体チップ裏面に凹凸を付与してあることを特徴とする付記1乃至5の何れかに記載の半導体装置。
(付記8)前記封止樹脂で封止する工程にあって、前記最上段の半導体チップと接続される前記残りの半導体チップの電極の表面を前記封止樹脂から露出させることを特徴とする付記7記載の半導体装置の製造方法。
(付記9)前記ワイヤにて電気的に接続する工程にあって、前記最上段の半導体チップと接続される前記残りの半導体チップの電極の表面より低く前記ワイヤを設けることを特徴とする付記7または8記載の半導体装置の製造方法。
(付記10)前記ワイヤボンド用のボールを前記基板に形成する工程を更に有することを特徴とする付記7乃至9の何れかに記載の半導体装置の製造方法。
1a 電極
2 第1半導体チップ(最上段の半導体チップ)
3 第2半導体チップ(残りの半導体チップ)
3a チップ電極
6 ボール
7 ワイヤ
8 接着剤
9 封止樹脂
11 サーマルバンプ
12 凹凸
Claims (5)
- 基板上に複数の半導体チップを積層してあり、前記複数の半導体チップの中の最上段の半導体チップが残りの半導体チップ上にフリップチップボンドにより接続されている半導体装置において、
前記残りの半導体チップは封止樹脂にて封止され、前記最上段の半導体チップは前記封止樹脂から露出していることを特徴とする半導体装置。 - 前記最上段の半導体チップと接続される前記残りの半導体チップの電極の表面が前記封止樹脂から露出していることを特徴とする請求項1記載の半導体装置。
- 前記残りの半導体チップが前記基板とワイヤにて電気的に接続されており、前記ワイヤは、前記最上段の半導体チップと接続される前記残りの半導体チップの電極の表面より低いことを特徴とする請求項1または2記載の半導体装置。
- 前記フリップチップボンド用の接着剤の材料と、前記封止樹脂の材料とが異なることを特徴とする請求項1乃至3の何れかに記載の半導体装置。
- 基板上に複数の半導体チップを積層してあり、前記複数の半導体チップの中の最上段の半導体チップが残りの半導体チップ上にフリップチップボンドにより接続されている半導体装置を製造する方法において、
基板上に前記残りの半導体チップを積層形成する工程と、
積層形成した前記残りの半導体チップと前記基板とをワイヤにて電気的に接続する工程と、
前記残りの半導体チップ及び前記ワイヤを封止樹脂で封止する工程と、
前記封止樹脂から露出するように、前記最上段の半導体チップを前記残りの半導体チップ上にフリップチップボンドする工程と
を有することを特徴とする半導体装置の製造方法。
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JP4972968B2 JP4972968B2 (ja) | 2012-07-11 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010027848A (ja) * | 2008-07-18 | 2010-02-04 | Nec Electronics Corp | 半導体パッケージ |
JP2011501397A (ja) * | 2007-04-23 | 2011-01-06 | キューファー アセット リミテッド. エル.エル.シー. | 極薄チップパッケージング |
US9190354B2 (en) | 2013-02-04 | 2015-11-17 | Socionext Inc. | Semiconductor device and manufacturing method of the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002170906A (ja) * | 2000-12-04 | 2002-06-14 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法 |
JP2003303847A (ja) * | 2002-04-10 | 2003-10-24 | Kaijo Corp | 半導体構造およびボンディング方法 |
JP2004297071A (ja) * | 2003-03-27 | 2004-10-21 | Stmicroelectronics Inc | 露出されているダイ表面及び補助アタッチメントを具備している集積回路パッケージ |
JP2005101186A (ja) * | 2003-09-24 | 2005-04-14 | Seiko Epson Corp | 積層型半導体集積回路 |
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2006
- 2006-03-16 JP JP2006073414A patent/JP4972968B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002170906A (ja) * | 2000-12-04 | 2002-06-14 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法 |
JP2003303847A (ja) * | 2002-04-10 | 2003-10-24 | Kaijo Corp | 半導体構造およびボンディング方法 |
JP2004297071A (ja) * | 2003-03-27 | 2004-10-21 | Stmicroelectronics Inc | 露出されているダイ表面及び補助アタッチメントを具備している集積回路パッケージ |
JP2005101186A (ja) * | 2003-09-24 | 2005-04-14 | Seiko Epson Corp | 積層型半導体集積回路 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011501397A (ja) * | 2007-04-23 | 2011-01-06 | キューファー アセット リミテッド. エル.エル.シー. | 極薄チップパッケージング |
JP2010027848A (ja) * | 2008-07-18 | 2010-02-04 | Nec Electronics Corp | 半導体パッケージ |
US9190354B2 (en) | 2013-02-04 | 2015-11-17 | Socionext Inc. | Semiconductor device and manufacturing method of the same |
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