JP2007242137A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a circuit scale in a semiconductor integrated circuit with built-in nonvolatile memory capable of electrically erasing and writing data, by shortening the writing and reading period of time with respect to a sub-storage area wherein information of erasing/writing properiety, etc., are stored. <P>SOLUTION: This semiconductor integrated circuit is equipped with: a memory array cell 5 having a main storage area constituted of memory cells of (N-1) rows, M columns, and the sub-storage area constituted of memory cells of one row, M columns; a row decoder 4 for selecting the memory cell of one row; a column decoder 6 for selecting the memory cell of at least one column; a driver 9 for driving a source of a transistor constituting the memory cells of memory cell array 5; an sense amplifier 7 for reading out the data from at least one memory cell; and a plurality of data latch circuits 2, each of them is connected to every adjacent two memory cells of sub-storage area through respective switching transistors. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit including a nonvolatile memory capable of electrically erasing and writing data.

  Non-volatile memories that can electrically erase and write data are EEPROMs that can erase data in units of words, and flash that can erase data in batches or blocks Memory etc. exist. Non-volatile memory can retain stored information even when the power is shut off, so it is important to store programs that control the CPU and microcomputer, and to be used in systems equipped with semiconductor integrated circuits that incorporate non-volatile memory. Used to store data.

  In such a nonvolatile memory, in order to protect programs and important data, erasure and writing of data in a part of storage areas are prohibited. For this purpose, a sub-storage area for storing erasure / write enable / disable information is provided separately from the main storage area for storing general data. Reference is made to the erasure / write enable / disable information stored in the storage area. Based on this erasure / write enable / disable information, it is determined whether the address indicated by the erase or write command is in an area where data should be protected or an area where data can be rewritten, and the address protects the data. When it is in the area to be stored, erasing and writing of data are prohibited.

  As a related technique, Patent Document 1 is provided with a flag bit (lock bit) memory cell for controlling write / erase prohibition / permission for each erase block in order to prevent the loss of important data. In a flash memory, there is a semiconductor non-volatile memory device in which the control circuit is downsized, the characteristics and reliability of the memory cell for the lock bit are the same as those of the data memory cell, and the memory cell for the lock bit can be easily formed. It is disclosed.

  This semiconductor nonvolatile memory device is a semiconductor nonvolatile memory device having a memory array in which a plurality of data storage memory cells are arranged in a matrix, and writing and erasing data in the memory array in units of blocks. A write / erase inhibit memory cell (lock bit memory) that is formed corresponding to each erase block in the memory array and into which data indicating whether write / erase to the block unit is permitted or prohibited is written. Cell) and a control means for writing write / erase inhibit data to the write / erase inhibit memory cell corresponding to the block when a write / erase inhibit command is received for the addressed block. is doing.

However, in this semiconductor nonvolatile memory device, the write / erase prohibition memory cells are provided in a line along the column direction of the data storage memory cells arranged in a two-dimensional matrix. As a result, a plurality of write / erase inhibit memory cells connected to one lock bit line are connected to a write data latch or a dedicated sense amplifier, so that data in these write / erase inhibit memory cells is Can only be written or read one bit at a time, and it takes time to write or read data. In addition, a dedicated sense amplifier is required for the write / erase inhibit memory cell.
Japanese Patent Laid-Open No. 10-188577 (page 1-2, FIG. 1)

  Accordingly, in view of the above points, the present invention provides a sub-memory in which erasure / write enable / disable information and the like are stored in a semiconductor integrated circuit incorporating a nonvolatile memory capable of electrically erasing and writing data. In the case of providing an area, it is an object to reduce the time for writing to and reading from the secondary storage area and to reduce the circuit scale for the secondary storage area.

  In order to solve the above problems, a semiconductor integrated circuit according to one aspect of the present invention is a semiconductor integrated circuit including a nonvolatile memory capable of electrically erasing and writing data, and includes N rows M A main storage area including a plurality of memory cells arranged in a two-dimensional array of columns (N and M are integers of 2 or more) and (N-1) rows and M columns of memory cells and 1 row and M columns And driving a plurality of word lines connected to control gates of a plurality of transistors constituting a memory cell in each row of the memory cell array. A row decoder for selecting one row of memory cells, and a plurality of transistors each connected to the drains of a plurality of transistors constituting the memory cells in each column of the main memory area A column decoder that selects at least one column of memory cells by driving a bit line; a driver that drives sources of a plurality of transistors that respectively configure a plurality of memory cells included in the memory cell array; a row decoder; A sense amplifier that reads data from at least one memory cell selected by the column decoder via at least one bit line, and two memory cells adjacent to each other in the sub storage area via respective switch transistors. And a plurality of connected data latch circuits.

  The semiconductor integrated circuit may further include a precharge circuit for precharging a plurality of data latch circuits prior to reading data from the memory cells in the sub storage area. A control circuit that controls a row decoder, a driver, a switching transistor, and a precharge circuit may be further provided so as to read and latch data of a plurality of bits stored in the memory cells of the storage area. .

  Here, the memory cell array has a main storage area where data can be divided and erased, and the control circuit is a partial storage area of the main storage area based on information read from the sub storage area The erasing and writing of data may be prohibited. Note that the memory cells in the 1st row and the Mth column in the sub storage area are desirably arranged in the outermost column of the memory cell array.

  Further, each of the plurality of data latch circuits includes a first inverter having an input terminal connected to the first memory cell in the secondary storage area and an output terminal connected to the second memory cell in the secondary storage area; A second inverter having an input terminal connected to the second memory cell and an output terminal connected to the first memory cell may be included.

  According to the present invention, in the memory cell array, a sub storage area constituted by memory cells of one row and M columns is provided, and a data latch circuit is provided to each two adjacent memory cells of the sub storage area via the respective switching transistors. Are connected so that access to a plurality of memory cells in the secondary storage area can be performed at one time, so that the time for writing and reading to the secondary storage area is reduced and the circuit scale for the secondary storage area is reduced. It becomes possible.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a block diagram showing a configuration of a nonvolatile memory built in a semiconductor integrated circuit according to an embodiment of the present invention. This semiconductor integrated circuit has a built-in nonvolatile memory capable of electrically erasing and writing data.

  As shown in FIG. 1, the semiconductor integrated circuit includes a control circuit 1, a data latch unit 2, an address buffer 3, an X decoder 4, a memory cell array 5, a Y decoder 6, a sense amplifier 7, an I / O interface 8 and SL (source line) driver 9.

  In the memory cell array 5, a plurality of memory cells from which data is erased, written and read are arranged in a two-dimensional array of N rows and M columns (N and M are integers of 2 or more). In the present embodiment, the (N-1) rows and M columns of memory cells constitute a main storage area 5a, and the outermost column (uppermost column or lowermost column) of 1 row and M columns of memory cells is sub-stored. Region 5b is configured. A plurality of word lines WL, a plurality of bit lines BL, and a plurality of source lines SL are connected to the plurality of memory cells in the main memory area 5a. On the other hand, one word line WL and one source line SL are connected to the plurality of memory cells in the sub storage area 5b.

  In the main storage area 5a, data can be divided and erased in units of one word or one block. In the following, it is assumed that the main storage area 5a can perform data divisional erasure in units of “sectors”. The secondary storage area 5b is used to manage erasability / write enable / disable information in each storage area (one sector unit) in the main storage area 5a and / or a system in which this semiconductor integrated circuit is mounted. Information is stored. For example, process information such as model information and lot numbers, internal voltage trimming information, or information regarding redundant circuits may be stored in the secondary storage area 5b. Hereinafter, the information stored in the secondary storage area 5b is referred to as “system information”.

  Under the control of the control circuit 1, the data latch unit 2 writes system information to the memory cell in the secondary storage area 5b, and reads the system information from the memory cell in the secondary storage area 5b when the power is turned on. In this way, if the nonvolatile memory is configured so that the data latch unit 2 is connected to the memory cells in the secondary storage area 5b provided along the row direction of the memory cell array 5, the memory cells in the secondary storage area 5b are used. There is no need to provide a Y decoder or a dedicated sense amplifier, and a plurality of bits of data can be written to the memory cells of the sub storage area 5b at a time, or a plurality of bits of data can be read from these memory cells at a time. Can do.

  When the address buffer 3 inputs an address designating a memory cell for one word where data is written or read, a sector address designating a sector of the memory cell and a row address designating a row in each sector Are output to the X decoder 4 and a column address designating the column of these memory cells is output to the Y decoder 6.

  The X decoder 4 drives a plurality of word lines WL respectively connected to control gates of a plurality of transistors constituting memory cells in each row of the memory cell array 5 based on the sector address and the row address, thereby Select a memory cell in a row. The Y decoder 6 drives at least one bit line BL connected to the drains of the plurality of transistors constituting the memory cells in each column of the main memory area 5a based on the column address. A memory cell in a column (for example, 8 columns corresponding to 8-bit data) is selected.

The sense amplifier 7 reads data from at least one memory cell (for example, eight memory cells corresponding to 8-bit data) selected by the X decoder 4 and the Y decoder 6 via the corresponding bit line BL. I / O interface 8, in the write mode, supplying the data D _IN input from the outside to the bit line BL, in read mode, and outputs the data D _OUT read by the sense amplifier 7 to the outside. The SL driver 9 applies a predetermined voltage to at least the sources of the transistors constituting the memory cells in the selected row in accordance with erasing, writing, and reading.

  The control circuit 1 controls the X decoder 4, the SL driver 9, and the data latch unit 2 so as to read and latch data of a plurality of bits stored in the memory cell of the secondary storage area 5 b when power is turned on. When the system information stores erasure / write enable / disable information regarding a part of the sector in the main storage area 5a, the control circuit 1 determines a part of the main storage area 5a based on the information. Data erasure and writing in the sector are prohibited.

  FIG. 2 is a cross-sectional view showing a partial structure of the memory cell array shown in FIG. Each memory cell 10 included in the memory cell array is constituted by a transistor including a floating gate 104 and a control gate 107. As shown in FIG. 2, in the P-type substrate 100, an N-type impurity diffusion region 101 serving as a drain and an N-type impurity diffusion region 102 serving as a source are formed. On the P-type substrate 100, a floating gate 104 is formed through an insulating film 103, and a control gate 107 is formed through insulating films 105 and 106.

FIG. 3 is a diagram showing an example of voltages at various parts of the memory cell in writing, reading and erasing.
When writing data to the memory cell, the X decoder 4 applies a first voltage (for example, 2V) to the control gate 107 of the selected memory cell via the word line, and controls the control gate of the unselected memory cell. A low level voltage (for example, 0 V) is applied to 107 via the word line. Further, the Y decoder 6 applies a low level voltage (for example, 0 V) to the drain 101 of the memory cell in which the data “0” is written via the bit line, so that the data “0” is not written (at the time of erasing). A second voltage (for example, 4 V) is applied to the drain 101 of the memory cell (maintaining data “1”) via the bit line. The SL driver 9 applies a high voltage (for example, 12V) to the source 102 of the selected memory cell via the source line.

  At this time, in the memory cell in which data “0” is written, the potential of the floating gate 104 becomes approximately 10 V due to capacitive coupling between the floating gate 104 and the source 102. As a result, some of the electrons flowing from the drain 101 to the source 102 are injected into the floating gate 104 as channel hot electrons. As a result, in the memory cell in which data “0” is written, the floating gate 104 is negatively charged, and the threshold voltage between the control gate and the source is increased.

  When reading the data stored in the memory cell, the X decoder 4 applies a third voltage (for example, 4V) to the control gate 107 of the selected memory cell via the word line, and the unselected memory A low level voltage (for example, 0 V) is applied to the control gate 107 of the cell via the word line. The SL driver 9 applies a low level voltage (for example, 0 V) to the source 102 of the selected memory cell via the source line. At this time, when a current source is connected to the memory cell from the sense amplifier side via the bit line, the bit line becomes 2 V or 0 V, for example, depending on the data write state.

  That is, in the memory cell in which data “0” is written, electrons accumulate in the floating gate 104 and the threshold voltage between the control gate and the source is high, so that the drain current does not flow and the bit line is 2V. Become. On the other hand, in the memory cell in which data “0” is not written, since no electrons are accumulated in the floating gate 104, the threshold voltage between the control gate and the source is low, the drain current flows, and the bit line becomes 0V. In the sense amplifier 7, the data can be identified by comparing the voltage of the bit line with the reference voltage.

  When erasing the data stored in the memory cell, the X decoder 4 applies a high voltage (for example, 15V) to the control gate 107 of the memory cell from which the data is erased via the word line, and the Y decoder 6 applies a low level voltage (for example, 0V) to the drain 101 of the memory cell from which data is erased via the bit line, and the SL driver 9 applies the source line to the source 102 of the memory cell from which data is erased. A low-level voltage (for example, 0 V) is applied via. As a result, a high electric field is generated between the control gate 107 and the floating gate 104, and electrons accumulated in the floating gate 104 are extracted to the control gate 107 side by the tunnel effect, thereby erasing data. The erased state corresponds to data “1”.

FIG. 4 is a circuit diagram showing a detailed configuration of the nonvolatile memory shown in FIG.
As shown in FIG. 4, in the main memory area 5a, the control gates of the transistors constituting the memory cells 10 arranged in a two-dimensional matrix are connected to the X decoder 4 via the word lines WL0, WL1,. The drain is connected to the Y decoder 6 through the bit lines BL0, BL1,..., And the source of the transistor is connected to the SL driver 9 through the source lines SL0, SL1,.

  In the secondary storage area 5b, two memory cells 51 and 52 adjacent in the row direction are used as a pair, and a pair of complementary data Di and Di bar is stored in the pair of memory cells 51 and 52. . The control gates of the transistors constituting the memory cells 51 and 52 are connected to the X decoder 4 through the word line WLS, and the drains are connected to the data latch unit 2 through the drain lines DL0, DL1,. A source is connected to the SL driver 9 via a source line SLS.

In the data latch unit 2, a data latch circuit including a pair of switching transistors 21 and 22 and inverters 23 and 24 corresponding to each pair of memory cells 51 and 52 in the secondary storage area 5b, Charge transistors 25 to 27 are provided. The transistors 21 and 22 are turned on when a high-level switch-on signal SWON is applied to the gates. The transistors 25 to 27 precharge the drain lines DL0, DL1,... To V _DD / 2 when the high-level precharge signal PRE is applied to the gates.

  When data is written to the memory cell in the secondary storage area 5b, the X decoder 4 applies a first voltage (for example, 2V) to the control gates of the memory cells 51 and 52 via the word line WLS, and the SL driver 9 applies a high voltage (for example, 12 V) to the sources of the memory cells 51 and 52 via the source line SLS. Further, when the control circuit 1 sets the switch-on signal SWON to the high level for a predetermined period, the transistors 21 and 22 are turned on. As a result, data Di and Di bar (i = 0, 1,...) Latched by being input to the data latch circuit from the outside are written into the memory cells 51 and 52 of the respective pairs.

  When data is read from the memory cell in the sub storage area 5b, the X decoder 4 applies a third voltage (for example, 4V) to the control gates of the memory cells 51 and 52 via the word line WLS, and the SL driver 9 applies a low-level voltage (for example, 0 V) to the sources of the memory cells 51 and 52 via the source line SLS. Further, the control circuit 1 once sets the precharge signal PRE to a high level to turn on the transistors 25 to 27 and precharge the drain lines DL0, DL1,. The transistors 21 and 22 are turned on by keeping the high level during this period. As a result, data Di and Di bar (i = 0, 1,...) Stored in each pair of memory cells 51 and 52 are read out and latched in the respective latch circuits.

  Next, an operation at the time of startup of the semiconductor integrated circuit according to the embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a circuit diagram showing a configuration of a switch control circuit included in the control circuit, and FIG. 6 is a waveform diagram showing a change in voltage of each part shown in FIG.

As shown in FIG. 5, power supply potentials V _DD and V _SS and a POR (power on reset) signal are supplied to the switch control circuit 1a from the outside of the semiconductor integrated circuit. In the present embodiment, the power supply potential _VSS is assumed to be the ground potential (0 V). The switch control circuit 1a includes a delay element 11 that delays an externally supplied POR signal by a first delay time D1, an AND circuit 12 to which an externally supplied POR signal and a delayed POR1 signal are input, A delay element 13 that delays the POR1 signal output from the delay element 11 by a second delay time D2, and an AND circuit 14 that receives the POR1 signal output from the delay element 11 and the delayed POR2 signal are included. Yes. As the delay elements 11 and 13, gate delays by a plurality of logic circuits (buffers or the like) connected in series may be used. Each of the AND circuits 12 and 14 has one input terminal as an inverting input.

As shown in FIG. 6, when the power supply voltage (V _DD −V _SS = V _DD ) rises when the power is turned on, the POR signal is activated from the low level to the high level. After the first delay time D1 elapses, the POR1 signal changes from low level to high level, and after the second delay time D2 elapses, the POR2 signal changes from low level to high level. The AND circuit 12 generates a 1-pulse precharge signal PRE based on the POR signal and the POR1 signal, and the AND circuit 14 generates a 1-pulse switch-on signal SWON based on the POR1 signal and the POR2 signal.

Referring to FIG. 4 again, the data latch unit 2 receives the precharge signal PRE and the switch-on signal SWON from the control circuit 1. During the period when the precharge signal PRE is at the high level, the transistors 25 to 27 are turned on, and the drain lines DL0, DL1,... Are precharged to V _DD / 2. Thereafter, during a period in which the switch-on signal SWON is at a high level, the switching transistors 21 and 22 are turned on, and the memory cells 51 and 52 in the secondary storage area 5 b are connected to the data latch unit 2.

  In the data latch unit 2, the data latch circuit constituted by the inverters 23 and 24 determines the output level according to the data Di and Di bar stored in the memory cells 51 and 52. That is, since the data Di and Di bar are complementary to each other, a potential difference is generated between the drain voltages of the two transistors constituting the memory cells 51 and 52 according to the data Di and Di bar. Therefore, the data latch circuit latches data stored in the memory cells 51 and 52 based on the potential difference. As described above, since the data is read using the data latch circuit, the data can be read accurately without providing a Y decoder or a sense amplifier for the memory cell in the sub storage area 5b.

  Here, a case will be described in which the system information stored in the secondary storage area 5b is erasable / writeable information on some sectors in the main storage area 5a. When the erasure / write enable / disable information is read from the secondary storage area 5b when the power is turned on, when an erase / write command is input from the outside, the control circuit 1 is based on the read erasure / write enable / disable information. Then, it is determined whether the address specified in the command corresponds to the sector to be protected. If the specified address corresponds to the sector to be protected, the command is reset. As a result, it is possible to protect programs and important data stored in the main storage area 5a.

The block diagram which shows the structure of the non-volatile memory in one Embodiment of this invention. FIG. 2 is a cross-sectional view showing a partial structure of the memory cell array shown in FIG. 1. The figure which shows the example of the voltage of each part of the memory cell in writing, reading, and erasing. The circuit diagram which shows the detailed structure of the non-volatile memory shown in FIG. The circuit diagram which shows the structure of the switch control circuit contained in the control circuit. The wave form diagram which shows the change of the voltage of each part shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Control circuit, 1a Switch control circuit, 2 Data latch part, 3 Address buffer, 4 X decoder, 5 Memory cell array, 5a Main storage area, 5b Sub storage area, 6 Y decoder, 7 Sense amplifier, 8 I / O interface, 9 SL driver, 10, 51, 52 Memory cell, 11, 13 Delay element, 12, 14 AND circuit, 100 P type substrate, 101 Drain, 102 Source, 103, 105, 106 Insulating film, 104 Floating gate, 107 Control gate

Claims (6)

A semiconductor integrated circuit including a nonvolatile memory capable of electrically erasing and writing data,
A main storage area including a plurality of memory cells arranged in a two-dimensional array of N rows and M columns (N and M are integers of 2 or more) and (N-1) rows and M columns of memory cells and 1 A memory cell array having a secondary storage area composed of memory cells in rows and M columns;
A row decoder for selecting one row of memory cells by driving a plurality of word lines each connected to the control gates of a plurality of transistors constituting each row of memory cells in the memory cell array;
A column decoder for selecting at least one column of memory cells by driving a plurality of bit lines respectively connected to the drains of a plurality of transistors constituting the memory cells in each column of the main storage area;
A driver for driving sources of a plurality of transistors respectively constituting a plurality of memory cells included in the memory cell array;
A sense amplifier that reads data from at least one memory cell selected by the row decoder and the column decoder via at least one bit line;
A plurality of data latch circuits each connected to two adjacent memory cells in the sub storage area via respective switching transistors;
A semiconductor integrated circuit comprising:   2. The semiconductor integrated circuit according to claim 1, further comprising a precharge circuit for precharging the plurality of data latch circuits prior to reading data from the memory cells in the sub storage area.   Control for controlling the row decoder, the driver, the switching transistor, and the precharge circuit so that, when power is turned on, a plurality of bits of data stored in the memory cells of the secondary storage area are read and latched. The semiconductor integrated circuit according to claim 2, further comprising a circuit. The memory cell array has a main storage area capable of performing divided erasure of data,
The control circuit prohibits erasing and writing of data in a partial storage area of the main storage area based on information read from the secondary storage area.
The semiconductor integrated circuit according to claim 3.   5. The semiconductor integrated circuit according to claim 1, wherein memory cells of 1 row and M columns in the sub storage area are arranged in an outermost column of the memory cell array. Each of the plurality of data latch circuits has a first inverter having an input terminal connected to the first memory cell in the sub storage area and an output terminal connected to the second memory cell in the sub storage area And a second inverter having an input terminal connected to the second memory cell and an output terminal connected to the first memory cell. Semiconductor integrated circuit.

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