JP2007123349A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be prevented from malfunction and can prevent an increase of parasitic capacity between adjoining control gate electrodes by an inter-electrode insulation film. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 1. A tunnel insulation film 3 is formed on the semiconductor substrate, and a floating gate electrode 11 is formed on the tunnel insulation film. On top of the floating gate electrode, the inter-electrode insulation film 12 is formed. The control gate electrodes 13 are formed on the inter-electrode insulation film, and each of them comprises a first portion formed on the inter-electrode insulation film and a second portion formed on the first portion with a larger width than the first portion in a channel lengthwise direction. Source/drain diffusion regions 15 are formed in the surface of the semiconductor substrate so as to interpose a channel region below the floating gate electrode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, for example, a gate electrode forming method of a flash memory type device.

  As an example of a method for forming a gate electrode of a flash memory device, a method for forming a gate electrode of a NAND flash memory will be described. First, a tunnel insulating film, a polycrystalline silicon film (FG polysilicon film) serving as a floating gate electrode, and a silicon nitride film are sequentially laminated on a semiconductor substrate made of silicon or the like.

  Next, an opening corresponding to a region where the element isolation insulating film is to be formed is formed in the silicon nitride film by a photolithography process. Next, an FG polysilicon film, a tunnel insulating film, and a groove extending inside the semiconductor substrate are formed by etching using the silicon nitride film as a mask. Next, the trench is filled with an insulating film to an appropriate height to form an element isolation insulating film.

  Next, an interelectrode insulating film is formed on the FG polysilicon film and the element isolation insulating film. Next, a polycrystalline silicon film (CG polysilicon film) and a silicon nitride film to be a control gate electrode are formed on the interelectrode insulating film. Next, a BSG (borosilicate glass) film and a TEOS (tetraethoxysilane) film are sequentially formed on the silicon nitride film.

  Next, a photoresist film having a pattern corresponding to the pattern of the gate electrode is formed on the TEOS film by a photolithography process. Next, the TEOS film, the BSG film, and the silicon nitride film are patterned using this photoresist film as a mask. Next, the photoresist film is removed.

  Next, the CG polysilicon film, the interelectrode insulating film, and the FG polysilicon film are patterned by etching such as RIE (Reactive Ion Etching) using the TEOS film, BSG film, and silicon nitride film as a mask. This etching is stopped at the tunnel insulating film.

  In this etching, the TEOS film, the BSG film, and the silicon nitride film as mask materials are large in thickness because of the large consumption. For this reason, the total film thickness of the processed film below the photoresist is as thick as about 1 μm. Therefore, the aspect ratio of the opening formed by patterning in the film to be processed is as large as about 10. As a result, there is a problem that a difference between an etching rate in a wide portion of the opening and an etching rate in a narrow portion becomes large, and there is a large difference in the amount etched in these portions.

  For this reason, since the etching rate is low in the region where the opening is narrow, the FG polysilicon film remains on the element isolation insulating film without being completely removed. This polysilicon causes a short circuit.

  On the other hand, since the etching rate is high in the wide opening region, the tunnel insulating film is also etched, or the element isolation insulating film is significantly etched, so that the upper surface of the element isolation insulating film falls below the tunnel insulating film. As a result, such a malfunction of the semiconductor device occurs.

  In addition, when the RIE method is used, since the aspect ratio of the opening formed in the film to be processed is large, the area of the lower portion of the opening is smaller than that of the upper portion. Therefore, if the process is performed under the condition that a desired area is obtained at the lower part of the opening, the size of the control gate electrode located near the upper part of the opening becomes thinner than the desired shape. Then, the resistance value of the control gate electrode increases.

  To solve such a problem, as disclosed in Patent Document 1, it is conceivable to form a gate insulating film (corresponding to the above-described interelectrode insulating film) and a control gate electrode by damascene. As shown in Patent Document 1, a floating gate electrode having a predetermined pattern, a dummy gate insulating film, and a dummy control gate electrode are formed.

  Next, a sidewall insulating film is formed on the sidewalls of the floating gate electrode, the dummy gate insulating film, and the dummy control gate electrode. Next, by removing the dummy control gate electrode and the dummy gate insulating film, a groove having a side surface made of a side wall insulating film and a bottom surface made of a floating gate electrode is formed on the floating gate electrode. Next, a gate insulating film is formed on the inner surface of the groove. Next, the trench is filled with the metal layer through the gate insulating film.

  With such a structure, a step of forming a high aspect ratio opening between the stacked structures of the gate electrodes is avoided. For this reason, it is suppressed that the dimension of a control gate electrode is thin. Furthermore, the difference in etching rate due to the width of the opening can be reduced. As a result, the tunnel insulating film is excessively etched, the upper surface of the element isolation insulating film is greatly lowered, or polysilicon remains on the element isolation insulating film. Therefore, it is possible to prevent malfunction of the semiconductor device.

However, in the structure of Patent Document 1, a gate insulating film is also formed on the side wall of the control gate electrode. Since the gate insulating film is made of a material having a higher dielectric constant than that of the interlayer insulating film, the parasitic capacitance between the adjacent control gate electrodes is larger than that in the case where there is no gate insulating film on the side wall. As a result, the operating characteristics of the transistor are degraded. This parasitic capacitance will become larger in the future when the gate insulating film is realized by a material having a higher dielectric constant, and the problem caused by this parasitic capacitance becomes more prominent.
Japanese Patent Laid-Open No. 2002-110824

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent the occurrence of malfunction of the semiconductor device and can avoid an increase in parasitic capacitance between adjacent control gate electrodes due to an interelectrode insulating film. To do.

  A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate, a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, and provided on the floating gate electrode. Provided on the interelectrode insulating film, a first portion on the interelectrode insulating film, and provided on the first portion, and having a larger width than the first portion in the channel length direction. And a pair of source / drain diffusion regions formed on the surface of the semiconductor substrate and sandwiching a channel region below the floating gate electrode.

  A semiconductor device according to a second aspect of the present invention includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate in a memory cell region and a select gate region, and the first insulating film in the memory cell region. A floating gate electrode provided; a first inter-electrode insulating film provided on the floating gate electrode; a first portion on the first inter-electrode insulating film provided on the first inter-electrode insulating film; A control gate electrode including a second portion provided on the first portion and having a width larger than the first portion in the channel length direction; and a channel region formed on a surface of the semiconductor substrate and below the floating gate electrode A pair of first source / drain diffusion regions sandwiching the first gate electrode, a first gate electrode provided on the first insulating film in the selection gate region, and the first gate electrode A second inter-electrode insulating film provided on the second inter-electrode insulating film and having an opening penetrating the first surface facing the first gate electrode and the second surface facing the first surface; A second gate electrode including a third portion on the insulating film between the second electrodes and a fourth portion provided on the third portion and having a width larger than the third portion in the channel length direction; and the semiconductor A pair of second source / drain diffusion regions formed on the surface of the substrate and sandwiching a channel region below the first gate electrode.

  A method of manufacturing a semiconductor device according to a third aspect of the present invention includes a step of forming a tunnel insulating film on a semiconductor substrate, a step of forming a floating gate electrode film on the tunnel insulating film, and the floating gate electrode. Forming a first groove extending inside the film, the tunnel insulating film, and the semiconductor substrate, filling the first groove with an element isolation insulating film having an upper surface protruding from the tunnel insulating film, and the floating Forming an interelectrode insulating film covering the surface of the gate electrode film and the surface of the element isolation insulating film; forming a first control gate electrode film on the interelectrode insulating film; and the first control gate electrode Forming a dummy insulating film on the film; the dummy insulating film; the first control gate electrode film; the inter-electrode insulating film; Forming a pattern of a laminated structure of the dummy insulating film, the first control gate electrode film, the inter-electrode insulating film, and the floating gate electrode film intersecting the element isolation insulating film by processing a gate electrode film; A step of filling a region between the patterns of the laminated structure with a buried insulating film, and removing the dummy insulating film in the pattern of the laminated structure buried with the buried insulating film to form a second groove And a step of filling the second groove with a second control gate electrode film.

  According to the present invention, there is provided a semiconductor device capable of preventing the occurrence of malfunction of the semiconductor device and avoiding an increase in parasitic capacitance between adjacent control gate electrodes due to the interelectrode insulating film, and a method for manufacturing the same. it can.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary. In the following description, the NAND flash memory is taken as an example. However, the present embodiment is not limited to this, and it is of course possible to apply this embodiment to a NOR flash memory.

  1, 2 (a), 2 (b), 2 (c), 2 (d) to 16 (a), 16 (b), 16 (c), and 16 (d). A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a plan view showing a part of a semiconductor device according to an embodiment of the present invention. FIG. 2A to FIG. 2D are cross-sectional views schematically showing main parts of a semiconductor device according to an embodiment of the present invention. 2A to 2C show memory cell array regions, and are cross-sectional views taken along lines IIA-IIA, IIB-IIB, and IIC-IIC in FIG. 1, respectively. FIG. 2D is a cross-sectional view of the transistor in the peripheral circuit region.

  As shown in FIG. 1, the semiconductor device has a selection gate region and a memory cell region. The memory cell region is sandwiched between selection gate regions. A control gate electrode 13 extends in the horizontal direction of the drawing. The control gate electrodes 13 are arranged side by side at a distance from each other in the vertical direction of the drawing. The control gate electrode 13 in the memory cell region constitutes a part of the memory cell transistor, and the control gate electrode 13 in the selection gate region constitutes a part of the selection gate transistor.

  A plurality of floating gate electrodes 11 are provided below each control gate electrode 13. The floating gate electrodes 11 are arranged side by side at a distance from each other in the horizontal direction of the drawing.

  As shown in FIGS. 2A to 2D, an element isolation insulating film 2 having an STI (Shallow Trench Isolation) structure is formed on the surface of a semiconductor substrate 1 such as silicon. The element isolation insulating film 2 partitions the element region of the semiconductor substrate 1 and is made of, for example, a silicon oxide film. The element isolation insulating film 2 protrudes from the surface of the semiconductor substrate 1.

  A tunnel insulating film 3 made of, for example, a silicon oxide film is provided on the surface of the semiconductor substrate 1 in the element region. On the tunnel insulating film 3, a plurality of stacked gate electrode structures that are adjacent to each other are provided. Each stacked gate electrode structure has a pattern as shown in FIG. Each stacked gate electrode structure includes a floating gate electrode 11, an interelectrode insulating film 12, a control gate electrode 13, and the like.

  In the stacked gate electrode structure, a floating gate electrode 11 is provided on the tunnel insulating film 3. The floating gate electrode 11 is made of, for example, conductive polysilicon.

  An interelectrode insulating film 12 is provided on the floating gate electrode 11. The interelectrode insulating film 12 is, for example, a silicon oxide film, a silicon nitride film, a laminated film (ONO film) of a silicon oxide film, and a laminated film of a silicon nitride film, a silicon oxide film, a silicon nitride film, a silicon oxide film, and a silicon nitride film. It is comprised from the film | membrane (NONON film | membrane) and the dielectric film containing aluminum or hafnium.

  In the selection gate region and the peripheral circuit region, the interelectrode insulating film 12 is provided only above the end portion of the floating gate electrode 11 along the channel length direction. That is, the interelectrode insulating film 12 has an opening 12a that penetrates the upper surface and the lower surface.

  A control gate electrode 13 is provided on the interelectrode insulating film 12. The control gate electrode 13 is composed of, for example, conductive polysilicon, tungsten, tungsten silicide, and a laminated film thereof. The control gate electrode 13 includes a first portion 13a on the interelectrode insulating film 12 and a second portion 13b on the first portion 13a. In the selection gate region and the peripheral circuit region, the first portion 13a of the control gate electrode 13 has an opening 24a at the same position as the interelectrode insulating film 12, and a part of the second portion 13b of the control gate electrode 13 is The interelectrode insulating film 12 and the control gate electrode 13 are embedded in the openings 12a and 24a in the first portion 13a.

  In each stacked gate electrode structure, the floating gate electrode 11, the interelectrode insulating film 12, and the first portion 13a of the control gate electrode 13 have substantially the same dimension, that is, substantially the same width in the channel length direction. On the other hand, the dimension, that is, the width of the second portion 13b of the control gate electrode 13a is larger than the dimension (width) of the first portion 13a of the control gate electrode 13.

  A silicide film 14 is formed on the upper surface of the control gate electrode 13. The silicide film 14 is made of, for example, nickel silicide or cobalt silicide.

  A source / drain diffusion region 15 is formed on the surface of semiconductor substrate 1 so as to sandwich a channel region below floating gate electrode 11. In the memory cell array region, adjacent source / drain diffusion regions 15 are connected.

  A spacer 16 is formed on the side wall of the laminated structure including the floating gate electrode 11, the interelectrode insulating film 12, the control gate electrode 13, and the silicide portion 14. The spacers 16 are filled with an interlayer insulating film 17. The interlayer insulating film 17 is made of, for example, TEOS or BSG.

  Next, regarding the method for manufacturing the semiconductor device shown in FIGS. 1 and 2A to 2D, FIGS. 3A, 3B, 3C, and 3D are used. This will be described with reference to FIGS. 16 (a), 16 (b), 16 (c), and 16 (d).

  2A to 13A, FIG. 15A, and FIG. 16A sequentially show a manufacturing process of the structure of FIG.

  2 (b) to 13 (b), FIG. 15 (b), and FIG. 16 (b) sequentially show the manufacturing process of the structure of FIG. 2 (b).

  2 (c) to 13 (c), 15 (c), and 16 (c) sequentially show manufacturing steps of the structure of FIG. 2 (c).

  2D to 13D, FIG. 15D, and FIG. 16D sequentially show a manufacturing process of the structure of FIG.

  As shown in FIGS. 3A to 3D, a tunnel insulating film 3 is formed on the surface of the semiconductor substrate 1 by, for example, a thermal oxidation method. Next, a material film (FG material film) 21 to be the floating gate electrode 11 is formed on the tunnel insulating film 3 by, eg, CVD (Chemical Vapor Deposition). Next, a silicon nitride film 22 is formed on the FG material film 21 by, eg, CVD.

  Next, a photoresist film (not shown) is formed on the silicon nitride film 22. Next, an opening is formed in a region where the element isolation insulating film 2 is to be formed in the photoresist film, for example, by a lithography process. Next, the silicon nitride film 22 is etched by anisotropic etching such as RIE using the photoresist film as a mask. As a result, an opening is formed in a region where the element isolation insulating film 2 is to be formed in the silicon nitride film 22. Thereafter, the photoresist film is removed.

  Next, as shown in FIGS. 4A to 4D, the FG material film 21, the tunnel insulating film 3, and the semiconductor are formed by anisotropic etching such as RIE using the silicon nitride film 22 as a mask. The substrate 1 is etched. As a result, the FG material film 21, the tunnel insulating film 3, and the trench 23 extending inside the semiconductor substrate 1 are formed. Thereafter, the photoresist film is removed by, for example, ashing.

  Next, as shown in FIGS. 5A to 5D, a film to be the element isolation insulating film 2 is deposited on the entire surface of the structure obtained by the steps so far by, eg, CVD. As a result, the trench 23 is filled with the element isolation insulating film 2. Next, by using, for example, a CMP (Chemical Mechanical Polishing) method using the silicon nitride film 22 as a stopper, the excess element isolation insulating film 2 on the silicon nitride film 22 is removed.

  Next, as shown in FIGS. 6A to 6D, the upper surface of the element isolation insulating film 2 in the trench 23 is set to an appropriate height, for example, about 40 nm from the tunnel insulating film 3, for example, by RIE. It is etched back to a high position.

  Next, as shown in FIGS. 7A to 7D, the silicon nitride film 22 is removed by, for example, hot phosphoric acid. Next, the interelectrode insulating film 12 is formed on the entire surface of the structure obtained by the steps so far, for example, by the CVD method. As a result, the interelectrode insulating film 12 is formed on the upper surface of the FG material film 21 and the side surface exposed above the element isolation insulating film 2 and on the upper surface of the element isolation insulating film 2.

  Next, as shown in FIGS. 8A to 8D, a material film (CG1 material) that becomes the first portion 13a of the control gate electrode 13 is formed on the entire surface of the interelectrode insulating film 12 by, eg, CVD. Film) 24 is formed. At this time, the CG1 material film 24 is buried above the element isolation insulating film 2 in a region between the FG material films 21 via the interelectrode insulating film 12.

  Next, as shown in FIGS. 9A to 9D, the top surface of the CG1 material film 24 is etched to the vicinity of the interface with the interelectrode insulating film 12 above the FG material film 21 by, for example, RIE. Back. When the dummy insulating film 31 on the CG1 material film 24 is removed in a later step, the CG1 material film 24 above the FG material film 21 and the interelectrode insulating film 12 below the CG1 material film 24 and further below It has a function of protecting the element isolation insulating film 2. On the other hand, when etching the laminated structure such as the CG1 material film 24, the interelectrode insulating film 12, and the FG material film 21 in a later step, the aspect ratio of the region (opening) formed between the laminated structures is reduced. In view of this, it is preferable that the CG1 material film 24 above the FG material film 21 is thin. The upper surface of the CG1 material film 24 is set at an appropriate position in consideration of the above factors, and as a specific example, the upper surface of the CG1 material film 24 can be positioned about 20 to 40 nm above the interelectrode insulating film 12.

  Next, as shown in FIGS. 10A to 10D, a mask material 25 made of, for example, BSG is formed on the CG1 material film 24. Next, an opening 26 is formed in the mask material 25 above the region where the opening 12 a of the interelectrode insulating film 12 is to be formed. Next, using the mask material 25 as a mask, the CG1 material film 24 and the interelectrode insulating film 12 are etched by anisotropic etching such as RIE. As a result, openings 12a and 24a are formed in the interelectrode insulating film 12 and the CG1 material film 24, respectively.

  Next, after removing the mask material 25, a dummy insulating film 31 is formed on the entire surface of the CG1 material film 24 as shown in FIGS. 11 (a) to 11 (d). At this time, the dummy insulating film 31 is embedded in the openings 12a and 24a. The dummy insulating film 31 has a function as a dummy electrode that fills the region where the control gate electrode 13 is to be formed. As the dummy insulating film 31, for example, a silicon nitride film can be used.

  Next, mask materials 32 and 33 are formed on the entire surface of the silicon nitride film 31 by, eg, CVD. For example, BSG and TEOS can be used as the mask materials 32 and 33, respectively.

  As described above, the thickness of the CG1 material film 24 above the FG material film 21 is kept as small as possible, and is thinner than the conventional one. Therefore, even if the tunnel insulating film 3, the FG material film 21, the interelectrode insulating film 12, the dummy insulating film 31, and the mask materials 32 and 33 have the same thickness as the conventional one, the FG material film 21 to the mask material 33 are used. The total thickness up to can be kept smaller than before.

  Next, a photoresist film 34 is formed on the mask material 33. Next, a pattern remaining in the regions where the floating gate electrode 11 and the control gate electrode 13 are to be formed is formed in the photoresist film 34 using a lithography process.

  Next, as shown in FIGS. 12A to 12D, mask materials 33 and 32 and a dummy insulating film 31 are formed using the photoresist film 34 as a mask by using anisotropic etching such as RIE. Is etched. Next, the photoresist film 34 is removed by, for example, ashing.

  Next, as shown in FIGS. 13A to 13D, the CG1 material film 24 and the electrodes are formed by anisotropic etching such as the RIE method using the mask materials 33 and 32 and the dummy insulating film 31 as a mask. The interlayer insulating film 12 and the FG material film 21 are etched. As a result, the first portion 13a of the control gate electrode 13 and the floating gate electrode 11 are formed. During this etching, much of the mask material 33 is consumed and lost.

  As described above, the total thickness from the FG material film 21 to the mask material 33 is smaller than the conventional one. Therefore, the etching rate according to the width of the region between the patterns of the laminated structure of the FG material film 21, the interelectrode insulating film 12, the first portion 13a of the control gate electrode 13, the dummy insulating film 31, and the mask material 32 is changed. The difference decreases. As a result, as shown in FIG. 14, the FG material film 21, the interelectrode insulating film 12, the first portion 13 a of the control gate electrode 13, the dummy insulating film 31, and the mask material 32 have a laminated structure pattern. Even if there is a difference between wide and narrow, the FG material film 21 remains on the tunnel insulating film 3 due to insufficient etching amount, or the element isolation insulating film 2 and the tunnel insulating film 3 are etched due to excessive etching amount. This can be suppressed.

  14 shows a stacked structure corresponding to two control gate electrodes 13 including a selection gate region in one memory cell block region formed by the memory cell region and the selection gate region shown in FIG. And a pattern portion of a laminated structure corresponding to the control gate electrode 13 of the selection gate region in another memory cell block region adjacent to this memory cell block region. In the figure, the region where the pattern of the laminated structure is wide is not shown. This corresponds to a region where the bit line or the source line contacts the source / drain diffusion region.

  Next, the mask material 32 is removed by, for example, vapor phase hydrofluoric acid.

  Next, as shown in FIGS. 15A to 15D, a buried insulating film 35 is formed on the entire surface of the structure obtained by the steps so far by, eg, CVD. As a result, the embedded insulating film 35 fills the laminated gate pattern between the floating gate electrode 11, the interelectrode insulating film 12, the first portion 13 a of the control gate electrode 13, and the dummy insulating film 31. Next, the excess buried insulating film 35 on the dummy insulating film 31 is removed by, for example, CMP using the dummy insulating film 31 as a stopper.

  Next, as shown in FIGS. 16A to 16D, the dummy insulating film 31 is removed by, for example, wet etching. As a result, a trench 36 for the second portion 13 b of the control gate electrode 13 is formed in the buried insulating film 35. Next, the width of the groove 36 in the channel length direction is widened by wet etching using, for example, hydrofluoric acid.

  The shape of the trench 36 before the width is increased in the steps of FIGS. 16A to 16D is determined by the shape of the dummy insulating film 31. The shape of the dummy insulating film 31 is determined by etching in the steps of FIGS. 12A to 12D. In this etching, even if anisotropic etching is used, the lower diameter of the openings formed in the dummy insulating film 31, the CG1 material film 24, the interelectrode insulating film 12, and the FG material film 21 is larger than the upper diameter. Somewhat smaller. For this reason, the lower part of the patterned dummy insulating film 31 is somewhat thicker than the upper part. Therefore, in the present embodiment, the width of the groove 36 is increased as described above. As a result, it is possible to avoid the upper portion of the second portion 13b of the control gate electrode 13 which is formed in a process described later and whose shape is defined by the width of the groove 36 from being thinner than the lower portion.

  Next, as shown in FIGS. 2A to 2D, the material film of the second portion 13b of the control gate electrode 13 is formed on the entire surface of the structure obtained by the steps so far by, eg, CVD. CG2 material film) is formed. As a result, the groove 36 is filled with the CG2 material film. Next, the excess CG2 material film on the buried insulating film 35 is removed by, for example, CMP using the buried insulating film 35 as a stopper. As a result, the second portion 13b of the control gate electrode 13 is formed.

  Next, the upper part of the control gate electrode 13 is processed into the silicide film 14. Next, the buried insulating film 35 is removed. Next, the spacer 16 and the source / drain diffusion region 15 are formed by a known process. Next, a region between the spacers 16 is filled with an interlayer insulating film 17. It is also possible to form the source / drain diffusion region 15 between the step of FIG. 13 and the step of FIG. 15 and use the buried insulating film 35 as an interlayer insulating film as it is.

  According to the semiconductor device of one embodiment of the present invention, the second portion of the control gate electrode 13 is formed after the tunnel insulating film 3, the floating gate electrode 11, the interelectrode insulating film 12, and the first portion 13 a of the control gate electrode 13 are formed. The portion 13b is formed by damascene. The first portion 13a of the control gate electrode 13 is thinned prior to forming a pattern of a laminated structure of the floating gate electrode 11, the interelectrode insulating film 12, the control gate electrode 13, the dummy insulating film 31, and the mask material 32. Is done. For this reason, the aspect ratio of the area | region between the patterns of a laminated structure can be reduced in the case of patterning of a laminated structure. Therefore, variation in etching amount due to the width of the region between the patterns of the stacked structure can be reduced.

  Further, since the second portion 13b of the control gate electrode 13 is formed by damascene, the width of the groove 36 can be increased prior to embedding the groove 36 for the second portion 13b. Therefore, even if the upper width of the dummy insulating film 31 becomes smaller than the lower width during patterning, the width difference between the upper and lower portions of the trench 36 defined by the shape of the dummy insulating film 31 is reduced. In addition to canceling, the control gate electrode 13 having a lower resistance can be formed.

  Further, as described above, the cross-sectional area of the upper portion of the control gate electrode 13 can be increased as compared with the conventional case. For this reason, the resistance value between the contact connected to the control gate electrode 13 and the control gate electrode 13 can be made smaller than when the control gate electrode 13 is formed by patterning as in the prior art.

  Further, the interelectrode insulating film 12 is not formed by damascene. When the interelectrode insulating film is formed by damascene, an interelectrode insulating film is also formed on the side wall of the control gate electrode, leading to an increase in parasitic capacitance between adjacent control gate electrodes. Further, when the interelectrode insulating film is formed by damascene, when the dummy gate insulating film in the pattern of the laminated structure is removed, the upper surface of the element isolation insulating film may drop between the adjacent floating gate electrodes. In addition, it is difficult to form an opening in the interelectrode insulating film of the transistors in the select gate region and the peripheral circuit region (see FIGS. 2C and 2D) as described below. That is, in this case, it is necessary to form an interelectrode insulating film on the inner surface of the groove for the interelectrode insulating film and the control gate electrode, and then to form an opening in the interelectrode insulating film at the bottom of the groove. Forming the opening requires a step of forming the opening at the bottom of the groove having a small aspect ratio. This step is difficult to perform due to the difficulty in aligning the mask. On the other hand, according to the present embodiment, the opening 12a can be formed in the interelectrode insulating film 12 without using the step of forming the opening at the bottom of the groove.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive various modifications, and it is understood that these modifications belong to the scope of the present invention.

1 is a plan view showing a part of a semiconductor device according to an embodiment of the present invention. 1 is a cross-sectional view schematically showing main parts of a semiconductor device according to an embodiment of the present invention. Sectional drawing which shows a part of manufacturing process of the structure of FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. FIG. 11 is a cross-sectional view showing a step following FIG. 10. Sectional drawing which shows the process following FIG. Sectional drawing which shows the process following FIG. Sectional drawing which shows the other part of the structure obtained in the process of FIG. Sectional drawing which shows the process of following FIG. FIG. 16 is a cross-sectional view showing a step following FIG. 15.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... Tunnel insulating film, 11 ... Floating gate electrode, 12 ... Interelectrode insulating film, 12a ... Opening, 13 ... Control gate electrode, 13a ... 1st part, 13b ... 1st 2 parts, 14 ... silicide film, 15 ... source / drain diffusion region, 16 ... spacer, 17 ... interlayer insulating film.

Claims (5)

A semiconductor substrate;
A tunnel insulating film provided on the semiconductor substrate;
A floating gate electrode provided on the tunnel insulating film;
An interelectrode insulating film provided on the floating gate electrode;
A control provided on the interelectrode insulating film, and including a first portion on the interelectrode insulating film and a second portion provided on the first portion and having a width larger than the first portion in the channel length direction. A gate electrode;
A pair of source / drain diffusion regions formed on the surface of the semiconductor substrate and sandwiching a channel region below the floating gate electrode;
A semiconductor device comprising: A semiconductor substrate;
A first insulating film provided on the semiconductor substrate in the memory cell region and the select gate region;
A floating gate electrode provided on the first insulating film in the memory cell region;
A first interelectrode insulating film provided on the floating gate electrode;
A first portion on the first inter-electrode insulating film; a first portion on the first inter-electrode insulating film; and a second portion provided on the first portion and having a width larger than the first portion in the channel length direction. A control gate electrode including
A pair of first source / drain diffusion regions formed on the surface of the semiconductor substrate and sandwiching a channel region below the floating gate electrode;
A first gate electrode provided on the first insulating film in the select gate region;
A second inter-electrode insulating film provided on the first gate electrode and having an opening penetrating a first surface facing the first gate electrode and a second surface facing the first surface;
A fourth portion provided on the second interelectrode insulating film, provided on the third portion on the second interelectrode insulating film and on the third portion, and having a larger width than the third portion in the channel length direction; A second gate electrode comprising:
A pair of second source / drain diffusion regions formed on the surface of the semiconductor substrate and sandwiching a channel region below the first gate electrode;
A semiconductor device comprising: Forming a tunnel insulating film on the semiconductor substrate;
Forming a floating gate electrode film on the tunnel insulating film;
Forming the first trench over the floating gate electrode film, the tunnel insulating film, and the semiconductor substrate;
Filling the first trench with an element isolation insulating film whose upper surface protrudes from the tunnel insulating film;
Forming an interelectrode insulating film covering the surface of the floating gate electrode film and the surface of the element isolation insulating film;
Forming a first control gate electrode film on the interelectrode insulating film;
Forming a dummy insulating film on the first control gate electrode film;
Processing the dummy insulating film, the first control gate electrode film, the interelectrode insulating film, the floating gate electrode film, the dummy insulating film intersecting the element isolation insulating film, the first control gate electrode film, Forming a pattern of a laminated structure of an interelectrode insulating film and the floating gate electrode film;
Burying a region between the patterns of the laminated structure with a buried insulating film;
Forming a second groove by removing the dummy insulating film in the pattern of the laminated structure embedded with the embedded insulating film;
Burying the second trench with a second control gate electrode film;
A method for manufacturing a semiconductor device, comprising:   4. The semiconductor device according to claim 3, further comprising a step of retreating the upper surface of the first control gate electrode film to the vicinity of the inter-electrode insulating film before the step of forming the dummy insulating film. Manufacturing method.   4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of expanding a width of the second groove in a channel length direction before the step of filling with the second control gate electrode film.

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