JP2007110155A - Ic memory and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an IC (Integrated circuit) memory and a semiconductor device in which an injection defect can be eliminated and chip costs can be reduced. <P>SOLUTION: A multi-chip type IC memory formed from a plurality of semiconductor chips comprises: at least one first chip forming a memory circuit section including a memory cell array on a semiconductor substrate; and a second chip forming, on the semiconductor substrate, an input circuit section to which a signal is inputted from the outside, an output circuit section which outputs a signal to the outside, and a power supply circuit section which supplies power to internal circuits, wherein said first chip is stuck on the second chip and connected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory, and more particularly to a multi-chip IC memory in which a semiconductor memory is configured using a plurality of semiconductor chips.

  FIG. 7 is a schematic block diagram showing a circuit example of an IC memory forming a conventional 8M × 32 DRAM. In FIG. 7, an IC memory 150 includes a memory cell array 151, a row decoder 152, a column decoder / amplifier circuit 153, a predecoder 154, an input / output circuit 155, a power supply circuit 156, a control circuit 157, and an input buffer. 158 and an address buffer 159. The input / output circuit 155 inputs / outputs data from the outside, and the power supply circuit 156 generates a voltage for each internal circuit, a power-on reset signal, and the like based on the power supplied from the outside.

  The control circuit 157 controls the row decoder 152, column decoder / amplifier circuit 153, predecoder 154, input / output circuit 155, power supply circuit 156, and address buffer 159. The input buffer 158 receives external control signals such as a write enable signal and a chip enable signal, and the address buffer 159 receives external address data. The column decoder and amplifier circuit 153 includes a sense amplifier, a column decoder, an I / O switch transistor, a preamplifier, and the like.

  FIG. 8 is a diagram showing a layout of each circuit when the DRAM shown in FIG. 7 is formed on one chip. In FIG. 8, a power supply circuit 156 is formed in the portions 201 and 202 in the chip 200, a control circuit 157 and an input buffer 158 are formed in the portion 203, and the memory cell array 151 and the portions 204 to 207 are formed. A row decoder 152, a column decoder / amplifier circuit 153, and a predecoder 154 are formed, and an input / output circuit 155 and an address buffer 159 are formed at portions 208 and 209, respectively.

  9 is a diagram showing an example of pin arrangement of the IC memory 150 formed by the chip 200 shown in FIG. 8, and FIG. 10 is a schematic diagram showing an example of the structure in the IC package shown in FIG. It is. In FIG. 10, in the IC memory 150, each pad 301 formed on the chip 200 is electrically connected to a predetermined portion of the lead frame 303 by a bonding wire 302.

Although different from the present invention, for example, an integration in which a plurality of single 4M bit memories are bonded to a substrate having pads and the pads formed on the substrate are electrically connected to the lead frame. There was a circuit module (for example, refer to Patent Document 1).
JP-A-3-2003360

An input protection circuit is provided at the input of the input buffer 158, the address buffer 159, etc., and the input protection circuit is formed with an element for absorbing surge (hereinafter referred to as a field transistor).
FIG. 11 is a cross-sectional view of a chip showing an example of the structure of a field transistor. The field transistor 400 is formed by forming an isolation oxide film region 404 between two n + diffusion regions 402 and 403 formed on a p-type silicon substrate 401. The n + diffusion region 402 is connected to the aluminum wiring 406 formed in the insulating film 405 to form the source of the n-channel MOS transistor, and the n + diffusion region 403 is connected to the aluminum wiring 407 formed in the insulating film 405. Thus, the drain of the n-channel MOS transistor is formed.

  The drain of the field transistor 400 is connected to the Vss terminal shown in FIGS. 7 and 9, and when a signal in which a large under-short occurs in the source of the field transistor 400 is input to the p-type silicon substrate 401. Electrons are injected. For example, in the case of a system operating at high speed, an under-short of −3 to −4 V occurs, and the p-type silicon substrate 401 is biased to about Vss or about −1 to −2 V. Therefore, n + that forms the source of the field transistor 400 The diffusion region 402 and the p-type silicon substrate 400 are forward biased, and electrons are injected into the p-type silicon substrate 400.

  Since the DRAM shown in FIGS. 7 to 11 is formed by one chip, the n + diffusion region 402 and the memory cell array 151 forming the source of the field transistor 400 are formed on the same substrate. For this reason, there has been a problem that a so-called injection failure occurs in which the electrons injected from the n + diffusion region 402 reach the memory cell array 151 and destroy the data stored in the memory cells.

  Further, when the 8M × 32 DRAM is formed by one chip as described above, the chip size is about 300 mm 2. However, when the chip size exceeds 100 mm 2, there is a problem that the yield is drastically decreased and the chip cost is increased.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain an IC memory and a semiconductor device that can eliminate the above-mentioned injection failure and reduce the chip cost. .

  The IC memory according to the first invention is a multi-chip type IC memory formed of a plurality of semiconductor chips, and includes at least one first chip in which a memory circuit portion having a memory cell array is formed on a semiconductor substrate, and an external An input circuit unit to which a signal is input, an output circuit unit to output a signal to the outside, and a second chip in which a power supply circuit unit for supplying power to each internal circuit unit is formed on a semiconductor substrate. The chip is bonded and connected on the second chip.

  An IC memory according to a second invention is the IC memory according to the first invention, wherein the first chip is connected to the second chip using bumps.

  The IC memory according to the third invention is an element for performing surge absorption in the first or second invention, wherein an isolation oxide film region is formed between two n + diffusion regions formed on a semiconductor substrate. Are formed on the second chip.

  In the IC memory according to the fourth invention, in the first to third inventions, the thickness of the semiconductor element formed on the first chip is reduced, and the thickness of the semiconductor element formed on the second chip is reduced. Is formed thicker.

  The IC memory according to the fifth invention is the IC memory according to the fourth invention, wherein the gate oxide film of the transistor formed on the first chip is thinned to reduce the gate oxide film of the transistor formed on the second chip. This is formed by increasing the thickness.

  The IC memory according to a sixth aspect of the present invention is the first to fifth aspects, wherein the wiring layer formed on the first chip is formed as a thin film and the wiring layer formed on the second chip is formed as a thick film. To form.

  An IC memory according to a seventh aspect of the present invention is the IC memory according to the first to sixth aspects, wherein a decoupling capacitor is formed in an empty area of the second chip.

  According to an eighth aspect of the present invention, there is provided a semiconductor device comprising: a multichip IC memory formed of a plurality of semiconductor chips; and at least one first chip having a memory circuit portion having a memory cell array formed on a semiconductor substrate; An input circuit unit to which a signal is input, an output circuit unit to output a signal to the outside, and a second chip in which a power supply circuit unit for supplying power to each internal circuit unit is formed on a semiconductor substrate. The chip is bonded and connected on the second chip, and the thickness of the gate oxide film of the transistor formed on the first chip is thinner than the thickness of the gate oxide film of the transistor formed on the second chip. Is.

  According to a ninth aspect of the present invention, in the eighth aspect, the film thickness of the wiring layer connecting the circuits formed on the first chip connects between the circuits formed on the second chip. It is thinner than the thickness of the wiring layer.

  A semiconductor device according to a tenth aspect of the present invention is the semiconductor device according to the eighth or ninth aspect, wherein a decoupling capacitor is formed in an empty area of the second chip.

  According to a first aspect of the present invention, there is provided an IC memory comprising: at least one first chip in which a memory circuit unit having a memory cell array is formed on a semiconductor substrate; an input circuit unit to which a signal is input from the outside; and an output that outputs a signal to the outside The circuit portion and the power supply circuit portion for supplying power to each internal circuit are bonded and connected to the second chip formed on the semiconductor substrate. For this reason, what was conventionally laid out two-dimensionally on the same plane can be connected three-dimensionally because the chips are stacked and connected, and the length of the signal line connecting each part can be increased. This is advantageous in speeding up the operation. In addition, by forming a highly integrated memory circuit portion that is prone to manufacturing defects on the first chip and reducing the chip size of the first chip to 100 mm 2 or less, the yield can be improved and the chip cost can be reduced. Can be planned.

  In the IC memory according to the second invention, specifically, in the first invention, the first chip is connected to the second chip using bumps. For this reason, what was conventionally laid out two-dimensionally on the same plane can be laid out three-dimensionally by stacking the chips and connecting them with bumps. This is advantageous in speeding up the operation. In addition, by forming a highly integrated memory circuit portion that is prone to manufacturing defects on the first chip and reducing the chip size of the first chip to 100 mm 2 or less, the yield can be improved and the chip cost can be reduced. Can be planned.

  An IC memory according to a third invention is an element for performing surge absorption, wherein an isolation oxide film region is formed between two n + diffusion regions formed on a semiconductor substrate in the first or second invention. Was formed on the second chip. Therefore, since the memory cell array is formed on the first chip and the element for absorbing the surge is formed on the second chip, the injection failure occurring in the memory cell array can be prevented.

  In the IC memory according to the fourth invention, in the first to third inventions, the thickness of the semiconductor element formed on the first chip is reduced, and the thickness of the semiconductor element formed on the second chip is increased. From this, the manufacturing process of the first chip and the second chip can be made different, and by increasing the film pressure of the semiconductor element formed on the second chip where a surge or the like may be input, It is possible to avoid a surge breakdown voltage drop at the input / output unit that occurs when the circuit is changed.

  The IC memory according to the fifth invention is the transistor memory according to the fourth invention, specifically, the transistor gate oxide formed on the second chip by reducing the thickness of the gate oxide film of the transistor formed on the first chip. The film thickness was increased. For this reason, the manufacturing process of the first chip and the second chip can be made different, and the transistor formed on the second chip that may receive a surge or the like uses a thick gate oxide film. As the transistor formed on the first chip, a transistor suitable for thinning the gate oxide film is used. By doing in this way, it is possible to avoid a surge breakdown voltage drop at the input / output section that occurs when miniaturization occurs.

  In the IC memory according to the sixth invention, in the first to fifth inventions, the wiring layer formed on the first chip is formed with a thin film, and the wiring layer formed on the second chip is formed with a thick film. From this, the manufacturing process of the first chip and the second chip can be made separately, the first chip is formed with a thin film suitable for miniaturization, and the second chip does not need to be miniaturized very much. Therefore, it can be easily formed with a thick film. For this reason, the resistance value of the wiring of the first chip can be reduced, and the wiring connecting the circuit formed at a distant place is formed on the first chip, and the circuit formed at a close place is connected. By forming the wiring on the second chip, the speed of the circuit can be increased.

  In the IC memory according to the seventh invention, in the first to sixth inventions, a decoupling capacitor is formed in an empty area of the second chip where no element is formed. Therefore, compared with the conventional case, the above-mentioned empty area can be formed larger in the second chip, so that a decoupling capacitor having a larger capacity than that of the conventional one can be formed. The number of capacitors can be reduced.

According to an eighth aspect of the present invention, there is provided a semiconductor device comprising: at least one first chip in which a memory circuit unit having a memory cell array is formed on a semiconductor substrate; an input circuit unit to which a signal is input from the outside; and an output that outputs a signal to the outside The circuit portion and the power supply circuit portion for supplying power to each internal circuit are bonded and connected to the second chip formed on the semiconductor substrate. For this reason, what was conventionally laid out two-dimensionally on the same plane can be connected three-dimensionally because the chips are stacked and connected, and the length of the signal line connecting each part can be increased. This is advantageous in speeding up the operation. In addition, by forming a highly integrated memory circuit portion that is likely to cause manufacturing defects on the first chip and reducing the chip size of the first chip to 100 mm ² or less, the yield can be improved and the chip cost is reduced. Can be achieved. Further, the thickness of the gate oxide film of the transistor formed on the first chip is reduced, and the thickness of the transistor gate oxide film formed on the second chip is increased. For this reason, the manufacturing process of the first chip and the second chip can be made different, and the transistor formed on the second chip that may receive a surge or the like uses a thick gate oxide film. As the transistor formed on the first chip, a transistor suitable for thinning the gate oxide film is used. By doing in this way, it is possible to avoid a surge breakdown voltage drop at the input / output section that occurs when miniaturization occurs.

  In a semiconductor device according to a ninth aspect based on the eighth aspect, the film thickness of the wiring layer connecting the circuits formed on the first chip is equal to that of the wiring layer connecting the circuits formed on the second chip. It was made thinner than the film thickness. From this, the manufacturing process of the first chip and the second chip can be made separately, the first chip is formed with a thin film suitable for miniaturization, and the second chip does not need to be miniaturized very much. Therefore, it can be easily formed with a thick film. For this reason, the resistance value of the wiring of the first chip can be reduced, and the wiring connecting the circuit formed at a distant place is formed on the first chip, and the circuit formed at a close place is connected. By forming the wiring on the second chip, the speed of the circuit can be increased.

  A semiconductor device according to a tenth aspect of the present invention is the semiconductor device according to the eighth or ninth aspect, wherein a decoupling capacitor is formed in an empty area of the second chip where no element is formed. Therefore, compared with the conventional case, the above-mentioned empty area can be formed larger in the second chip, so that a decoupling capacitor having a larger capacity than that of the conventional one can be formed. The number of capacitors can be reduced.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a circuit example of a multichip IC memory according to the first embodiment of the present invention.

  In FIG. 1, an IC memory 1 includes memory cell arrays 2a, 2b, 2c, 2d, row decoders 3a, 3b, 3c, 3d, column decoders and amplifier circuits 4a, 4b, 4c, 4d, predecoders 5a, 5b, 5c, 5d, input / output circuits 6a, 6b, 6c, 6d for inputting / outputting data to / from the outside, row decoder 3a, column decoder / amplifier circuit 4a, predecoder 5a and input / output circuit 6a. A control circuit 7a, a row decoder 3b, a column decoder / amplifier circuit 4b, a predecoder 5b and a control circuit 7b for controlling the input / output circuit 6b, a row decoder 3c, a column decoder / amplifier circuit 4c, a predecoder 5c and an input A control circuit 7c for controlling the output circuit 6c, a row decoder 3d, a column decoder / amplifier circuit 4d, and a predecoder d and a control circuit 7d for controlling the input and output circuit 6d.

  Further, the IC memory 1 is based on a power supply supplied from the outside, and a step-down power supply voltage intVcc for internal circuits, a silicon substrate bias voltage Vbb, a boost voltage Vpp for driving a word line, a cell plate voltage Vcp, and a bit line potential. Generated based on the power supply circuit 8 that generates the holding voltage VBL and further generates the power-on reset signal POR and the like when the power is turned on, the row address strobe signal, the chip enable signal, and the write enable signal input from the outside An input buffer 9 that outputs signals to the control circuits 7a to 7d and an address buffer 10 that is controlled by an enable signal from the control circuits 7a to 7d and generates an internal address signal based on an external address signal are provided.

  The input buffer 9 has a / RAS terminal to which a row address strobe signal / RAS is input, and / CE0, / CE1, / CE2, / CE3 to which chip enable signals / CE0, / CE1, / CE2, / CE3 are input. Each terminal is connected to each terminal and a / WE terminal to which a write enable signal / WE is input, and further connected to each control circuit 7a to 7d. The address buffer 10 is connected to terminals A0 to A13 to which address signals A0 to A13 are input, and further connected to predecoders 5a to 5d. Here, / indicates inversion of the signal level.

  The control circuits 7a to 7d are connected to the corresponding row decoders 3a to 3d, column decoders and amplifier circuits 4a to 4d, predecoders 5a to 5d, and input / output circuits 6a to 6d. Each is connected to an address buffer 10. The row decoders 3a to 3d and the column decoders and amplifier circuits 4a to 4d are connected to the corresponding memory cell arrays 2a to 2d, respectively, and the column decoders and amplifier circuits 4a to 4d are respectively connected to the corresponding input / output circuits 6a to 6d. Connected to 6d. The predecoders 5a to 5d are connected to the corresponding row decoders 3a to 3d, and are connected to the corresponding column decoders and amplifier circuits 4a to 4d, respectively. Further, the column decoder and amplifier circuits 4a to 4d are connected to corresponding input / output circuits 6a to 6d.

  The input / output circuit 6a is connected to the data input / output terminals DQ0 to DQ7, the input / output circuit 6b is connected to the data input / output terminals DQ8 to DQ15, and the input / output circuit 6c The input / output circuit 6d is connected to each of the terminals DQ16 to DQ23, and the input / output circuit 6d is connected to each of the data input / output terminals DQ24 to DQ31. The power supply circuit 8 is connected to the power supply terminals Vdd and Vss and further supplies power to each circuit, but the connection is omitted. The IC memory 1 is provided with power supply terminals VddQ and VssQ in addition to the power supply terminals Vdd and Vss, and the power supply terminals VddQ and VssQ are connected to predetermined locations of each circuit. Is omitted.

  The column decoder and amplifier circuits 4a to 4d are sense amplifiers for amplifying data of memory cells connected by the word lines selected by the corresponding row decoders 3a to 3d, and outputs of the corresponding predecoders 5a to 5d. A column decoder for selecting the sense amplifier based on the I / O switch transistor, an I / O switch transistor for connecting the sense amplifier to the local I / O line based on an output signal from the column decoder, and the local I / O It includes a preamplifier that amplifies the signal read to the line. Further, the column decoder and amplifier circuits 4a to 4d may include a write circuit for writing data to the corresponding memory cell arrays 2a to 2d based on the output signals of the corresponding input / output circuits 6a to 6d.

  The predecoders 5a to 5d generate a predecode signal from the internal address signal input from the address buffer 10, and output the predecode signal to the corresponding row decoders 3a to 3d and column decoders and amplifier circuits 4a to 4d. To do. The input / output circuits 6a to 6d output data from the data terminals based on the output signals of the preamplifiers in the corresponding column decoder and amplifier circuits 4a to 4d. The memory cell arrays 2a to 2d, row decoders 3a to 3d, column decoders and amplifier circuits 4a to 4d, predecoders 5a to 5d and control circuits 7a to 7d constitute a memory circuit unit, input / output circuits 6a to 6d, input The buffer 9 and the address buffer 10 form an input circuit unit, and the input / output circuits 6a to 6d also form an output circuit unit. The power supply circuit 8 forms a power supply circuit section.

  In the above configuration, the memory cell array 2a, the row decoder 3a, the column decoder / amplifier circuit 4a, the predecoder 5a, and the control circuit 7a are formed as one chip to form the chip 20, and the memory cell array 2b, row decoder 3b, column The decoder / amplifier circuit 4b, the predecoder 5b and the control circuit 7b are formed as one chip to form a chip 30, and the memory cell array 2c, row decoder 3c, column decoder / amplifier circuit 4c, predecoder 5c and control circuit 7c are combined into one chip. The chip 40 is formed as a chip, and the memory cell array 2d, the row decoder 3d, the column decoder / amplifier circuit 4d, the predecoder 5d, and the control circuit 7d are formed as a single chip as the chip 50.

  Further, the input / output circuits 6a to 6d, the power supply circuit 8, the input buffer 9 and the address buffer 10 are formed as a single chip to form a chip 60. On the chip 60, the chips 20, 30, 40 and 50 are arranged. Place and connect each. Here, when a signal for enabling the formed chip is input to each of the control circuits 7a to 7d, the control circuit 7a to 7d outputs a signal to the power supply circuit 8, and the power supply circuit 8 has a control circuit that has not received the signal. The capacity of the power supplied to each formed chip is reduced. The chips 20, 30, 40 and 50 form a first chip, and the chip 60 forms a second chip.

Next, FIG. 2 is a diagram showing a layout example in which the chips 20, 30, 40, 50 are arranged on the chip 60.
In FIG. 2, in the chip 20, a memory cell array 2a, a row decoder 3a, a column decoder and an amplifier circuit 4a, and a predecoder 5a are formed in portions 21 to 24, and a control circuit 7a is formed in a portion 25. In the chip 30, the memory cell array 2b, the row decoder 3b, the column decoder and amplifier circuit 4b, and the predecoder 5b are formed in the portions 31 to 34, and the control circuit 7b is formed in the portion 35.

  Similarly, in the chip 40, the memory cell array 2c, the row decoder 3c, the column decoder and amplifier circuit 4c, and the predecoder 5c are formed in the portions 41 to 44, and the control circuit 7c is formed in the portion 45. In the chip 50, the memory cell array 2d, the row decoder 3d, the column decoder and amplifier circuit 4d, and the predecoder 5d are formed in the portions 51 to 54, and the control circuit 7d is formed in the portion 55. In the chip 60, the input / output circuits 6a to 6d, the input buffer 9, and the address buffer 10 are formed in the portions 61 to 64, and the power supply circuit 8 is formed in the portion 65. Further, the chips 20, 30, 40, and 50 are disposed on and connected to the chip 60.

  Usually, the circuit portion having a high degree of integration has a high defect rate, and when the chip size exceeds 100 mm 2, the yield is drastically reduced. Therefore, the circuit portion having a high degree of integration is divided into the chips 20, 30, 40, and 50. In addition, by making the chip size of the chips 20, 30, 40, 50 not to exceed 100 mm2, the yield can be improved and the chip cost can be reduced. In the first embodiment, the portion where the degree of integration is high is divided into four chips 20, 30, 40, 50. However, the present invention is not limited to this, and the chips 20, 30, 40 are not limited thereto. , 50 chip size exceeds 100 mm 2, the portion where the degree of integration is high may be divided into more chips so that the chip size is 100 mm 2 or less.

  Next, FIG. 3 is a schematic cross-sectional view showing a connection method for connecting the chip 20 on the chip 60, and a method for connecting the chips 20, 30, 40, 50 on the chip 60 using FIG. 3. Will be described taking the chip 20 as an example. In FIG. 3, for ease of explanation, each device formed on the chips 20 and 60 is omitted, and only the part related to the connection of the chips 20 and 60 is shown. In FIG. 3, only a part of the chips 20 and 60 is shown.

  In FIG. 3, connection electrodes 71 and 72 are formed on one surface of the chip 20 where each device is formed, and an insulating film 73 is not formed on the electrodes 71 and 72, respectively. . Similarly, electrodes 75 and 76 for connection are formed on one surface of the chip 60 where each device is formed, and a pad 77 for connecting to a lead frame using a bonding wire is formed. The insulating films 78 are not formed on the electrodes 75 and 76 and the pad 77, respectively. The electrode 71 and the electrode 75, and the electrode 72 and the electrode 76 are formed at corresponding positions. The electrode 71 and the electrode 75 are connected using the bump 81, and the electrode 72 and the electrode 76 are connected using the bump 82. Connected.

  FIG. 4 is a schematic diagram showing an example of the structure in the IC package in the IC memory according to the first embodiment. In FIG. 4, the IC memory 1 is configured such that each pad 77 formed on the chip 60 to which the chips 20, 30, 40, 50 are connected by the method shown in FIG. Are electrically connected to each other.

Next, FIG. 5 is a circuit example showing a part of the address buffer 10 shown in FIG. Note that the pad 77 shown in FIG. 5 is a pad 77a.
In FIG. 5, an input protection circuit 91 having a field transistor is connected to a pad 77 to which an address signal is input from the outside. The input protection circuit 91 includes a field transistor 92, an n-channel MOS transistor 93, and two resistors 94 and 95.

  The source of the field transistor 92 is connected to the pad 77a via a resistor 94, and the drain of the n-channel MOS transistor 93 is connected to the connection portion via a resistor 95. The drain of the field transistor 92 and the gate and source of the n-channel MOS transistor 93 are each connected to the Vss terminal. A connection portion between the drain of the n-channel MOS transistor 93 and the resistor 95 is connected to one input terminal of the NOR circuit 96, and an indefinite input potential is applied to the pad 77 at the other input terminal of the NOR circuit 96. Sometimes, an address buffer enable signal / CAI for preventing a current flowing through the NOR circuit 96 is input.

  The output of the NOR circuit 97 is connected to a transmission gate 98 through an inverter circuit 97, and the transmission gate 98 is connected to a latch circuit 101 formed by two inverter circuits 99 and 100. Are connected to each of the predecoders 5 a to 5 d via the inverter circuit 102. An address latch signal / CAL for causing the latch circuit 101 to latch the signal input to the pad 77 at a predetermined timing is supplied via the gate of the n-channel MOS transistor forming the transmission gate 98 and the inverter circuit 103. Each is input to the gate of the p-channel MOS transistor.

  In such a configuration, the address buffer 10 including the input protection circuit 91 is formed in the chip 60 shown in FIG. 2, and the field transistor 92 is also formed in the chip 60. Here, the memory cell arrays 2a to 2d are not formed on the chip 60, but are formed on the chips 20, 30, 40, and 50, respectively. Therefore, since field transistor 92 and memory cell arrays 2a to 2d are not formed on the same chip, it is possible to prevent an injection failure caused by an undershoot in a signal input from pad 77. The n-channel MOS transistor 93 constituting the input protection circuit 91 is used for operation check.

FIG. 6 is a circuit example showing a part of the input / output circuits 6a to 6d shown in FIG. The pad 77 shown in FIG. 6 is referred to as a pad 77b.
In FIG. 6, the pad 77 b is connected to the source of the n-channel MOS transistor 111 and the drain of the n-channel MOS transistor 112, and the drain of the n-channel MOS transistor 111 is connected to the power supply terminal VddQ of the IC memory 1. The source of the n-channel MOS transistor 112 is connected to the power supply terminal VssQ of the IC memory 1.

  The gate of the n-channel MOS transistor 111 is connected to the output of the level conversion circuit 113, and the input of the level conversion circuit 113 is connected to the output of the NAND circuit 114. One input of the NAND circuit 115 is connected to one input of the NAND circuit 114, and an output enable signal OEM from the control circuit is input to the connection portion.

  The other input terminal of the NAND circuit 114 receives the data signal DATA from the column decoder and amplifier circuit corresponding to the input / output circuit, and the other input of the NAND circuit 115 receives the column decoder corresponding to the input / output circuit and An inverted data signal / DATA from the amplifier circuit is input. The output of the NAND circuit 115 is connected to the input of the inverter circuit 116, and the output of the inverter circuit 116 is connected to the gate of the n-channel MOS transistor 112.

  In the level conversion circuit 113, the power supply terminal 117 is connected to the power supply circuit 8, the boosted voltage Vpp is supplied from the power supply circuit 8, and the power supply terminal 118 is connected to the Vss terminal of the IC memory 1. The power supply terminal 117 may be connected to the Vdd terminal of the IC memory 1. As described above, by separating the power supply terminals 117 and 118 of the level conversion circuit 113 and the power supply connected to the n-channel MOS transistors 111 and 112, noise generated when data is output from the pad 77b is reduced. It is possible to prevent the level conversion circuit 113 from going around through the chip substrate. Further, by supplying the boosted voltage Vpp to the power supply terminal 117 of the level conversion circuit 113, the “H” level of the signal output from the pad 77b can be increased.

  Here, since the inputs of the NAND circuits 114 and 115 are connected to a column decoder and an amplifier circuit, in the input / output circuits 6a to 6d, only the NAND circuits 114 and 115 are connected to the corresponding chip 20. , 30, 40, 50. By doing so, the wiring can be shortened, the wiring can be simplified, and the number of bumps can be reduced, so that the cost can be reduced.

  Furthermore, a decoupling capacitor can be formed by forming two metal wiring layers and an isolation oxide film in empty regions other than the regions 61 to 65 in the chip 60. Since the IC memory 1 has a multi-chip structure in which the chips 20, 30, 40, and 50 are connected to the chip 60, the vacant area is formed larger in the chip 60 than in the case where the IC memory 1 is formed with one chip. Therefore, it is possible to form a decoupling capacitor having a larger capacity than the conventional one, and it is possible to reduce the decoupling capacitor that has been conventionally attached externally.

  By connecting the decoupling capacitor thus formed on the chip 60 between the VddQ terminal and the VssQ terminal of the IC memory 1 or between the terminal for outputting the boosted voltage Vpp of the power supply circuit 8 and the Vss terminal of the IC memory 1, Noise can be reduced. Further, it can be used as a decoupling capacitor for a power source consumed by the chips 20, 30, 40, and 50.

  As described above, the multichip IC memory according to the first embodiment of the present invention includes the memory cell arrays 2a to 2d, the row decoders 3a to 3d, the column decoders and amplifier circuits 4a to 4d, and the pre-integrated circuit portions. Decoders 5a to 5d and control circuits 7a to 7d are formed on chips 20, 30, 40, and 50, respectively, and input / output circuits 6a to 6d, power supply circuit 8, input buffer 9 and address, which are circuit parts having relatively low integration degrees. The buffer 10 was formed on the chip 60, and the chips 20, 30, 40, and 50 were arranged on the chip 60 and connected.

  For this reason, what was conventionally laid out two-dimensionally on the same plane can be connected three-dimensionally because the chips are stacked and connected, and the length of the signal line connecting each part can be increased. This is advantageous in speeding up the operation. In addition, since the manufacturing processes of the chips 20, 30, 40, 50 and the chip 60 can be made separately, the chips 20, 30, 40, 50 are formed with thin films suitable for miniaturization, and the chip 60 is Since it is not necessary to make it very fine, it is easy to form a thick film. For this reason, the wiring of the chip 60 can reduce the resistance value, the wiring that connects the circuit formed at a remote location is formed on the chip 60, and the wiring that connects the circuit formed at a nearby location is By forming them on the chips 20, 30, 40, 50, it is possible to increase the speed of the circuit.

  Furthermore, the transistors formed on the chips 20, 30, 40, and 50 and the gate oxide thick film of the transistors formed on the chip 60 can be easily changed. That is, the transistors forming the input buffer, the address buffer, the input / output circuit, etc. formed in the chip 60 to which a surge or the like may be input use a thick gate oxide film, and the chips 20, 30, Transistors suitable for thinning the gate oxide film are used as the transistors forming the control circuits 40 and 50. By doing so, it is possible to avoid a surge withstand voltage drop at the input / output section that occurs when miniaturization is performed. Further, the memory cell array can be formed on the chips 20, 30, 40, 50, the field transistors can be formed on the chip 60, and the memory cell array and the field transistors can be formed on different chips, respectively, which can prevent injection failure. it can.

  Further, by forming a highly integrated circuit portion that is likely to cause manufacturing defects in the chips 20, 30, 40, and 50, and reducing the chip size of each of the chips 20, 30, 40, and 50 to 100 mm 2 or less, the yield can be reduced. The chip cost can be reduced.

1 is a block diagram illustrating a circuit example of a multichip IC memory according to a first embodiment of the present invention. FIG. 3 is a diagram showing a layout example in which chips 20, 30, 40, and 50 are arranged on a chip 60. 5 is a schematic cross-sectional view showing a connection method for connecting the chip 20 on the chip 60. FIG. It is the schematic which showed the structural example in IC package of IC memory in Embodiment 1 of this invention. 2 is a circuit example showing a part of the address buffer 10 shown in FIG. 1. 2 is a circuit example showing a part of the input / output circuits 6a to 6d shown in FIG. It is the schematic block diagram which showed the circuit example of the IC memory which forms the conventional DRAM. FIG. 8 is a diagram showing a layout of each circuit when the DRAM shown in FIG. 7 is formed by one chip. FIG. 9 is a diagram illustrating a pin arrangement example of an IC memory 150 formed by a chip 200 illustrated in FIG. 8. FIG. 10 is a schematic diagram illustrating an example of a structure in the IC package illustrated in FIG. 9. It is chip | tip sectional drawing which showed the structural example of the field transistor.

Explanation of symbols

  1 IC memory, 2a to 2d memory cell array, 3a to 3d row decoder, 4a to 4d column decoder and amplifier circuit, 5a to 5d predecoder, 6a to 6d input / output circuit, 7a to 7d control circuit, 8 power supply circuit, 9 input Buffer, 10 address buffer, 20, 30, 40, 50, 60 chips, 81 bumps

Claims (10)

In a multi-chip type IC memory formed of a plurality of semiconductor chips,
At least one first chip in which a memory circuit portion having a memory cell array is formed on a semiconductor substrate;
An input circuit unit for inputting a signal from the outside, an output circuit unit for outputting a signal to the outside, and a second chip in which a power supply circuit unit for supplying power to each internal circuit is formed on a semiconductor substrate,
An IC memory, wherein the first chip is bonded to and connected to a second chip.   The IC memory according to claim 1, wherein the first chip is connected to the second chip using bumps.   2. The device according to claim 1, wherein the second chip is formed with an element for absorbing surge, wherein an isolation oxide film region is formed between two n + diffusion regions formed on a semiconductor substrate. The IC memory according to claim 2.   4. The semiconductor device according to claim 1, wherein the semiconductor element formed on the first chip is thinned and the semiconductor element formed on the second chip is thickened. 5. IC memory according to the above.   5. The gate oxide film of the transistor formed on the first chip is thinned and the gate oxide film of the transistor formed on the second chip is thickened. IC memory described in 1.   6. The wiring layer formed on the first chip is formed with a thin film, and the wiring layer formed on the second chip is formed with a thick film. IC memory.   7. The IC memory according to claim 1, wherein a decoupling capacitor is formed in an empty area of the second chip. In a multi-chip type semiconductor device formed of a plurality of semiconductor chips,
At least one first chip in which a memory circuit portion having a memory cell array is formed on a semiconductor substrate;
An input circuit unit for inputting a signal from the outside, an output circuit unit for outputting a signal to the outside, and a second chip in which a power supply circuit unit for supplying power to each internal circuit is formed on a semiconductor substrate,
The first chip is bonded and connected on the second chip, and the thickness of the gate oxide film of the transistor formed on the first chip is equal to the thickness of the gate oxide film of the transistor formed on the second chip. A semiconductor device characterized by being thinner than the thickness.   9. The film thickness of a wiring layer connecting circuits formed on the first chip is smaller than a film thickness of a wiring layer connecting circuits formed on the second chip. The semiconductor device described.   10. The semiconductor device according to claim 8, wherein a decoupling capacitor is formed in an empty area of the second chip.

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