JP2007104584A - Camera apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a camera apparatus capable of photographing a high speed image whose frame rate is higher than 30 frames per second and easily ensuring compatibility with an apparatus that can reproduce or display an image of 30 frames per second among frames configuring the high speed image. <P>SOLUTION: In the camera apparatus provided with first and second memories 7, 8 used to record or reproduce image data outputted from a signal processing section 4 and capable of photographing a video signal whose frame rate is higher than 30 frames per second, when a camera section 3 performs photographing at a frame rate higher than 30 frames per second, the first memory 7 records frames at a frame rate of 30 frames per second among frames configuring image data and the second memory 8 records the other frames than the frames recorded in the first memory 7. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a camera device having a high-speed shooting function.

  In Japan, a photographing apparatus (video camera) capable of recording a general moving image has a specification in which a video signal to be recorded conforms to the NTSC system, and a magnetic tape or an optical disk is generally used as an information medium on which the video signal is recorded. It is popular. The NTSC system is a specification of 525 horizontal scanning lines, vertical synchronization frequency 60 Hz, and 2: 1 interlace. That is, an image (frame) of 30 frames per second is recorded. Further, it is widely known that the DV standard is a standard for digitally recording video signals and the like on a magnetic tape, and the DVD video standard is a standard for digitally recording video signals and the like on an optical disk.

On the other hand, there are high-speed photographing cameras that output images composed of a frame rate higher than 30 frames per second in professional video cameras. A high-speed shooting camera is a camera capable of high-quality slow motion playback by recording a moving image with an increased frame rate as described above. Applications of such cameras are for athlete athlete form analysis, research and development of vehicle airbags, and factory process monitoring. The number of frames of video that can be recorded with a high-speed camera is large, and it is possible to shoot several hundred to several thousand frames per second. A high-speed camera device is generally configured to connect to a personal computer and store the captured video in a dedicated format in a large-capacity storage device such as a hard disk mounted on the personal computer (for example, a patent) Reference 1).
JP-A-6-54281

  However, since the high-speed shooting camera device as described above needs to be connected to a personal computer, the user cannot easily carry it. In addition, since the video is recorded in a dedicated hard disk etc. in a dedicated format, it is difficult to play or display the image on devices other than the personal computer and the display connected to it, ensuring easy compatibility. I couldn't.

  In view of the above problems, the present invention can capture a high-speed image at a frame rate higher than 30 frames per second, and among the frames constituting the captured high-speed image, a frame corresponding to 30 frames per second; It is an object of the present invention to provide a camera device capable of easily ensuring compatibility with a device capable of reproducing or displaying an image of 30 frames per second by recording other frames on different information media.

  In order to solve such a problem, an image sensor that converts an incident optical signal into an electric signal, a video signal is generated based on the electric signal output from the image sensor, and the generated video signal is compressed. A signal processing unit for outputting image data, and first and second memories for recording or reproducing the image data output from the signal processing unit, and a video signal having a frame rate higher than 30 frames per second. A camera device capable of photographing, wherein when shooting at a frame rate higher than 30 frames per second by the camera unit, 30 frames per second of frames constituting the image data are stored in the first memory. And a frame other than the frame recorded in the first memory is recorded in the second memory.

  The present invention can realize a high-speed photographing function capable of photographing at a high frame rate in a camera device.

  In addition, only 30 frames per second that are compatible with general television signals can be extracted from the frames constituting the high-speed image and written into an independent memory, so 30 frames per second. It is possible to easily ensure compatibility with a device capable of reproducing or displaying the image.

  In the camera device of the present invention, the second memory may be composed of a plurality of memories, and image data may be divided and recorded in the plurality of memories.

  The first memory may be a detachable nonvolatile memory.

(Embodiment 1)
FIG. 1 is a block diagram of a camera apparatus according to an embodiment of the present invention.

  In FIG. 1, the camera unit 3 includes a lens 1 and an image sensor 2. The imaging device 2 forms an image of reflected light from a subject incident through the lens 1, converts it into an electrical signal, and outputs it. Further, the image pickup device 2 is composed of, for example, a CCD image sensor or a CMOS image sensor.

  The first signal processing circuit 4 performs camera signal processing such as noise removal and image quality adjustment on the output signal of the image sensor 2, zoom control and focus control for the lens 1, and operation control of the image sensor 2. Data compression / decompression processing is performed on signals. The video signal output from the first signal processing circuit 4 is referred to as “image data”. The image data is composed of compressed video signals and audio signals, and additional information (photographing date and time, bit rate information, etc.) associated therewith.

  The first memory interface circuit 5 can write the image data output from the first signal processing circuit 4 in the first memory 7. In addition, the image data recorded in the first memory 7 can be reproduced.

  The first memory 7 is composed of an information medium that is detachable from the camera device, and is composed of, for example, a memory card on which a semiconductor memory is mounted, a disk such as a recordable DVD, a magnetic tape, or the like. Note that the magnetic tape does not have to be used when reproducing a video signal taken at a high speed, because a random access such as a disk is not possible or data reading is slow.

  The second memory interface circuit 6 can write the image data output from the first signal processing circuit 4 in the second memory 8 to the eighth memory 14. Further, the image data recorded in the second memory 8 to the eighth memory 14 can be read out.

  The second memory 8 to the eighth memory 14 are composed of information media fixed to the apparatus, and are composed of, for example, a semiconductor memory composed of a nonvolatile memory or a volatile memory, a hard disk, or the like. In this embodiment, the number of memories is seven. However, the number of memories is not limited, and the number of memories may be increased or decreased depending on image quality (frame rate) or cost. Further, the information medium is not necessarily limited to a fixed type information medium, and may be constituted by a detachable information medium.

  The second signal processing circuit 15 includes the image data read from the first memory 7 by the first memory interface circuit 5 and the second memory 8 to the eighth memory 14 by the second memory interface circuit 6. A video signal with a high frame rate is reproduced from the image data read out from. Specifically, one moving image is generated by connecting frames read from each memory.

  The display unit 16 is capable of displaying the video signal output from the second signal processing circuit 15 and is composed of, for example, a liquid crystal display of about 2 to 4 inches or an electronic viewfinder that allows the user to view and view the video. However, it is not limited to these.

  The operation of the photographing apparatus configured as described above will be described.

  First, when an image of a subject is captured by the camera device, optical information such as reflected light of the subject is imaged on the image sensor 2 via the lens 1. In the image sensor 2, incident optical information is converted into electrical information by a photoelectric conversion action and output to the signal processing circuit 4. The signal processing circuit 4 performs camera signal processing such as white balance processing that corrects the color temperature of the video signal, gamma correction processing that corrects gradation, and NR (noise reduction) processing that reduces noise, and image data. Compression / decompression processing is performed.

  The reason why the image data needs to be compressed / decompressed is to record the video signal on the information medium without any problem. That is, the image data when an NTSC analog video signal is converted into a digital signal has a large data amount, which is about 20 Mbytes / second. If such large-capacity data is recorded on an information medium without being compressed, the recording time may be shortened due to the capacity limitation of the information medium. Further, when the video frame rate in the image data to be recorded is higher than the writing rate of the information medium, there is a possibility that frame loss (frame drop) may occur in the video signal.

  The compressed image data is written into the first memory 7 to the eighth memory 14 via the first memory interface circuit 5 and the second memory interface circuit 6, respectively. A specific write operation will be described later.

  In the present embodiment, the first memory 7 is composed of a removable nonvolatile memory such as a memory card. The second memory 8 to the eighth memory 14 do not need to be nonvolatile memories, but even if they are constituted by nonvolatile memories, the effects of the present embodiment are not hindered.

  Next, the image data writing operation to the first memory 7 to the eighth memory 14 will be described.

  FIG. 2 is a timing chart for explaining how image data is written to the memory. In FIG. 2, (a) is a general video signal, and the period of the frame is 1/30 second. (B) shows an image signal taken at a high speed, and the frame period is 1/240 seconds which is 1/8 of (a). Note that 1/240 is set as an example, and other numerical values may be used. (C) shows an image signal recorded in the first memory 7. (D) to (j) show image data written in the second memory 8 to the eighth memory 14. The horizontal axis is time.

  In this embodiment, as shown in FIG. 1, eight memories are provided, and high-speed captured image data (FIG. 2 (b)) of 240 frames / second inputted is converted into FIGS. 2 (c) to (j). As shown in FIG. 3, the image data is divided into 30 frames / second and recorded in different memories. That is, each frame of the high-speed captured image data shown in (b) is written to the first memory 8 to the eighth memory 14 in order from the front. Therefore, the frames recorded in each memory are written by shifting one frame at a time between the memories as shown in (c) to (j), but in each memory, image data with a period of 30 frames per second is recorded. Has been.

  By recording in this way, normal image data of 30 frames / second can be recorded in the first memory 7 as shown in FIG. Therefore, when the apparatus is externally connected to another device (for example, a television receiver) and image data is reproduced, the image data can be reproduced based on the image data output from the first memory 7, and compatibility Can keep. The image data read from the first memory 7 is input to the second signal processing circuit 15 via the first memory interface circuit 5. The second signal processing circuit 15 restores a moving image (video signal and audio signal) from the input image data and causes the display unit 16 to display it.

  In addition, since the first memory 7 is detachable from the apparatus, the first memory 7 is detached from the apparatus, and the first memory 7 is attached to another detachable device to reproduce image data. It is also possible to do.

  In the case of high-speed playback, the second memory interface circuit 6 reads out image data from the first memory 7 to the eighth memory 14 in order (recorded order), and sends the image data to the second signal processing circuit 15. Output. The second signal processing circuit 15 generates a single moving image by arranging the input image data in time series and displays the moving image on the display unit 16.

  As a compression format of the image data, the standard Motion-JPG (AVI), the MPEG system, or the like can be used. Note that the image data recorded in the second memory 8 to the eighth memory 14 does not have to maintain compatibility with other devices, and therefore has the necessity of using the above-mentioned standard. Absent. The reason for providing seven memories excluding the first memory 7 is to reduce the data writing speed to each memory.

(Embodiment 2)
FIG. 3 is a timing chart showing image data recording and reproduction operations in a camera apparatus having two memories (for example, the second memory 8 and the third memory 9 in FIG. 1) in addition to the first memory 7. It is a chart.

  In FIG. 3, (a) is a general video signal, and the frame period is 1/30 second. (B) is an example of image data taken at a high speed, and the frame period is 1/240 seconds, which is 1/8 of the normal frame period. (C) shows the image data recorded in the first memory 7. (D) and (e) show image data recorded in the second memory 8 and the third memory 9.

  In the above configuration, a general video signal (frame period of 1/30 seconds) as shown in (c) is recorded in the first memory 7. Also, image data having a frame period of 1/120 seconds is recorded in the second memory 8 and the third memory 9, respectively, as shown in (d) and (e). Each frame in the image data shown in (d) and each frame in the image data shown in (e) have a phase difference of 1/240 seconds. That is, the image data shown in (b) is written alternately into the second memory 8 and the third memory 9 frame by frame.

  In the image data recorded as described above, the image data shown in (c) can be read from the first memory 7 to reproduce a video signal having a frame period of 1/30 seconds. Also, by reading out the image data shown in (d) and (e) from the second memory 8 and the third memory 9, and connecting the frames, a frame period of 1/240 seconds as shown in (b) Can be reproduced.

  According to the present embodiment, it is possible to realize recording and reproduction of image data with a small number of memories.

(Embodiment 3)
FIG. 4 is a timing chart showing image data recording and reproducing operations in a camera apparatus having two memories (for example, the second memory 8 and the third memory 9 in FIG. 1) in addition to the first memory 7. It is a chart.

  In FIG. 4, (a) is a general video signal, and the frame period is 1/30 second. (B) is an example of image data taken at a high speed, and the frame period is 1/240 seconds, which is 1/8 of the normal frame period. (C) shows the image data recorded in the first memory 7 and has a frame period of 1/30 seconds. (D) and (e) show image data recorded in the second memory 8 and the third memory 9. 4 is different from the operation of FIG. 3 in that FIG. 3 records one frame, whereas FIG. 4 records two frames. That is, in the eight frames having a frame period of 1/240 seconds in the image data shown in (b), the first two frames are recorded in the second memory 8, and the next two frames are recorded in the third frame. The next two frames are recorded in the second memory 9 and the last two frames are recorded in the third memory 10.

  4, the operation of recording and reproducing image data with respect to each memory and the operation of generating a video signal based on the reproduced image data are substantially the same as the operation in FIG.

  According to the present embodiment, it is possible to realize recording and reproduction of image data with a small number of memories.

(Embodiment 4)
FIG. 5 is a timing chart showing image data recording and reproducing operations in a camera apparatus having two memories (for example, the second memory 8 and the third memory 9 in FIG. 1) in addition to the first memory 7. It is a chart.

  In FIG. 5, (a) is a general video signal, and the cycle of the frame is 1/30 second. (B) is an example of image data taken at a high speed, and the frame period is 1/240 seconds, which is 1/8 of the normal frame period. (C) shows the image data recorded in the first memory 7 and has a frame period of 1/30 seconds. (D) and (e) show image data recorded in the second memory 8 and the third memory 9.

  5 differs from the operation of FIG. 3 in that FIG. 3 records one frame at a time, whereas FIG. 5 records four frames. That is, in the eight frames having the frame period of 1/240 seconds in the image data shown in (b), the first four frames are recorded in the second memory 8, and the next four frames are recorded in the third frame. Are recorded in the memory 9.

  In FIG. 5, the operation of recording and reproducing image data with respect to each memory and the operation of generating a video signal based on the reproduced image data are substantially the same as the operation in FIG.

  According to the present embodiment, it is possible to realize recording and reproduction of image data with a small number of memories.

(Embodiment 5)
FIG. 6 is a timing chart showing image data recording and reproduction operations in a camera apparatus having four memories (for example, the second memory 8 to the fifth memory 11 in FIG. 1) in addition to the first memory 7. It is a chart.

  In FIG. 6, (a) is a general video signal, and the cycle of the frame is 1/30 second. (B) is an example of image data taken at a high speed, and the frame period is 1/240 seconds, which is 1/8 of the normal frame period. (C) shows the image data recorded in the first memory 7 and has a frame period of 1/30 seconds. (D) to (g) show image data recorded in the second memory 8 to the fifth memory 10.

  6 is different from the operation of FIG. 3 in that FIG. 3 records two frames in one frame, whereas FIG. 6 records two frames in four memories. That is, in the eight frames having a frame period of 1/240 seconds in the image data shown in (b), the first two frames are recorded in the second memory 8, and the next two frames are recorded in the third frame. The next two frames are recorded in the fourth memory 10, and the last two frames are recorded in the fourth memory 11.

  In FIG. 6, the operation of recording and reproducing image data with respect to each memory and the operation of generating a video signal based on the reproduced image data are substantially the same as the operation in FIG.

  According to the present embodiment, since many memories are mounted, even when the writing speed of each memory is slow, image data can be recorded and reproduced without dropping frames.

(Embodiment 6)
FIG. 7 is a timing chart showing image data recording and reproduction operations in a camera apparatus having four memories (for example, the second memory 8 to the fifth memory 11 in FIG. 1) in addition to the first memory 7. It is a chart.

  In FIG. 7, (a) is a general video signal, and the cycle of the frame is 1/30 second. (B) is an example of image data taken at a high speed, and the frame period is 1/240 seconds, which is 1/8 of the normal frame period. (C) shows the image data recorded in the first memory 7 and has a frame period of 1/30 seconds. (D) to (g) show image data recorded in the second memory 8 to the fifth memory 10.

  7 differs from the operation shown in FIG. 6 in that FIG. 6 is recorded in each memory by 2 frames, whereas FIG. 7 is recorded in each memory by 1 frame. That is, in the eight frames having the frame period of 1/240 seconds in the image data shown in (b), the first frame is recorded in the first memory 7 and the second memory 8, and the second frame is recorded in the second frame. 3, the third frame is recorded in the fourth memory 10, and the fourth frame is recorded in the fourth memory 11. In addition, the fifth frame is recorded in the second memory 8, the sixth frame is recorded in the third memory 9, the seventh frame is recorded in the fourth memory 10, and the eighth frame is recorded. 4 is recorded in the memory 11.

  In FIG. 7, the operation of recording and reproducing image data with respect to each memory and the operation of generating a video signal based on the reproduced image data are substantially the same as the operation in FIG.

  According to the present embodiment, since many memories are mounted, even when the writing speed of each memory is slow, image data can be recorded and reproduced without dropping frames.

(Embodiment 7)
FIG. 8 is a timing chart showing image data recording and reproduction operations in a camera apparatus provided with one memory (for example, the second memory 8 in FIG. 1) in addition to the first memory 7.

  In FIG. 8, (a) is a general video signal, and the cycle of the frame is 1/30 second. (B) is an example of image data taken at a high speed, and the frame period is 1/240 seconds, which is 1/8 of the normal frame period. (C) shows the image data recorded in the first memory 7 and has a frame period of 1/30 seconds. (D) shows image data recorded in the second memory 8.

  In FIG. 8, the captured image data is recorded in the first memory 7 in the eight frames having a frame period of 1/240 seconds as shown in FIG. The second frame is recorded in the second memory 8.

  In FIG. 8, the operation of recording and reproducing image data with respect to each memory and the operation of generating a video signal based on the reproduced image data are substantially the same as the operation in FIG.

  According to the present embodiment, it is possible to realize recording and reproduction of image data with a small number of memories.

(Embodiment 8)
FIG. 9 is a timing chart showing image data recording and reproduction operations in a camera apparatus having two memories (for example, the second memory 8 to the fifth memory 11 in FIG. 1) in addition to the first memory 7. It is a chart.

  In FIG. 9, (a) is a general video signal, and the cycle of the frame is 1/30 second. (B) is an example of image data taken at a high speed, and the frame period is 1/240 seconds, which is 1/8 of the normal frame period. (C) shows the image data recorded in the first memory 7 and has a frame period of 1/30 seconds. (D) and (e) show image data recorded in the second memory 8 and the third memory 9.

  In FIG. 9, the captured image data is recorded in the first memory 7 in the eight frames having a frame period of 1/240 seconds as shown in FIG. The fifth frame is recorded in the second memory 8, and the fifth to eighth frames are recorded in the third memory 9.

  In FIG. 9, the operation of recording and reproducing image data with respect to each memory and the operation of generating a video signal based on the reproduced image data are substantially the same as the operation in FIG.

  According to the present embodiment, it is possible to realize recording and reproduction of image data with a small number of memories.

(Embodiment 9)
Next, recording and reproducing operations of image data composed of 2: 1 interlace signals will be described.

  As shown in FIG. 12, the 2: 1 interlace signal divides a frame image 31 into an odd field 32 composed of odd-numbered scan lines and an even field 33 composed of even-numbered scan lines. The odd field 32 and the even field 33 are alternately output. In the case of FIG. 12, the frame period is 1/30 seconds, the field period is 1/60 seconds, the number of scanning lines in the frame is 480, and the number of scanning lines in the field is 240. FIG. 10 shows the operation timing when the interlace signal taken at high speed is recorded in the memory.

  In FIG. 10, (a) shows image data composed of a general interlace signal, and has a frame period of 1/30 seconds and a field period of 1/60 seconds. (B) shows image data of an interlaced signal taken at high speed, and has a frame period of 1/240 seconds and a field period of 1/480 seconds. In (b), the odd field and the even field are alternately arranged starting from the odd field. (C) shows the image data recorded in the first memory 7. (D) shows image data recorded in the second memory 8. In FIG. 10, the odd field is shown with hatching, and the even field is shown without hatching.

  In FIG. 10, in order to keep the order of the odd field and the even field of the image data written to the first memory 7, the write timings of the odd field and the even field are not equal as shown in (c). However, odd fields and even fields are written with a uniform period.

  In FIG. 10, as shown in FIG. 10B, the image data taken at high speed is written in the first odd field image to the first memory 7 and the image data from the first even field to the fifth odd field is written. Write to the second memory 8. Next, the fifth even field image is written to the first memory 7, and the image data from the sixth odd field to the eighth even field is written to the second memory 8. As a result, out of the 16 field images in (b) corresponding to one frame cycle period in (a), the first memory 7 can record odd field images and even field images one by one. The remaining 14 pieces of image data can be recorded in the second memory 8.

  According to the present embodiment, it is possible to realize recording and reproduction of image data with a small number of memories.

(Embodiment 10)
In FIG. 11, (a) shows the image data comprised by the general interlace signal, and a frame period is 1/30 second and a field period is 1/60 second. (B) shows image data of an interlaced signal taken at high speed, and has a frame period of 1/240 seconds and a field period of 1/480 seconds. In (b), the odd field and the even field are alternately arranged starting from the odd field. (C) shows the image data recorded in the first memory 7. (D) shows image data recorded in the second memory 8. In FIG. 11, the odd field is shown with hatching, and the even field is shown without hatching.

  In FIG. 11, as shown in FIG. 11B, image data taken at high speed is written in the first odd-numbered field and even-numbered field image data to the first memory 7, and the eighth odd-numbered and even-numbered fields are eighth. The image data up to the odd and even fields are written into the second memory 8.

  As a result, out of the 16 field images in (b) corresponding to one frame cycle period in (a), the first memory 7 can record odd field images and even field images one by one. The remaining 14 pieces of image data can be recorded in the second memory 8.

  According to the present embodiment, it is possible to realize recording and reproduction of image data with a small number of memories.

  As described above, according to the present embodiment, image data having a frame period of 1/30 seconds, which is general image data, is recorded in the first memory 7, and different displays such as a television receiver are used. Compatibility with equipment can be maintained.

  In the present invention, image data taken at high speed is divided and recorded in a plurality of memories, and the first memory is constituted by a removable nonvolatile memory and is recorded in the first memory at a frame period of general image data. As a result, it is possible to provide a high-speed shooting camera device that can perform high-speed shooting and at the same time maintain good compatibility with other devices.

  The present invention mounts a high-speed shooting function that can be used for sports form analysis or the like on a portable shooting device, and is useful in a video camera, a digital still camera, a mobile phone with a camera, and the like.

1 is a block diagram showing a configuration of a camera device according to Embodiment 1 of the present invention. Timing chart showing operation in the first embodiment Timing chart showing operation of the second embodiment Timing chart showing operation of embodiment 3 Timing chart showing operation of embodiment 4 Timing chart showing operation of embodiment 5 Timing diagram showing the operation of the sixth embodiment Timing diagram showing the operation of the seventh embodiment Timing diagram showing the operation of the eighth embodiment Timing diagram showing the operation of the ninth embodiment Timing diagram showing the operation of the tenth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lens 2 Image pick-up element 3 Camera part 4 Signal processing circuit 5 1st memory interface circuit 6 2nd memory interface circuit 7 1st memory 8 2nd memory 9 3rd memory 10 4th memory 11 5th Memory 12 6th memory 13 7th memory 14 8th memory

Claims (3)

An image sensor that converts an incident optical signal into an electrical signal;
A signal processing unit that generates a video signal based on an electrical signal output from the imaging device, compresses the generated video signal, and outputs image data;
First and second memories for recording or reproducing image data output from the signal processing unit,
A camera device capable of photographing a video signal having a frame rate higher than 30 frames per second,
When shooting at a frame rate higher than 30 frames per second by the camera unit,
In the first memory, a frame corresponding to 30 frames per second among the frames constituting the image data is recorded,
The camera device according to claim 1, wherein a frame other than a frame recorded in the first memory is recorded in the second memory.   The camera device according to claim 1, wherein the second memory includes a plurality of memories, and image data is divided and recorded in the plurality of memories.   The camera device according to claim 1, wherein the first memory includes a detachable nonvolatile memory.

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