JP2007102022A - Flat display device and driving method of the flat display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flat display device of which power consumption is reduced, without causing the display quality to lower, and a driving method of the flat display device. <P>SOLUTION: The flat display device is equipped with an effective display part 110 where a plurality of display pixels PX are arrayed, a plurality of scanning lines Y arranged along rows where the plurality of display pixels PX are arrayed, a plurality of signal lines X, arranged along columns where the plurality of pixels PX are arrayed, a scanning line drive circuit 120 which scans the plurality of scanning lines Y, a signal line drive circuit 130, which supplies an image signal PD to the display pixels PX via the plurality of signal lines X, switch elements B provided in between signal lines differing in polarity, and a controller TCON, having a scanning line control part SLC which makes the scanning line drive circuit 120 scan alternate or more scanning lines Y and a switch control part SWC which turns on the switching elements B in a non-scanning period T1 of the scanning line drive circuit 120. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a flat panel display device, and more particularly to a flat panel display device driven by an active matrix system and a driving method of the flat panel display device.

  In general, the flat display device includes an effective display unit in which a plurality of display pixels are arranged in a matrix, a plurality of scanning lines arranged along a row in which the plurality of display pixels are arranged, and a plurality of display pixels. And a plurality of signal lines arranged along the columns to be arranged.

  The plurality of scanning lines are connected to a scanning line driving circuit. The scanning line driving circuit selects a display pixel for each row through each scanning line. The plurality of signal lines are connected to a signal line driving circuit. The signal line driver circuit supplies an image signal to the display pixels in the row selected by the scanning line driver circuit via each signal line.

Conventionally, a scanning line driving circuit sequentially drives all scanning lines to display an image of one screen in one frame. Recently, especially in mobile products, the scanning line drive circuit thins out one or more scanning lines and drives them in an interlaced manner. One frame is composed of a plurality of fields to display a single screen image, thereby reducing power consumption. There has been proposed a flat display device that reduces the thickness (see Patent Document 1).
JP 2001-282204 A

  In the above flat display device, generally, charges stored in display pixels have positive and negative polarities, and the distribution of positive and negative electrodes has regularity. Thus, in the flat display device in which the display pixel has positive and negative polarities, the polarity of the image signal applied to the signal line is inverted according to a certain rule. As a result, when a large amount of power is consumed by the signal line driving circuit to drive the signal line at the timing when the polarity of the image signal applied to the signal line is inverted, the effect of the interlaced driving is obtained. In some cases, it was not possible to get enough.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a flat display device that reduces power consumption without degrading display quality, and a driving method of the flat display device. .

The flat display device according to the first aspect of the present invention includes an effective display unit in which a plurality of display pixels are arranged,
A plurality of scanning lines arranged along a row in which the plurality of display pixels are arranged, a plurality of signal lines arranged along a column in which the plurality of display pixels are arranged, and the plurality of scanning lines. A scanning line driving circuit for scanning; a signal line driving circuit for supplying an image signal to a display pixel via the plurality of signal lines; a switch element provided between signal lines having different polarities; and the scanning line driving A flat panel display device comprising: a scanning line control unit that causes a circuit to scan one or more scanning lines by interlaced; and a controller that includes a switch control unit that turns on the switch element during a non-scanning period of the scanning line driving circuit.

  The driving method of the flat display device according to the second aspect of the present invention includes an effective display unit in which a plurality of display pixels are arranged, a plurality of scanning lines arranged along a row in which the plurality of display pixels are arranged, A plurality of signal lines arranged along a column in which a plurality of display pixels are arranged, a scanning line driving circuit that scans the plurality of scanning lines, and an image signal is supplied to the display pixels through the plurality of signal lines. A driving method of a flat display device comprising: a signal line driving circuit; a switching element provided between each of signal lines having different polarities; and a controller for controlling the scanning line driving circuit and the switching element, The controller controls the scanning line driving circuit to scan the plurality of scanning lines at one or more intervals, and turns on the switch element while the scanning line driving circuit is not scanning the scanning line. The pole Shorting between different signal lines of.

  According to the present invention, it is possible to provide a flat panel display device and a driving method of the flat panel display device that reduce power consumption without degrading display quality.

  A flat display device according to an embodiment of the present invention will be described below with reference to the drawings.

  As shown in FIG. 1, the flat display device according to the present embodiment includes a liquid crystal display panel 101 including a pair of substrates arranged opposite to each other and a liquid crystal layer (not shown) sandwiched between the pair of substrates. It is the liquid crystal display device 100 which has.

  The liquid crystal display panel 101 includes an effective display unit 110 in which a plurality of display pixels PX are arranged, a plurality of scanning lines Y arranged along a row in which the display pixels PX are arranged, and a column in which the display pixels PX are arranged. And a plurality of signal lines X arranged in a row. A circuit board 150 is electrically connected to the end of the liquid crystal display panel 101 via a flexible board 140.

  Each display pixel PX includes a switch element TR such as a thin film transistor and a pixel capacitor PC connected to the drain electrode of the switch element TR. The gate electrode of the switch element TR is connected to the scanning line Y, and the source electrode is connected to the signal line X.

  The liquid crystal display panel 101 further includes a pixel electrode (not shown) disposed in each display pixel and a counter electrode (not shown) facing all the pixel electrodes. When a voltage is applied between the pixel electrode and the counter electrode, charges are stored in the pixel capacitor PC. Here, the charge stored in the pixel capacitor PC may be positive or negative with respect to the potential of the counter electrode.

  In the present embodiment, as shown in FIG. 1, in the effective display unit 110, the distribution of the positive display pixels PX and the negative display pixels PX is two pixels in the direction in which the signal line X extends, and the direction in which the scanning line Y extends. In addition, display pixels PX having the same polarity are arranged in a range of one pixel. That is, display pixels PX having different polarities are alternately arranged in the direction in which the scanning line Y extends, and display pixels having different polarities are alternately arranged in every two pixels in the direction in which the signal line X extends. Yes.

  Around the effective display section 110, a scanning line driving circuit 120 for driving a plurality of scanning lines Y and switch circuits SWA and SWB are arranged. On the flexible substrate 140, a signal line driving circuit 130 that supplies an image signal PD to the display pixels PX via a plurality of signal lines X is disposed. The plurality of scanning lines Y are all connected to the scanning line driving circuit 120. The plurality of signal lines X are connected to the signal line driving circuit 130 via the switch circuits SWA and SWB.

  The scanning line driving circuit 120 selects one row of display pixels PX via each scanning line Y. The signal line driving circuit 130 supplies an image signal PD corresponding to one row of display pixels PX selected by the scanning line driving circuit 120 to each display pixel PX.

  The switch circuit SWA has a switch element A for electrically disconnecting the signal line drive circuit 130 and the display pixel PX, and the switch circuit SWB has a switch element B for short-circuiting signal lines having different polarities. is doing. The switch element A and the switch element B are, for example, thin film transistors formed on a substrate.

  The scanning line driving circuit 120, the signal line driving circuit 130, and the switch circuits SWA and SWB are controlled by a timing controller TCON arranged on the circuit board 150. The timing controller TCON has a scanning line control unit SLC and a switch control unit SWC. The switch control unit SWC has a second switch control unit SWC2.

  The scanning line control unit SLC transmits a timing signal YST, a clock signal YCK, an output enable signal OE, and the like to the scanning line driving circuit 120. The scanning line driving circuit 120 is controlled so as to interlace and scan one or more scanning lines Y in response to the output enable signal OE from the timing controller TCON.

  The timing controller TCON transmits a timing signal XST, a clock signal XCK, an image signal PD, and the like to the signal line driver circuit 130. The signal line driving circuit 130 drives the signal line X in response to the timing signal XST from the timing controller TCON, and outputs the video signal PD ′ (based on the digital image signal PD) to the display pixel via the driven signal line X. Write the created analog signal).

  The gate electrodes of the switch element A and the switch element B are electrically connected to the switch control unit SWC of the timing controller TCON. The source electrode of the switch element A is connected to the output terminal of the signal line driving circuit 130, and the drain electrode is connected to each signal line X extending to the effective display section 110.

  The source electrode and the drain electrode of the switch element B are connected to a signal line X connected to the display pixel PX having a different polarity. In the case shown in FIG. 1, the switch element B includes the signal line X1 and the signal line X2, the signal line X3 and the signal line X4,..., And the signal line X (m−1) and the signal line X (m). Is arranged.

  The switch control unit SWC turns on the switch element B during a period in which the scanning line driving circuit 120 does not drive the scanning line Y, that is, a non-scanning period. The switch element A is turned off during the non-scanning period by the second switch control unit SWC2 of the switch control unit SWC.

  In the present embodiment, the scanning line driving circuit 120 performs interlace scanning by skipping the scanning lines Y line by line. That is, as shown in FIG. 2, the scanning line driving circuit 120 scans the scanning lines Y1, Y3, Y5... And scans the scanning lines Y2, Y4, Y6. The operation of the liquid crystal display device 100 in this case will be described below.

  In the following description, the signal line X in which the positive charge is accumulated is referred to as a positive signal line X (a), and the signal line X in which the negative charge is accumulated is referred to as a negative signal line X (a + 1). When the polarities of the display pixels are arranged as in the liquid crystal display panel 100 according to the present embodiment, the polarity of the voltage Vout applied to the signal line X is inverted in two horizontal periods as shown in FIG.

  At this time, the timing controller TCON sets the switch control signal SW to high (H) in a period during which the scanning line driving circuit 120 performs interlace scanning on the scanning lines Y2, Y4, Y6.

  At the timing when the switch control signal SW becomes high, the switch element A is turned off and the switch element B is turned on. Therefore, at this time, the output terminal of the signal line driving circuit 130 and each signal line X are electrically disconnected by the switch element A, and the positive signal line X (a) and the negative signal line X (a + 1) are switched by the switch element B. Are electrically connected.

  As a result, the charges accumulated in the positive signal line X (a) and the negative signal line X (a + 1) in the period when the switch element B is on, that is, in the non-scanning period T1, are averaged. Therefore, when the voltage of the opposite polarity is next applied to the signal line X, the load that the signal line driving circuit 130 drives the signal line X is reduced. Therefore, the power consumption for driving the signal line X by the signal line driving circuit 130 is also reduced.

  As described above, according to the present embodiment, in the liquid crystal display device 100 in which the scanning line driving circuit 120 performs interlace scanning, further reduction in power consumption is realized by reducing the power consumption of the signal line driving circuit 130. A liquid crystal display device 100 can be provided.

  Further, as described above, the time for writing the image signal PD to the pixel capacitor PC by averaging the charges accumulated in the positive signal line X (a) and the negative signal line X (a + 1) in the non-scanning period T1. The display quality of the liquid crystal display device 100 can be maintained.

  Next, another embodiment of the present invention will be described. In the following description, components similar to those in the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 1, the timing controller TCON has a second scanning line control unit SLC2 in the scanning line control unit SLC. The second scanning line control unit SLC2 controls the scanning line driving circuit 120 to switch the scanning line Y corresponding to the display pixel PX to which the image signal PD is next supplied prior to the period during which the image signal PD is written. Drive during a period when B is on.

  That is, as shown in FIG. 3, the scanning line driving circuit 120 scans the scanning lines Y1, Y3, Y5... In the 1/2 field of the nth frame as in the above-described embodiment, and the scanning lines Y2, Y4,. Interlaced scanning is performed by skipping Y6. In the present embodiment, the scanning line Y corresponding to the row of the display pixel PX to which the image signal PD is next supplied is in the non-scanning period T1 in which the scanning line driving circuit 120 skips the scanning lines Y2, Y4, Y6. Driven.

  For example, as shown in FIG. 3, in the non-scanning period T1 after the scanning line driving circuit 120 drives the scanning line Y3, the scanning line Y5 corresponding to the row of the display pixel PX into which the image signal PD is written next is driven. Is done. That is, since the switch element A is off and the switch element B is on in the non-scanning period T1, the positive display pixel and the signal line X (a) and the negative display pixel and the signal line X (a + 1) Are electrically connected by the switch element B, and the charges accumulated in the signal line X and the pixel capacitor PC having different polarities are averaged prior to the period in which the image signal PD is written.

  Except for the above points, the liquid crystal display device according to the above-described embodiment operates in the same manner. According to this embodiment, not only the same effects as those of the above-described embodiment can be obtained, but also by averaging the charge stored in the pixel capacitor PC before the image signal PD is written to the pixel capacitor PC. The load on the signal line driver circuit 130 can be reduced. That is, it is possible to provide the liquid crystal display device 100 that further achieves power saving.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.

  For example, in the above embodiment, the switch circuits SWA and SWB are disposed in the liquid crystal display panel 101, but may be included in the signal line drive circuit 130. In this case, the same effect as that of the above embodiment can be obtained.

  Further, in the above embodiment, the timing controller TCON causes the scanning line driving circuit 120 to thin out the scanning lines Y one by one and perform interlace scanning, thereby forming two fields and one frame. However, if the non-scanning period T1, which is a period for averaging the charges accumulated in the signal lines and the pixel capacitors, is not sufficient for the period in which the scanning line Y is thinned out by one line, the scanning line Y is thinned out every two or more lines. You may make it scan. In this case, the non-scanning period T1 is two or more horizontal periods, and a sufficient period for averaging the charges accumulated in the signal line and the pixel capacitor is obtained. Accordingly, it is possible to provide a liquid crystal display device that reduces power consumption while maintaining display quality of a display image.

  In the above embodiment, the liquid crystal display device has been described as a flat display device. However, the present invention is not limited to this, and the present invention may be applied to, for example, an organic EL display device using an organic EL element as a display element. Also in this case, the same effect as the above embodiment can be obtained.

  In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

1 is a diagram schematically showing a liquid crystal display panel of a liquid crystal display device according to one embodiment of the present invention. 3 is a timing chart illustrating an operation example of the liquid crystal display device illustrated in FIG. 1. 6 is a timing chart illustrating another example of the operation of the liquid crystal display device illustrated in FIG.

Explanation of symbols

  PX ... display pixel, Y1-Y (m) ... scanning line, X1-X (n) ... signal line, TR ... switch element, PC ... pixel capacitance, SWA, SWB ... switch circuit, A, B ... switch element, TCON ... Timing controller, X (a) ... Positive signal line, X (a + 1) ... Negative signal line, SLC ... Scanning line controller, SLC2 ... Second scanning line controller, SWC ... Switch controller, SWC2 ... Second switch control Part, T1 ... non-scanning period, 100 ... liquid crystal display device, 101 ... liquid crystal display panel, 110 ... effective display part, 120 ... scanning line driving circuit, 130 ... signal line driving circuit, 140 ... flexible substrate, 150 ... circuit board

Claims (6)

An effective display section in which a plurality of display pixels are arranged;
A plurality of scanning lines arranged along a row in which the plurality of display pixels are arranged;
A plurality of signal lines arranged along a column in which the plurality of display pixels are arranged;
A scanning line driving circuit for scanning the plurality of scanning lines;
A signal line driving circuit for supplying an image signal to a display pixel via the plurality of signal lines;
A switch element provided between each of the signal lines having different polarities;
A scanning line control unit that causes the scanning line driving circuit to skip one or more scanning lines and a controller that includes a switch control unit that turns on the switch element during a non-scanning period of the scanning line driving circuit. Flat display device.   The controller is configured to turn on the switch element prior to a period during which an image signal is written to a scan line corresponding to a display pixel to which an image signal is next supplied among the plurality of scan lines to the scan line driving circuit. The flat display device according to claim 1, wherein the flat display device has a configuration in which scanning is performed. A second switch element provided on each of the plurality of signal lines;
The flat display device according to claim 1, wherein the controller is configured to turn off the second switch element during a period in which the switch element is turned on. An effective display section in which a plurality of display pixels are arranged;
A plurality of scanning lines arranged along a row in which the plurality of display pixels are arranged;
A plurality of signal lines arranged along a column in which the plurality of display pixels are arranged;
A scanning line driving circuit for scanning the plurality of scanning lines;
A signal line driving circuit for supplying an image signal to a display pixel via the plurality of signal lines;
A switch element provided between each of the signal lines having different polarities;
A driving method of a flat display device comprising: the scanning line driving circuit; and a controller for controlling the switch element,
The controller controls the scanning line driving circuit to scan the plurality of scanning lines at one or more intervals;
A driving method of a flat display device, wherein the scanning line driving circuit turns on the switch element to short-circuit between the signal lines having different polarities during a period in which the scanning line is in a non-scanning state.   The controller turns on the switch element prior to a period during which an image signal is written to a scanning line corresponding to a display pixel to which an image signal is next supplied among the plurality of scanning lines. The flat panel display device driving method according to claim 4, wherein scanning is performed during a period. A driving method of a flat display device further comprising a second switch element provided on each of the plurality of signal lines,
The flat panel display driving method according to claim 4, wherein the controller turns off the second switch element during a period in which the switch element is turned on.

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