JP2007199854A - Constant-current circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a constant-current circuit capable of outputting a stable constant current by equipping a compensation circuit for compensating the deviation of a reference current from an assumed value, due to manufacturing variations or fluctuation in the power supply voltages. <P>SOLUTION: The constant current circuit includes a current mirror circuit for supplying a mirror current that is proportional to the reference current; an operational amplifier for comparing the output potential of the current mirror circuit to reference potential; and a compensation circuit for canceling out the increase or decrease in the reference current depending on the result of comparison by the operational amplifier. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a constant current circuit, and more particularly to a constant current circuit that includes a compensation circuit that compensates for a deviation even when a reference current varies, and outputs a constant current.

  Conventionally, for example, when supplying a constant current required for an analog circuit or the like, a current mirror circuit is used.

  FIG. 3 is a schematic diagram showing an example of a conventional current mirror circuit.

  As shown in FIG. 3, the current mirror circuit 12 includes an NMOS transistor M11 having a gate terminal connected to a drain terminal and a source terminal connected to the ground GND, and a gate terminal commonly connected to the gate terminal of the NMOS transistor M11. An NMOS transistor M12 having a source terminal connected to the ground GND is formed. The drain terminal of the NMOS transistor M11 is an input terminal of the current mirror circuit 12 to which the reference current I11 generated by the reference current generation circuit 11 is input. Between the drain and source of the NMOS transistor M12, the reference terminal A current (hereinafter, mirror current) I12 obtained by mirroring the current I11 flows.

  FIG. 4 is a schematic diagram showing an example of the reference current generating circuit 11 shown in FIG.

  As shown in FIG. 4, the reference current generation circuit 11 includes, for example, a resistor R, an operational amplifier 22, an NMOS transistor M15, and PMOS transistors M16 and M17. One end of the resistor R is connected to the negative input terminal of the operational amplifier 22, and the other end is connected to the ground GND. A reference voltage Vref generated by a BGR (band gap reference) circuit (not shown) is input to the + input terminal of the operational amplifier 22. The NMOS transistor M15 has a source terminal connected to the one end of the resistor R, a gate terminal connected to the output terminal of the operational amplifier 22, and a drain terminal connected to the drain terminal of the PMOS transistor M16. The gate terminal and drain terminal of the PMOS transistor M16 are connected in common, and the source terminal is connected to the power supply voltage VDD. The source terminal of the PMOS transistor M17 is connected to the power supply voltage VDD, and the gate terminal is connected to the gate terminal of the PMOS transistor M16. Therefore, the PMOS transistors M16 and M17 form a current mirror circuit, and the reference current Iref is output from the drain terminal of the PMOS transistor M17.

  Here, since the reference voltage Vref is generated by the BGR circuit, it is a constant voltage that does not easily depend on temperature, power supply voltage, process, and the like. In the configuration shown in FIG. 4, if the gain of the operational amplifier 22 is sufficiently high, Vref = Vx can be guaranteed, and the reference current Iref is Vx / R (constant).

  In FIG. 3, an NMOS transistor M11 and an NMOS transistor M12 operate in a saturation region, and a reference current I11 and a mirror current I12 flowing between the drain and source of each transistor are expressed by the following equations (1) and (2). expressed.

Here, W11 and L11 are the channel width and channel length of the NMOS transistor M11, and W12 and L12 are the channel width and channel length of the NMOS transistor M12. Further, the mu _n is the mobility, Cox the gate capacitance per unit area, Vgs and Vthn are NMOS transistors M11, the gate-source voltage of M12 and the threshold. From Equation (1) and Equation (2)

The relationship holds.

  That is, the mirror current I12 of the NMOS transistor M12 has a value proportional to the size of the NMOS transistor 11 and the reference current I11. Here, if the sizes of the NMOS transistors are the same, the mirror current I12 of the NMOS transistor M12 becomes the reference current I11.

However, in general, the mirrored current may deviate from the assumed value due to variations in the manufacturing process and fluctuations in the power supply voltage. As means for solving such a problem, for example, Patent Document 1 discloses a current mirror circuit that makes input / output characteristics constant even when there are variations in manufacturing processes and fluctuations in power supply voltage or temperature. Patent Document 2 discloses a current mirror circuit that allows a constant current to flow through a load even when the power supply voltage or the resistance value of the electric load fluctuates.
JP-A-10-229310 Japanese Patent Laid-Open No. 9-307369

  According to the techniques disclosed in Patent Document 1 and Patent Document 2, although the mirror current with respect to the input current (reference current) of the current mirror circuit can be kept constant, a desired mirror current can be obtained due to variations and fluctuations in the reference current. May not be able to get.

  As described above, the reference current is a constant current if the reference voltage Vx (= Vref) used in the reference current generation circuit and the resistance R are constant, but in reality, the resistance R generated by PolySi or the like is about 20%. There is variation due to the process, and even if the reference voltage Vref is kept constant, if the resistance value varies, the reference current also varies. However, the conventional current mirror circuit cannot absorb such variations and fluctuations in the reference current and cannot obtain a desired mirror current.

  An object of the present invention is to provide a constant current circuit capable of solving a problem based on the prior art and including a compensation circuit that compensates for the deviation even when the reference current is deviated from an assumed value, thereby obtaining a desired constant current. Is to provide.

  In order to achieve the above object, the constant current circuit of the present invention includes a first MOS transistor having a gate terminal connected to a drain terminal and a reference current input to the drain terminal, and the same polarity as the first MOS transistor. A current mirror circuit having a second MOS transistor having a gate terminal connected to the gate terminal of the first MOS transistor and supplying a mirror current proportional to the reference current; And a compensation circuit that cancels the increase and decrease of the mirror current.

  Here, the compensation circuit includes an operational amplifier that compares the gate voltage of the first MOS transistor with a reference potential, and a current path that holds the mirror current constant according to a comparison result of the operational amplifier. preferable.

  Furthermore, the constant current circuit of the present invention includes a third MOS transistor having a gate terminal and a drain terminal connected in common to the drain terminal of the second MOS transistor, and the same polarity as the third MOS transistor. A fourth MOS transistor having a gate terminal connected to the gate terminal of the third MOS transistor, and the fourth MOS transistor further mirrors and outputs the mirror current flowing through the third MOS transistor; Is preferred.

  The current path preferably includes a fifth MOS transistor having a drain terminal connected to the drain terminal of the third MOS transistor and a gate terminal connected to the output of the operational amplifier.

  The constant current circuit of the present invention includes a current path that detects when the reference current increases or decreases due to fluctuations in the manufacturing process or the like and generates a current corresponding to the increase or decrease, and the reference current and the current flowing through the current path Is used to mirror the current. According to the constant current circuit of the present invention, it is possible to output a constant current even when the reference current is deviated from an assumed value due to variations in resistance, etc. constituting the reference current generation circuit or fluctuations in the power supply voltage. Become.

  Hereinafter, a constant current circuit of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a schematic diagram illustrating an internal configuration of a constant current circuit of the present invention.

  The constant current circuit 10 shown in FIG. 1 includes an NMOS transistor M1 having a gate terminal connected to a drain terminal and a source terminal connected to the ground GND, a gate terminal connected to the gate terminal of the NMOS transistor M1, and a source terminal connected to the ground GND. A current mirror circuit 2 similar to the conventional one is provided that includes an NMOS transistor M2 connected thereto. Further, the constant current circuit 10 of the present invention includes a PMOS transistor M4 having a drain terminal and a gate terminal connected in common and connected to the drain terminal of the NMOS transistor M2, a source terminal connected to the power supply voltage VDD, and a source terminal connected to the power supply voltage VDD. A current mirror circuit 5 comprising a PMOS transistor M5 connected to the power supply voltage VDD and having a gate terminal connected to the gate terminal of the PMOS transistor M4 is provided. Furthermore, the constant current circuit 10 of the present invention includes an operational amplifier 3 having a negative input terminal connected to the drain terminal of the NMOS transistor M1 and a positive input terminal connected to the reference voltage Vref, and a drain terminal connected to the drain terminal of the PMOS transistor M4. , A compensation terminal 4 comprising an NMOS transistor M3 having a source terminal connected to the ground GND and a gate terminal connected to the output terminal of the operational amplifier 3. The NMOS transistor M3 corresponds to a current path in the present invention, and the compensation circuit 4 compensates for variations and fluctuations in the reference current by this current path.

  Here, it is preferable that the reference voltage Vref as one input of the operational amplifier 3 is a fixed potential and is not easily influenced by the power supply voltage. For example, a reference generated by a bandgap reference (BGR) circuit is used. Electric potential is used.

  Here, the drain terminal of the NMOS transistor M1 is an input terminal of the constant current circuit 10 of the present invention to which the reference current I1 is input, and the constant current circuit 10 of the present invention outputs a constant current to the drain terminal of the PMOS transistor M5. Output terminal.

  The NMOS transistor M1 and the NMOS transistor M2 constitute a current mirror circuit 2 similar to the conventional one. As described above, the relationship represented by the following equation holds between the reference current I1 and the drain current I2 flowing through the NMOS transistor.

  In the current mirror circuit 2 having this configuration, the NMOS transistor M1 and the NMOS transistor M2 have the same size (W1 = W2, L1 = L2), and the NMOS transistor M2 is mirrored with a current having the same value as the reference current I1. To do. That is, the reference current I1 from the reference current generating circuit 1 is input to the drain terminal of the NMOS transistor M1, and the NMOS transistor M1 and the NMOS transistor M2 have the same size. -A current of I2 = I1 flows between the sources.

  Next, the operation of the compensation circuit constituting the constant current circuit 10 of the present invention will be described.

  As described above, in the compensation circuit 4, the gate terminal of the NMOS transistor M3 has the positive voltage input terminal connected to the reference voltage Vref and the negative voltage negative input terminal connected to the drain terminal of the NMOS transistor M1. Since the output terminal of the amplifier 3 is connected, a current I3 corresponding to the difference between the reference voltage Vref and the gate voltage of the NMOS transistor M1 flows through the NMOS transistor M3.

  Here, the reference current I1 (= mirror current I2) is expressed by the following equation.

From the equation (5), the gate-source voltage of the NMOS transistors M1 and M2 is

It becomes. The gate-source voltage of the NMOS transistor M3 is expressed by the following equation.

Therefore, the current I3 flowing between the drain and source of the NMOS transistor M3 is

It becomes.

  As can be seen from equation (8), the drain current flowing through the NMOS transistor M3 decreases as the reference current I1 increases, and increases as the reference current I1 decreases.

  The PMOS transistor M4 has a current I4 that is a sum of the current I2 = I1 flowing through the MOS transistor M2 and the current I3 flowing through the NMOS transistor M3, and the current value is set to an appropriate value for the reference voltage Vref, or , W3, and L3 can be arbitrarily set by appropriately setting the values.

  Further, the source terminal of the PMOS transistor M4 is connected to the power supply voltage VDD, the gate terminal and the drain terminal thereof are connected in common, the source terminal of the PMOS transistor M5 is the power supply voltage VDD, and the gate terminal is the drain terminal of the PMOS transistor M4. Therefore, the PMOS transistor M4 and M5 constitute a current mirror circuit 5. Therefore, a current of Iout = I4 is output from the drain terminal of the PMOS transistor M5.

  Here, it is assumed that the reference voltage Vref is set to an appropriate value in advance to obtain a desired output current, and the reference current varies in that state due to a manufacturing process or other causes.

  When the reference current I1 increases from a predetermined value, the drain voltage of the NMOS transistor M1 increases, and the output voltage of the operational amplifier 3 decreases according to the difference between the reference voltage Vref and the drain voltage. Then, the drain-source current I3 decreases due to the decrease in the gate voltage of the NMOS transistor M3, and the reference current I1 is the sum of the reference current I1 flowing through the PMOS transistor M4 and the current I3 of the PMOS transistor M3. The increased effect will be weakened and compensated.

  On the other hand, when the reference current I1 decreases below a predetermined value, the drain voltage of the NMOS transistor M1 decreases, and the output voltage of the operational amplifier 3 increases according to the difference between the reference voltage Vref and the drain voltage. This time, since the gate voltage of the NMOS transistor M3 increases, the current I3 increases, and the current I4, which is the sum of the reference current I1 flowing through the PMOS transistor M4 and the current I3 of the PMOS transistor M3, is affected by the decrease in the reference current I1. It will be weakened and compensated.

  FIG. 2 is an input / output characteristic curve obtained by simulation of how the output current Iout changes when the reference current I1 changes in the constant current circuit shown in FIG.

  In FIG. 2, the reference current I1 is varied from 30 μA to 50 μA. As can be seen from the figure, the output current Iout changes only a few percent, and it can be seen that the compensation circuit 4 constituting the constant current circuit 10 of the present invention compensates for the increase and decrease of the reference current I1.

  The constant current circuit of the present invention can output a desired stable constant current by providing a compensation circuit that compensates for this variation even if the reference current varies due to variations in manufacturing processes and variations in power supply voltage. It becomes.

  The present invention is basically as described above.

  Although the constant current circuit of the present invention has been described in detail above, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the spirit of the present invention.

It is the schematic of one Embodiment showing the internal structure of the constant current circuit of this invention. Input / output characteristic curve obtained by simulation of how the output current changes when the reference current changes in the constant current circuit shown in FIG. It is the schematic which shows an example of the conventional current mirror circuit. It is the schematic which shows an example of a reference current generation circuit.

Explanation of symbols

1, 11 Reference current generation circuit 2, 5, 12 Current mirror circuit 3, 22 Operational amplifier 4 Compensation circuit M1, M2, M3, M11, M12, M13, M14, M15 NMOS transistors M4, M5, M16, M17 PMOS transistor Vref Reference potential

Claims (4)

A first MOS transistor in which a gate terminal and a drain terminal are connected and a reference current is input to the drain terminal; and a gate terminal having the same polarity as the first MOS transistor and the gate terminal of the first MOS transistor A current mirror circuit having a second MOS transistor connected and supplying a mirror current proportional to the reference current;
A constant current circuit, comprising: a compensation circuit that cancels an increase / decrease in the mirror current according to an increase / decrease in the reference current.   The compensation circuit includes an operational amplifier that compares a gate voltage of the first MOS transistor with a reference potential, and a current path that holds the mirror current constant according to a comparison result of the operational amplifier. The constant current circuit according to claim 1.   A third MOS transistor having a gate terminal and a drain terminal commonly connected to the drain terminal of the second MOS transistor, and the same polarity as the third MOS transistor, and the gate terminal of the third MOS transistor The fourth MOS transistor connected to a gate terminal, wherein the fourth MOS transistor further mirrors and outputs the mirror current flowing through the third MOS transistor. Constant current circuit.   The current path includes a fifth MOS transistor having a drain terminal connected to a drain terminal of the third MOS transistor and a gate terminal connected to an output of the operational amplifier. Constant current circuit.

Images