JP2007173558A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for reducing the used amount of a C<SB>5</SB>F<SB>8</SB>gas in an etching treatment using the C<SB>5</SB>F<SB>8</SB>gas as an etching gas. <P>SOLUTION: In a dry etching device for dry-etching a silicon-oxide film using a C<SB>5</SB>F<SB>8</SB>gas as an etching gas, a stabilization step immediately before a STEP 3 of performing actual etching operation is divided into two steps, that is, a STEP 1 of not introducing the C<SB>5</SB>F<SB>8</SB>gas and a STEP 2 of introducing the C<SB>5</SB>F<SB>8</SB>gas. The flow amount of the C<SB>5</SB>F<SB>8</SB>gas in the STEP 2 is set to be equal to the flow amount of the C<SB>5</SB>F<SB>8</SB>gas in the STEP 3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a dry etching process in the manufacturing process of a semiconductor integrated circuit device.

Japanese Patent Application Laid-Open No. 2004-281528 (Patent Document 1) describes damage to various components in a chamber by performing plasma discharge after adjusting the flow rate and pressure of a mixed gas such as C ₅ F ₈ , Ar, and O _2. A plasma processing apparatus capable of preventing the above is disclosed.

Japanese Patent Laid-Open No. 2002-231596 (Patent Document 2) automatically controls a series of processes for performing etching by performing plasma discharge after adjusting the flow rate of a mixed gas such as C ₅ F ₈ , Ar and O _2. A manufacturing method and a manufacturing system of a semiconductor device are disclosed that can reduce the cost of manufacturing a semiconductor device and improve the operating rate of the manufacturing device.
JP 2004-281528 A JP 2002-231596 A

  The present inventor is examining a technique for etching a thin film mainly composed of silicon oxide deposited on a semiconductor substrate (hereinafter simply referred to as a substrate) with high processing accuracy in a manufacturing process of a semiconductor integrated circuit device. Among them, the present inventors have found the following problems.

That is, the present inventors changed the etching gas from C ₄ F ₈ gas to C ₅ F ₈ gas for the purpose of improving the processing accuracy when etching the thin film mainly composed of silicon oxide deposited on the substrate. I'm considering doing that. When performing the etching process, before the actual etching process is performed, a stabilization process for stabilizing the pressure in the chamber of the etching apparatus and the flow rate of the etching gas flowing into the chamber is performed for a predetermined time. Etching gas is used even during this stabilization process, and C ₅ F ₈ gas is more expensive than C ₄ F ₈ gas, and therefore, it is a problem to reduce the amount of etching gas used.

One object of the present invention is to provide a technique capable of reducing the amount of C ₅ F ₈ gas used in an etching process using C ₅ F ₈ gas as an etching gas.

  The outline of one representative one of the inventions disclosed in the present application will be briefly described as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps:
(A) a step of transporting a semiconductor substrate on which a first insulating film mainly composed of silicon oxide is formed on a main surface to a processing chamber of an etching apparatus;
(B) a step of performing a first stabilization process by flowing a first etching gas into the processing chamber in which the semiconductor substrate is transferred;
(C) after the first stabilization process, flowing the first etching gas and the second etching gas into the processing chamber to perform a second stabilization process;
(D) A step of etching the first insulating film while keeping the inside of the processing chamber in the atmosphere during the second stabilization process after the second stabilization process.

(2) A method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps:
(A) a step of transporting a semiconductor substrate on which a first insulating film mainly composed of silicon oxide is formed on a main surface to a processing chamber of an etching apparatus;
(B) a step of performing a first stabilization process by flowing a first etching gas into the processing chamber in which the semiconductor substrate is transferred;
(C) A step of etching the first insulating film by flowing the first etching gas and the second etching gas into the processing chamber after the first stabilization processing.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In a dry etching apparatus that dry-etches an insulating film mainly composed of silicon oxide deposited on a substrate, the stabilization process immediately before the etching process is divided into two stages. During the first stabilization process, there is no etching gas in the processing chamber. In the second stabilization process after the first stabilization process, the etching gas, the dilution gas, and the additive gas are introduced into the processing chamber. Thereby, the usage-amount of the etching gas at the time of a stabilization process can be reduced.

  Before describing the present invention in detail, the meaning of terms in the present application will be described as follows.

  A wafer is a single crystal silicon substrate (generally a substantially circular shape) used for manufacturing integrated circuits, an SOI (Silicon On Insulator) substrate, an epitaxial substrate, a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, etc. These composite substrates are referred to. The term “semiconductor integrated circuit device” as used herein refers not only to a semiconductor integrated circuit device such as a silicon wafer or a sapphire substrate, but also to a TFT (Thin Film Transistor) unless otherwise specified. ) And STN (Super-Twisted-Nematic) liquid crystal or the like made on other insulating substrates such as glass.

  The device surface is a main surface of a wafer on which a device pattern corresponding to a plurality of chip regions is formed by lithography.

  The resist pattern refers to a film pattern obtained by patterning a photosensitive resin film (resist film) by a photolithography technique. This pattern includes a simple resist film having no opening at all for the portion. In general, the photosensitive resin film and photolithography are based on light, but in this application, for the sake of convenience, a resist sensitive to an electromagnetic wave having a wavelength shorter than that of an electron beam or ultraviolet light is used unless otherwise specified. Including pattern forming technology.

  A parallel plate type reactive ion etching apparatus is a reaction generated by applying high frequency power to one of parallel plate electrodes installed in parallel while sending an etching gas into an etching chamber (chamber) and exhausting from one side. An etching apparatus that etches a wafer disposed on an electrode or a thin film deposited on the wafer using a reactive gas plasma.

The perfluorocarbon gas refers to a gas represented by C _m F _n (m and n are predetermined integers).

  A silicon oxide film is a PSG (Phosphor Silicate Glass) film or BPSG (Boro-Phospho Silicate Glass) film formed by a coating method or a thermal CVD (Chemical Vapor Deposition) method, or an oxidation formed by a plasma CVD method. A thin film containing silicon oxide as a main component, such as a silicon film and a SiOC film.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. In addition, when referring to the constituent elements in the embodiments, etc., “consisting of A” and “consisting of A” do not exclude other elements unless specifically stated that only the elements are included. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In addition, when referring to materials, etc., unless specified otherwise, or in principle or not in principle, the specified material is the main material, and includes secondary elements, additives It does not exclude additional elements. For example, unless otherwise specified, the silicon member includes not only pure silicon but also an additive impurity, a binary or ternary alloy (for example, SiGe) having silicon as a main element.

  In addition, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  In the drawings used in the present embodiment, even a plan view may be partially hatched to make the drawings easy to see.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a schematic explanatory diagram of a dry etching apparatus used for manufacturing the semiconductor integrated circuit device of the first embodiment.

  The dry etching apparatus PPRE used for manufacturing the semiconductor integrated circuit device according to the first embodiment is a parallel plate type reactive ion etching apparatus. As shown in FIG. 1, the dry etching apparatus PPRE is formed of a loading chamber TR, a transfer chamber HR, a processing chamber (chamber) SR, and the like. One or more substrates (semiconductor wafers (hereinafter simply referred to as “wafers”)) to be dry-etched by this dry etching apparatus PPRE are stored in a wafer storage container such as a FOUP (Front Opening Unified Pod) or a wafer cassette. In this state, it is transferred to the input chamber TR. The robot arm RA disposed in the transfer chamber HR takes out the substrates one by one from the wafer storage container transferred to the loading chamber TR and carries them to the processing chamber SR. A predetermined dry etching process (for example, dry etching of a silicon oxide film) is performed on the substrate carried to the processing chamber SR.

  FIG. 2 is a schematic explanatory diagram of the processing chamber SR, and FIG. 3 is an explanatory diagram showing a detailed structure of the processing chamber SR.

  In the processing chamber SR, an upper electrode UE, a lower electrode BE, a shield ring SHR, an inner focus ring IFR, an outer focus ring OFR, a cover ring CR, and the like are arranged.

  For example, the upper electrode UE formed of a material containing Si (silicon) as a main component is disposed relatively above the processing chamber SR and has a function of injecting an etching gas and plasma into the processing chamber SR. The upper electrode UE is electrically connected to the ground potential.

  For example, the substrate 1 is placed on the lower electrode BE made of a material whose main component is ceramic, and an etching process is performed under a situation where high-frequency power is applied from the high-frequency power source RPS. Further, the lower electrode BE may be obtained by applying polyimide coating to a material mainly composed of Al (aluminum).

  For example, the shield ring SHR formed of a material mainly composed of quartz has a function of controlling a plasma generation region in the processing chamber SR.

  For example, the inner focus ring IFR formed of a material containing silicon as a main component has a function of receiving plasma by spreading it to the outer periphery.

  For example, the outer focus ring OFR and the cover CR formed of a material whose main component is quartz have a function of controlling a region that receives plasma.

In the processing chamber SR, for example, the silicon oxide film deposited on the substrate is etched. In the first embodiment, the etching gas used for etching the silicon oxide film is, for example, C ₅ F ₈ gas that is a perfluorocarbon gas, Ar (argon) gas that is a dilution gas, and O ₂ (oxygen) that is an additive gas. The flow rates of these gases individually into the processing chamber SR are controlled. That is, C ₅ F ₈ gas, Ar gas, and O ₂ gas are respectively introduced from individual pipes PP1, PP2, PP3, and mass flow controllers MFC1, MFC2 having functions as valves provided in the pipes PP1, PP2, PP3, respectively. , MFC3 controls the flow rate. The C ₅ F ₈ gas, Ar gas, and O ₂ gas introduced into the pipes PP1, PP2, and PP3 merge in the pipe PP4 connected to the pipes PP1, PP2, and PP3, and enter the processing chamber SR from above the processing chamber SR. To be introduced.

  The etching gas used for the etching process is discharged out of the processing chamber SR from the pipe PP5. The pipe PP5 is provided with an APC (Auto Pressure Control) valve APC and a pump PMP having a function as a valve, and the flow rate and pressure when the etching gas is discharged out of the processing chamber SR by the APC valve APC and the pump PMP. Be controlled.

  Next, the manufacturing process of the semiconductor integrated circuit device using the dry etching apparatus according to the first embodiment as described with reference to FIGS. 1 to 3 will be described in the order of the processes with reference to FIGS. The semiconductor integrated circuit device according to the first embodiment has, for example, a p-channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor).

  First, as shown in FIG. 4, the element isolation portion 2 is formed on the main surface (element formation surface) of the substrate 1. This element isolation part 2 can be formed as follows, for example. First, the main surface of the substrate 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is etched to form a groove. Next, the substrate 1 is thermally oxidized at about 1000 ° C. to form a thin silicon oxide film (not shown) on the inner wall of the groove. This silicon oxide film is formed to recover the damage caused by the dry etching generated on the inner wall of the groove and to relieve the stress generated at the interface between the silicon oxide film embedded in the groove and the substrate 1 in the next step. Is. Subsequently, a silicon oxide film 3 is deposited on the substrate 1 including the inside of the trench as an insulating film by, for example, a CVD (Chemical Vapor deposition) method. Next, the element isolation portion 2 is formed by polishing the silicon oxide film 3 on the upper portion of the groove by chemical mechanical polishing (CMP), and leaving the silicon oxide film 3 in the groove portion.

  Next, an impurity having an n-type conductivity (for example, P (phosphorus)) is ion-implanted into the substrate 1, and then the substrate 1 is subjected to a heat treatment to diffuse the impurity, thereby forming an n-type well 5 in the substrate 1. To do. At this time, active regions which are main surfaces of the n-type well 5 are formed in the substrate 1, and these active regions are surrounded by the element isolation portion 2.

  Next, the surface of the substrate 1 (n-type well 5) is wet-cleaned using, for example, a hydrofluoric acid-based cleaning solution, and then the substrate 1 is heat treated to act as a gate insulating film on each surface of the n-type well 5. A clean gate oxide film 7 is formed.

  Subsequently, a low resistance polycrystalline silicon film having a film thickness of about 100 nm is deposited on the substrate 1 as a conductive film by the CVD method, for example. Next, the polycrystalline silicon film is etched using a photoresist film patterned by photolithography as a mask, thereby forming a gate electrode 8 made of the polycrystalline silicon film. The gate electrode 8 is patterned so that a part thereof extends on the element isolation part 2.

  Next, after depositing a silicon oxide film on the substrate 1 by a CVD method, the silicon oxide film is anisotropically etched by a reactive ion etching (RIE) method, thereby forming a sidewall of the gate electrode 8. Sidewall spacers 9 are formed on the substrate. Subsequently, a p-type semiconductor region (source, drain) 10 of the p-channel type MISFET Qp is formed by implanting an impurity having a p-type conductivity (for example, B (boron)) on the n-type well 5. An LDD (Lightly Doped Drain) structure is formed by forming a low-concentration p-type semiconductor region before forming the sidewall spacer 9 and forming a high-concentration p-type semiconductor region after forming the sidewall spacer 9. May be. The p-channel type MISFET Qp is completed through the steps so far. Note that an n-channel MISFET may be formed in a region not shown in FIG. In the n-channel MISFET, a p-type well is formed by introducing an impurity (for example, B) having a p-type conductivity into the substrate 1 and performing a heat treatment, and after forming a gate electrode similar to the gate electrode 8 described above. The n-type semiconductor region (source, drain) can be formed by implanting an n-type conductivity impurity (for example, P or As (arsenic)) into the p-type well.

Subsequently, after cleaning the surface of the substrate 1, a Co (cobalt) film and a Ti (titanium) film are sequentially deposited on the substrate 1 by a sputtering method. Next, heat treatment is performed on the substrate 1 to form a CoSi ₂ layer 12 as a silicide layer on the p-type semiconductor region 10 and the gate electrode 8. In the first embodiment, a means for forming such a CoSi ₂ layer 12 is exemplified. Instead of forming the CoSi ₂ layer 12, Ni (nickel), W (tungsten), Mo (molybdenum), Ti A refractory metal silicide layer such as a NiSi _x layer, a WSi _x layer, a MoSi _x layer, a TiSi _x layer, or a TaSi _x layer may be formed using (titanium) or Ta (tantalum).

Next, after removing the unreacted Co film and Ti film by etching, the substrate 1 is subjected to heat treatment to reduce the resistance of the CoSi ₂ layer 12.

  Next, a silicon nitride film 17 having a thickness of about 50 nm is deposited on the substrate 1 by, eg, CVD. The silicon nitride film 17 serves as an etching stopper layer when forming a contact hole described later.

  Subsequently, for example, a PSG film (first insulating film) 20 is applied as an interlayer insulating film on the silicon nitride film 17, and heat treatment is performed to flatten the film. Next, a silicon oxide film (first insulating film) 21 is deposited on the PSG film 20 by plasma CVD. Further, the deposition of the PSG film 20 is omitted, and after the silicon oxide film 21 is deposited on the silicon nitride film 17, the surface of the silicon oxide film 21 is polished by CMP to flatten the surface. Also good. Next, a silicon nitride film 22 is deposited on the silicon oxide film 21 by, eg, CVD.

Next, as shown in FIG. 5, the silicon nitride film 22 is patterned by etching using a photoresist film as a mask. Subsequently, after removing the photoresist film, the silicon oxide film 21 and the PSG film 20 are sequentially etched using the remaining silicon nitride film 22 as a mask to form an opening. Next, by etching the silicon nitride film 22 and the silicon nitride film 17 appearing at the bottom of the opening, a contact hole 25 is formed on the p-type semiconductor region 10 and on the gate electrode 8 of the n-channel type MISFET Qp. The bottom of the contact hole 25 reaching the CoSi ₂ layer 12 on the gate electrode 8 reaches a p-type semiconductor region 10 (CoSi ₂ layer 12 on the p-type semiconductor region 10) that is partially planar and adjacent to the gate electrode 8.

  Here, FIG. 6 is a diagram showing processing condition settings of the dry etching apparatus of the first embodiment (see FIGS. 1 to 3) during the etching process of the silicon oxide film 21, the PSG film 20, and the silicon nitride film 17. It is a figure and has shown the numerical value per process of the board | substrate 1 of 1 sheet. In FIG. 6, the same numerical value is entered for each code in the column where the codes (a) to (j) are described. As shown in FIG. 6, during the etching process of the silicon oxide film 21, the PSG film 20, and the silicon nitride film 17, the processing condition setting of the dry etching apparatus of the first embodiment is switched in 10 steps (STEP). The step described as “stable” in the step end condition (hereinafter referred to as the stabilization step) waits for the etching process until the pressure in the processing chamber SR (see FIG. 2) and the flow rate of the etching gas reach predetermined values. The step is a step, and the time described in the step processing time is set as the maximum standby time, and the process proceeds to the next step as soon as the pressure and the etching gas flow rate in the processing chamber SR reach predetermined values (values at the time of etching). If the pressure in the processing chamber SR and the etching gas flow rate do not reach the predetermined values even after the step processing time, the operation of the dry etching apparatus is stopped. A step described as “time” in the step end condition (hereinafter referred to as a processing step) is a step in which the etching process is actually performed, and the dry etching process is performed for the time described in the step processing time. Is. In STEP 2, the residue of the photoresist film used as a mask when the silicon nitride film 22 is patterned is removed. In STEP 5, the silicon oxide film 21 and PSG film 20 are etched. In STEP 7, the silicon oxide film 21 and PSG are etched. Residues generated during the etching of the film 20 are removed, and in STEP 9, the silicon nitride film 17 is etched.

In the first embodiment, the etching of the silicon oxide film 21 and the PSG film 20 uses C ₅ F ₈ gas (second etching gas) as an etching gas, Ar gas (first etching gas) as a dilution gas, and O 2 A mixed gas using _two gases (first etching gas) as an additive gas for adjusting etching characteristics is used. C ₅ F ₈ gas can etch a silicon oxide-based film with higher processing accuracy than C ₄ F ₈ gas. By the way, according to an experiment conducted by the present inventor, C ₅ F ₈ gas and Ar gas are used at the same flow rate conditions as STEP 5 in the stabilization step immediately before STEP 5 in which the silicon oxide film 21 and the PSG film 20 are etched. When O ₂ gas was introduced, it took about 15 seconds for the pressure in the processing chamber SR and the flow rate of the etching gas to reach predetermined values (values at the time of etching). On the other hand, in the step of Embodiment 1 shown in FIG. 6, the stabilization step (first stabilization process) of STEP 3 in which the introduction of C ₅ F ₈ gas is not performed is about 15 seconds, and C ₅ F ₈ gas is used. The stabilization step (second stabilization process) of STEP 4 in which the above-described introduction was performed was about 5 seconds. Here, the flow rate of Ar gas and _{O 2} gas in STEP3 (first flow rate) is the same as the flow rate of Ar gas and _{O 2} gas in STEP4 (second flow rate), _C 5 F in STEP4 the flow rate of ₈ gas is the same as the flow rate of _C 5 _{F 8} gas in STEP5. In the first embodiment, in the stabilization step (STEP 3 and STEP 4) and the processing step (STEP 5), the chamber pressure (pressure in the processing chamber SR) is kept constant at about 2.7 Pa. That is, according to the first embodiment, it is possible to minimize the amount of C ₅ F ₈ gas used that is more expensive than C ₄ F ₈ gas in the stabilization step. In addition, according to the first embodiment, compared to the case where the amount of C ₅ F ₈ gas used in the stabilization step is the same as the amount of C ₅ F ₈ gas used in the processing step, in the stabilization step. Since the usage time of C ₅ F ₈ gas can be reduced by about 10 seconds, if the unit price of C ₅ F ₈ gas (molecular weight 212) is about 102.4 yen, it costs about 1.3 yen per substrate. Can be saved. If the silicon oxide film 21 and the PSG film 20 are etched on 550 substrates 1 in one day, it is possible to save about 250,000 yen per year.

  Next, as shown in FIG. 7, for example, a Ti film having a thickness of about 10 nm and a TiN film having a thickness of about 50 nm are sequentially deposited as a barrier film on the silicon oxide film 21 including the inside of the contact hole 25 by, for example, sputtering. Then, heat treatment is performed at 500 to 700 ° C. for 1 minute. Next, for example, a W film is deposited as a conductive film on the silicon oxide film 21 and the barrier film by a CVD method, and the contact hole 25 is buried with the W film. Next, the W film, the TiN film, and the Ti film on the silicon oxide film 21 are removed by the etch back method or the CMP method, and the W film, the TiN film, and the Ti film are left in the contact hole 25. As a result, a plug 26 is formed in the contact hole 25 using the TiN film and the Ti film as a barrier film and the W film as a main conductive layer.

  Next, as shown in FIG. 8, a W film is deposited on the silicon oxide film 21 and the plug 26 by, eg, sputtering. Subsequently, the W film is patterned by dry etching using the photoresist film as a mask to form the wiring 27.

  Next, as shown in FIG. 9, an interlayer insulating film 38 is formed by depositing a silicon oxide film on the substrate 1. Subsequently, the interlayer insulating film 38 is etched using a photoresist film patterned by the photolithography technique as a mask to form a contact hole 39 reaching the wiring 27.

  Subsequently, for example, a Ti film having a thickness of about 10 nm and a TiN film having a thickness of about 50 nm are sequentially deposited as barrier films on the interlayer insulating film 38 including the inside of the contact hole 39 by, for example, a sputtering method. Heat treatment for a minute. Next, for example, a W film is deposited as a conductive film on the barrier film and the interlayer insulating film 38 by, eg, CVD, and the contact hole 39 is filled with the W film. Thereafter, the Ti film, the TiN film, and the W film on the interlayer insulating film 38 are removed, and the Ti film, the TiN film, and the W film are left in the contact hole 39, thereby forming plugs 42 in the contact holes 39, respectively. .

  Next, as shown in FIG. 10, a Ti film, an Al (aluminum) film, and a titanium nitride film are sequentially deposited from the lower layer as a conductive film on the interlayer insulating film 38. Subsequently, the Ti film, the Al film, and the titanium nitride film are etched using the photoresist film patterned by the photolithography technique as a mask, thereby forming the wiring 44.

Next, as shown in FIG. 11, for example, a SiON film (first insulating film) 45 having a thickness of about 25 nm and a silicon oxide film (first insulating film) having a thickness of about 750 nm are formed on the substrate 1 by plasma CVD. 46 is deposited. Subsequently, the silicon oxide film 46 and the SiON film 45 are etched using a photoresist film patterned by photolithography as a mask, thereby forming a contact hole 48 reaching the wiring 44. In the first embodiment, also in the etching process of the silicon oxide film 46 and the SiON film 45, the C ₅ F ₈ gas is used as an etching gas and the Ar gas is diluted as in the etching process of the silicon oxide film 21 and the PSG film 20. A mixed gas in which O ₂ gas is used as an additive gas for adjusting etching characteristics is used. Thereby, the contact hole 46 can be processed with high accuracy.

Here, FIG. 12 shows the processing condition setting of the dry etching apparatus (see FIGS. 1 to 3) of the first embodiment at the time of etching the silicon oxide film 46 and the SiON film 45 (processing of the contact hole 46). It is explanatory drawing shown, and has shown the numerical value per process of the board | substrate 1 of 1 sheet. In FIG. 12, the same numerical value is entered for each code in the column where the codes (k) to (o) are written. As shown in FIG. 12, in the etching process of the silicon oxide film 46 and the SiON film 45, as in the etching process of the silicon oxide film 21 and the PSG film 20, the stabilization step immediately before the processing step (STEP 3) is performed. performing C ₅ F ₈ does not perform the introduction of the gas STEP1 is divided into two stages (first stabilization process) and the introduction of _C 5 _{F 8} gas STEP2 (second stabilization process). The flow rate of C ₅ F ₈ gas in STEP 2 is the same as the flow rate of C ₅ F ₈ gas in STEP 3. According to the experiment conducted by the present inventor, when C ₅ F ₈ gas, Ar gas, and O ₂ gas are introduced under the same flow rate conditions as STEP 3 in the stabilization step immediately before STEP 3, the inside of the processing chamber SR It took about 15 seconds for the pressure and the etching gas flow rate to reach predetermined values (values at the time of etching). On the other hand, in the first step of this embodiment is shown in FIG. _12, C 5 _{F 8} STEP1 is not performed introduction of gas is about 15 _seconds, STEP2 to deploying C 5 _{F 8} gas was about 5 seconds . Here, the flow rate of Ar gas and _{O 2} gas in STEP1 (first flow rate) is the same as the flow rate of Ar gas and _{O 2} gas in STEP2 (second flow rate), _C 5 F in STEP2 the flow rate of ₈ gas is the same as the flow rate of _C 5 _{F 8} gas in STEP3. In the first embodiment, in the stabilization step (STEP 1 and STEP 1) and the processing step (STEP 3), the chamber pressure (pressure in the processing chamber SR) is kept constant at about 5.3 Pa. That is, according to the first embodiment, even in the stabilization step during the etching process of the silicon oxide film 46 and the SiON film 45, the amount of expensive C ₅ F ₈ gas used is minimized compared to the C ₄ F ₈ gas. It can be suppressed to the limit. Further, according to the first embodiment, the stabilization step in the etching process of the silicon oxide film 46 and the SiON film 45 is also performed in the stabilization step as in the etching process of the silicon oxide film 21 and the PSG film 20. Compared to the case where the amount of C ₅ F ₈ gas used is the same as the amount of C ₅ F ₈ gas used in the processing step, the time for using C ₅ F ₈ gas in the stabilization step can be reduced by about 10 seconds. Accordingly, if the etching process of the silicon oxide film 46 and the SiON film 45 is performed on 1700 substrates 1 in one day, the cost of about 750,000 yen can be saved annually.

  Next, as shown in FIG. 13, a plug 50 is formed in the contact hole 48. The plug 50 can be formed, for example, by a process similar to the process of forming the plug 42.

  Subsequently, the semiconductor integrated circuit device according to the first embodiment is manufactured by forming the wiring 52 connected to the plug 50 on the silicon oxide film 46. The wiring 52 can be formed by a process similar to the process of forming the wiring 44, for example. Further, by repeating the same process as the process of forming the SiON film 45, the silicon oxide film 46, the plug 50, and the wiring 52, the wirings may be formed in multiple layers.

In the first embodiment described above, the case where C ₅ F ₈ gas is used as the etching gas for etching the silicon oxide film has been described. However, C ₄ F ₆ gas other than C ₅ F ₈ gas and CHF _{3 are used.} Even when a gas or the like is used as an etching gas, the stabilization step can be divided into two stages: a step in which no etching gas is introduced and a step in which an etching gas is introduced. Thereby, the amount of etching gas used in the stabilization step can be reduced. In particular, CHF ₃ gas is strongly desired to be reduced because it has a large global warming potential, and application of the first embodiment can contribute to the reduction of the amount of use.

(Embodiment 2)
Next, the second embodiment will be described.

  In the second embodiment, the dry etching process of the silicon oxide film (PSG film 20, silicon oxide film 21, and silicon oxide film 46) by the dry etching apparatus described with reference to FIGS. 1 to 3 in the first embodiment. Is performed under conditions different from those of the first embodiment. That is, in the first embodiment, the chamber pressure (pressure in the processing chamber SR) is kept constant and the flow rate of the dilution gas (Ar gas) is kept constant in the stabilization step and the processing step. In the second embodiment, the chamber pressure is made higher than the chamber pressure in the processing step in a part of the stabilization step, and the flow rate of the dilution gas is made lower than the flow rate of the dilution gas in the process step. is there.

For example, FIG. 14 shows the present embodiment during the etching process (processing of the contact hole 46 (see FIG. 11)) of the silicon oxide film 46 (see FIG. 11) and the SiON film 45 (see FIG. 11) in the second embodiment. It is explanatory drawing which shows the process condition setting of the dry etching apparatus (refer FIGS. 1-3) of the form 1, and has shown the numerical value per process of the board | substrate 1 of 1 sheet. In FIG. 14, the same numerical value is entered for each code in the column in which the codes (k) to (q) are written. As shown in FIG. 14, also in the second embodiment, and STEP2 of the introduction of the preceding is not performed introduction of _C 5 _{F 8} gas stabilization step STEP1 and _C 5 _{F 8} gas in the processing step (STEP3) This is divided into two stages. The flow rate of C ₅ F ₈ gas in STEP 2 is the same as the flow rate of C ₅ F ₈ gas in STEP 3. Further, as described above, the chamber pressure in STEP 1 (about 6.7 Pa (first pressure)) is set higher than the chamber pressure in STEP 2 and STEP 3 (about 5.3 Pa (second pressure)), and STEP 1 Ar gas flow rate (third flow rate (q)) is lower than Ar gas flow rate (about 81 × 10 ⁻² Pa · m ³ / s (fourth flow rate, fifth flow rate)) in STEP2 and STEP3. Set. Thereby, STEP1 can be completed in about 12 seconds, and STEP2 can be completed in about 5 seconds. That is, according to the second embodiment, STEP 1 can be shortened by about 3 seconds as compared with the first embodiment. As a result, the manufacturing period of the semiconductor integrated circuit device according to the second embodiment can be shortened.

  Further, as shown in FIG. 15, the stabilization step corresponding to STEP2 in FIG. 14 may be omitted. This is based on the fact that the discharge in the processing chamber SR is not stable for a few seconds after the processing step (STEP 2 in FIG. 15) is started. STEP 2 in FIG. The stabilization step corresponding to is performed. Thereby, in the processing condition shown in FIG. 15, the stabilization step can be further shortened by about 5 seconds compared to the processing condition shown in FIG.

  According to the second embodiment described above, the same effect as in the first embodiment can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

The manufacturing method of a semiconductor integrated circuit device of the present invention can be applied to a manufacturing process of a semiconductor integrated circuit device including a dry etching process using a perfluorocarbon gas such as C ₅ F ₈ gas as an etching gas.

It is a schematic explanatory drawing of the dry etching apparatus used for manufacture of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a schematic explanatory drawing of the processing chamber which the dry etching apparatus shown in FIG. 1 has. It is explanatory drawing which shows the detail of the process chamber which the dry etching apparatus shown in FIG. 1 has. It is principal part sectional drawing explaining the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. FIG. 5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 4; It is explanatory drawing which shows the process conditions in the etching process in the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. FIG. 6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 5; FIG. 8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7; FIG. 9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8; FIG. 10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 10; It is explanatory drawing which shows the process conditions in the etching process in the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. FIG. 12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 11; It is explanatory drawing which shows the process conditions in the etching process in the manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is explanatory drawing which shows the process conditions in the etching process in the manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Element isolation part 3 Silicon oxide film 5 N-type well 7 Gate oxide film 8 Gate electrode 10 P-type semiconductor region (source, drain)
12 CoSi ₂ layer 17 Silicon nitride film 20 PSG film (first insulating film)
21 Silicon oxide film (first insulating film)
22 Silicon nitride film 25 Contact hole 26 Plug 38 Interlayer insulating film 39 Contact hole 42 Plug 44 Wiring 45 SiON film (first insulating film)
46 Silicon oxide film (first insulating film)
48 Contact hole 50 Plug 51 Wiring APC APC valve BE Lower electrode CR Covering HR Transfer chamber IFR Inner focus ring MFC1, MFC2, MFC3 Mass flow controller OFR Outer focus ring PMP Pump PP1, PP2, PP3, PP4, PP5 Piping PPRE Dry etching device Qp p-channel MISFET
RA Robot arm RPS High frequency power supply SHR Shield ring SR Processing room TR Input room UE Upper electrode

Claims (13)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) a step of transporting a semiconductor substrate on which a first insulating film mainly composed of silicon oxide is formed on a main surface to a processing chamber of an etching apparatus;
(B) a step of performing a first stabilization process by flowing a first etching gas into the processing chamber in which the semiconductor substrate is transferred;
(C) after the first stabilization process, flowing the first etching gas and the second etching gas into the processing chamber to perform a second stabilization process;
(D) A step of etching the first insulating film while keeping the inside of the processing chamber in the atmosphere during the second stabilization process after the second stabilization process. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
The second etching gas contains a perfluorocarbon gas as a main component. The method of manufacturing a semiconductor integrated circuit device according to claim 2,
The second etching gas contains C ₅ F ₈ gas as a main component. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
The first flow rate of the first etching gas during the first stabilization process is the same as the second flow rate of the first etching gas during the second stabilization process. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
The first pressure in the processing chamber during the first stabilization processing is higher than the second pressure in the processing chamber during the second stabilization processing and etching of the first insulating film. In the manufacturing method of the semiconductor integrated circuit device according to claim 5,
The first etching gas includes a dilution gas and an additive gas;
The third flow rate of the dilution gas during the first stabilization process is smaller than the fourth flow rate of the dilution gas during the second stabilization process. The method of manufacturing a semiconductor integrated circuit device according to claim 6.
The dilution gas is mainly composed of argon. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) a step of transporting a semiconductor substrate on which a first insulating film mainly composed of silicon oxide is formed on a main surface to a processing chamber of an etching apparatus;
(B) a step of performing a first stabilization process by flowing a first etching gas into the processing chamber in which the semiconductor substrate is transferred;
(C) A step of etching the first insulating film by flowing the first etching gas and the second etching gas into the processing chamber after the first stabilization processing. The method of manufacturing a semiconductor integrated circuit device according to claim 8.
The second etching gas contains a perfluorocarbon gas as a main component. In the manufacturing method of the semiconductor integrated circuit device according to claim 9,
The second etching gas contains C ₅ F ₈ gas as a main component. The method of manufacturing a semiconductor integrated circuit device according to claim 8.
The first pressure in the processing chamber during the first stabilization process is higher than the second pressure in the processing chamber during the etching of the first insulating film. In the manufacturing method of the semiconductor integrated circuit device according to claim 11,
The first etching gas includes a dilution gas and an additive gas;
The third flow rate of the dilution gas during the first stabilization process is smaller than the fifth flow rate of the dilution gas during the etching of the first insulating film. The method of manufacturing a semiconductor integrated circuit device according to claim 12,
The dilution gas is mainly composed of argon.

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