JP2007165928A - Semiconductor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To contribute to improvement in yield and reliability by reducing the number of assembling steps by mounting several types of semiconductor integrated circuit chips on a module substrate. <P>SOLUTION: Mounting pads are grouped and arranged on a module substrate (10) so as to be able to mount semiconductor integrated circuit chips having substantially the same heights, for example, the semiconductor integrated circuit chips are arranged in a line for each group of the same types of semiconductor integrated circuit chips. Then, anisotropic conductive films (66A, 66B) are adhered for each grouped mounting pad, and a mounting pattern and a bump electrode of a semiconductor integrated circuit chip are conductively connected via the adhered anisotropic conductive film. Thereby, a plurality of the semiconductor integrated circuit chips can be collectively pressure bonded with heat to the anisotropic conductive film for each group. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor module in which a plurality of semiconductor integrated circuit chips are mounted, for example, to a technique effective when applied to a multichip module in which a data processor chip and a memory chip are mounted on a multilayer wiring board.

  An electronic circuit that performs image processing and the like is often composed of a data processor called a microprocessor or a microcomputer and a high-speed operation memory represented by a synchronous DRAM (hereinafter referred to as SDRAM) accessed by them. Recent SDRAMs are required to operate at higher speeds such as 100 MHz operation represented by standards such as “PC100” and “PC133” and 133 MHz operation. When an electronic circuit includes such a high-speed operation memory, for example, it becomes necessary to perform high-speed operation, countermeasures for high-frequency noise become important accordingly. A printed circuit board (PCB) on which an SDRAM or a data processor is mounted may be a high-frequency noise source that cannot be ignored. So, for example, to reduce the high-frequency impedance of the power supply line, surround it with a shield frame, increase the equivalent capacitance by devising the power supply line, and adopt a multilayer wiring structure. To be considered.

  However, it is difficult to form a printed circuit board having a desired performance, and if the entire printed circuit board has a multilayer wiring structure, the manufacturing cost of the printed circuit board becomes extremely high.

  In addition, the present inventors have clarified that there is room for further study on high-frequency noise countermeasures for circuit portions that operate at high speed and technology for mounting multiple types of LSIs such as microprocessors on a multilayer wiring board. .

  First, it is possible to sufficiently prevent memory data from being destroyed by high-frequency noise during high-speed operation of the memory. One considered technique is a technique in which a high-speed operation circuit such as a microprocessor, an I / O port, and a random access memory is provided on a multilayer wiring board, and the multilayer wiring board is mounted on a printed board such as a motherboard. With this technique, it is possible to expect a certain level of good operation of the high-speed operation circuit by the multilayer wiring board. However, even with this configuration, when high-frequency noise flows through the bus connected to the memory or the microprocessor, the read data or write data of the memory during the access operation changes undesirably on the bus.

  Secondly, consideration is given to device mounting layout and function assignment of external connection electrodes. That is, it is desirable that the external noise flowing in via the module internal bus connected to the memory or the microprocessor has a small influence on the read data or write data of the memory during the access operation. For this purpose, it is desirable to consider the mounting layout of several types of devices on the module board and to consider the function assignment of the external connection electrodes of the module board.

  Thirdly, when determining the mounting layout on the module substrate for the several types of devices, the number of steps for mounting and assembling the devices on the multilayer wiring board may be reduced so that the yield and reliability of the semiconductor module are not lowered. is necessary.

  After completing the present invention, the present inventors have learned that there are the following known examples.

  One is Japanese Patent Laid-Open No. 1-220498. In this publication, high-frequency noise is easily radiated from a bus line connecting between a microprocessor and an I / O port. An invention is disclosed in which a sufficient noise reduction effect can be obtained while disposing on a multilayer substrate while preventing a significant increase in cost. Then, it is stated that, if both random access memories are mounted on the multilayer substrate, the portion most likely to generate high frequency noise is mounted on the multilayer substrate.

  Another is JP-A-5-335364, which describes an invention relating to a multilayer wiring board in which a region for mounting a memory LSI is provided around a region for bare mounting a microprocessor LSI. Yes.

  However, these known examples do not mention anything as mentioned above that has room for further study.

Japanese Patent Laid-Open No. 1-220498 JP-A-5-335364

  An object of the present invention is to provide a semiconductor module that can prevent memory data from being destroyed by high-frequency noise during a memory access operation, and an electronic circuit in which the semiconductor module is mounted on a motherboard.

  Another object of the present invention is to provide a high-speed operation circuit such as a data processor chip and a memory chip on a multilayer wiring board, and even if the multilayer wiring board is mounted on a printed board such as a motherboard, the data processor chip does not It is an object of the present invention to provide a semiconductor module and an electronic circuit in which external noise hardly flows into a memory via an in-module bus to which they are connected.

  Still another object of the present invention is to provide a semiconductor module in which read data or write data of a memory during an access operation hardly changes undesirably on an in-module bus.

  Another object of the present invention is to provide a semiconductor module that can alleviate the effects of external noise in terms of the mounting layout of several types of semiconductor integrated circuit chips on a module substrate.

  Another object of the present invention is to provide a semiconductor module that can alleviate the influence of external noise in terms of function assignment of external connection electrodes of a module substrate on which several types of semiconductor integrated circuit chips are mounted.

  Another object of the present invention is to provide a semiconductor module that can contribute to an improvement in yield and reliability by reducing the number of processes for assembling several types of semiconductor integrated circuit chips mounted on a module substrate.

  Still another object of the present invention is a multi-chip module that can operate at high speed while suppressing high-frequency noise, has high resistance to external noise, has high reliability, and can realize them at a relatively low cost. Is to provide a semiconductor module such as

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

《Noise resistant performance enhancement buffer》
A semiconductor module according to a first aspect of the present invention includes a data processor chip, a memory chip, a module substrate having a plurality of external connection electrodes and a plurality of wiring layers connectable to the plurality of external connection electrodes. A buffer circuit that can be regarded as a switch circuit is provided. The data processor chip and the memory chip are commonly connected to an intra-module bus formed by the wiring layer. The buffer circuit is inserted into the intra-module bus, and blocks input from an external connection electrode connected to the intra-module bus when the memory chip is accessed by the data processor chip.

  Based on the above, it is possible to prevent memory data from being destroyed due to high frequency noise during the memory access operation.

  The buffer circuit, for example, responds to an operation selection of an address output buffer that outputs an address signal toward the external connection electrode, a control signal output buffer that outputs an access control signal toward the external connection electrode, and the memory chip. Thus, the data input / output buffer is brought into a high impedance state. Since the address output buffer and the control signal output buffer always suppress signal input, there is no noise inflow through the address output buffer and control signal output buffer. Common-sense data direction control in the data input / output buffer is input by the read operation of the data processor and output by the write operation, but in the present invention, it is controlled to a high impedance state in response to the operation selection of the memory chip. When the data processor chip accesses the memory chip, it is difficult for the external noise to flow into the memory via the in-module bus to which the data processor chip is connected, and the memory data can be prevented from being destroyed by the high frequency noise during the memory access operation.

  The buffer circuit may be an address input / output buffer, a control signal input / output buffer, and a data input / output buffer. In this case, these input / output buffers are high in response to the operation selection of the memory chip. The impedance state is set. The memory access operation is controlled in the high impedance state in response to the memory chip operation selection, so that when the data processor chip accesses the memory chip, it is difficult for external noise to flow into the memory via the internal bus connected to the data processor chip. It is possible to suppress the destruction of memory data due to high frequency noise inside.

  From the viewpoint of suppressing high-frequency noise, the module substrate has a solid pattern in which the power supply wiring pattern and the ground wiring pattern are uniformly formed on the entire surface. It is a good idea to have a multilayer wiring structure that has a large equivalent capacitance and that can be taken uniformly over the entire circuit. At this time, if the multilayer wiring structure adopts a structure including a base layer having a plurality of wiring layers and a build-up layer in which the same number of wiring layers are stacked on the front and back of the base layer, the module substrate Warpage can be prevented well.

  Even if the high-frequency noise resistance is enhanced by the multilayer wiring board, when the data processor chip accesses the memory chip, the external noise tends to flow into the memory via the internal module bus to which the data processor chip is connected. Suppresses the inflow of such external noise and prevents memory data destruction due to high frequency noise during memory access operation.

《Noise-proof performance enhanced layout》
In the multichip module according to the second aspect of the present invention, a large number of external connection electrodes connected to the wiring layer are arranged on one surface of the module substrate having a plurality of wiring layers, and the other surface of the module substrate. Mounting pads for mounting a plurality of semiconductor integrated circuit chips connected to the wiring layer are disposed. In the mounting pad, a mounting pad area of a plurality of semiconductor integrated circuit chips capable of relatively high speed operation is separated from a mounting pad area of a plurality of semiconductor integrated circuit chips having a relatively low operating speed. Yes.

  If the high-speed operation area and the low-speed operation area are separated on the module board, the function of the external connection electrode arranged on the back side of the module board is different from the circuit characteristics of the high-speed operation area and the low-speed operation area. It becomes possible to decide accordingly.

  For example, external connection electrodes assigned to addresses and data are arranged on the back surface of a region where a plurality of semiconductor integrated circuit chips having relatively low operation speeds are mounted. The address and data input / output operations are performed at high speed and frequently in the operation of the multichip module, so that the influence of the noise generated in the frequent part of such signal change is mitigated by the circuit in the high speed operation region. be able to.

  Further, a relatively large number of external connection electrodes assigned to supply of the power supply voltage and the ground voltage can be arranged on the back surface of the region where the plurality of semiconductor integrated circuit chips having relatively high operation speeds are mounted. If the number of external connection terminals for power supply is relatively large, the number of external connection electrodes assigned for signal input / output is relatively small, so that the influence of external noise on the circuit in the high-speed operation region can be mitigated. it can.

  In the multichip module according to another aspect of the external noise inflow mitigation layout, a large number of external connection electrodes connected to the wiring layer are arranged on one surface of the module substrate having a plurality of wiring layers, and the other side of the module substrate is arranged. A data processor chip, a memory chip, and a buffer circuit connected to the wiring layer are provided on the surface. A data processor chip is disposed substantially at the center of the module substrate. A plurality of memory chips are arranged on one side and a plurality of buffer circuits are arranged on the other side with the data processor chip interposed therebetween. According to this, the data processor chip and the memory chip are operated at a relatively high speed or frequently, and the buffer circuit is operated at a relatively low speed or the operation frequency is relatively low. According to this layout, as described above, the high-speed operation region and the low-speed operation region are separated.

  In a multichip module according to still another aspect of the external noise inflow mitigation layout, a large number of external connection electrodes connected to the wiring layer are arranged on one surface of the module substrate having a plurality of wiring layers, On the other surface, a data processor chip, a memory chip, and a buffer circuit are provided via a mounting pad connected to the wiring layer. External connection electrodes corresponding to input / output of addresses and data are arranged on the back surface of the area where the buffer circuit is mounted. As a result, the external connection electrode portions where the signal changes frequently such as address and data input / output can be kept away from the high-speed operation portions such as the data processor chip and the memory chip.

  In a multichip module according to still another aspect of the external noise inflow mitigation layout, a large number of external connection electrodes connected to the wiring layer are arranged on one surface of the module substrate having a plurality of wiring layers, On the other surface, a data processor chip, a memory chip, and a buffer circuit are provided via a mounting pad connected to the wiring layer. A relatively large number of external connection electrodes assigned to supply of a power supply voltage and a ground voltage are disposed on the back surface of the area where the memory chip is mounted. As a result, as described above, the external connection electrode portions with frequent signal changes such as address output and data input / output can be kept away from the high-speed operation portions such as the data processor chip and the memory chip.

  In a multichip module according to still another aspect of the external noise inflow mitigation layout, a large number of external connection electrodes connected to the wiring layer are arranged on one surface of the module substrate having a plurality of wiring layers, A plurality of types of semiconductor integrated circuit chips are provided on the other surface via mounting pads connected to the wiring layer. The arrangement of the external connection electrodes for the operation power supply allocated to supply of the power supply voltage and the ground voltage is rough on the module substrate, and the rear surface of the semiconductor integrated circuit chip with higher power consumption is assigned to the external power supply allocated to the operation power supply. The connection electrodes are densely arranged. In general, there is a correlation that the charge / discharge operation of the internal circuit in the semiconductor integrated circuit chip increases in power consumption as it is performed at high speed and frequently. Therefore, if attention is paid to this point of view, signals such as address output and data input / output can be obtained by arranging the external connection electrodes allocated for the operation power source closer to the back surface of the semiconductor integrated circuit chip that consumes more power. The external connection electrode portion that frequently changes is moved away from the high-speed operation portion rather than the low-speed operation portion.

<Reducing the number of assembly steps>
The semiconductor module according to the viewpoint of reducing the assembly man-hour has a mounting pattern formed on the other surface of the module substrate in which a plurality of external connection electrodes are arranged on one surface, and the mounting pattern is a semiconductor integrated having substantially the same height dimension. Each group of circuit chips has a grouped pattern in which the semiconductor integrated circuit chips can be mounted in a line. The mounting pattern and the bump electrode of the semiconductor integrated circuit chip are conductively connected through an anisotropic conductive film attached to each of the grouped patterns. Since a mounting pattern in which an anisotropic conductive film can be attached to each group of semiconductor integrated circuit chips having almost the same height dimension is adopted, one anisotropic conductive film is attached to each group, A plurality of semiconductor integrated circuit chips can be collectively heated to the anisotropic conductive film for each group, and in this respect, the number of processes for mounting several types of semiconductor integrated circuit chips on a module substrate and assembling can be reduced. can do. Thereby, it can contribute to the improvement of the yield and reliability of a semiconductor module. In addition, the cost of the multichip module is reduced.

<Address delay reduction wiring>
A semiconductor module focused on aligning the address input timing to the memory chip has a number of external connection electrodes connected to the wiring layer on one side of the module substrate having the wiring layer, and the other side of the module substrate. A data processor chip and a plurality of memory chips connected to the wiring layer are mounted on the surface. Each of the memory chips has electrode pads arranged in a line, and a plurality of memory chips are arranged in a direction intersecting with the arrangement direction of the electrode pads, and a wiring layer for supplying an address to each memory chip is a memory chip. It extends in the arrangement direction and is sequentially coupled to an electrode pad for address input.

《Motherboard and daughter board》
Focusing on the relationship between the mother board and the daughter board mounted thereon, the electronic circuit of the present invention includes a first semiconductor device and a second semiconductor device capable of operating at a higher speed than the first semiconductor device. It is configured to be mounted on the bus in a common connection state. The relationship of the second semiconductor device to the wiring board corresponds to the relationship of the daughter board to the mother board. The second semiconductor device has a data processor chip and a memory chip that are commonly connected to the bus via an external connection electrode on a multilayer wiring board, and a wiring from the data processor chip and the memory chip to the external connection electrode A buffer circuit is provided in the path. The buffer circuit cuts off the input from the bus when accessing the memory chip by the data processor chip.

  As the buffer circuit, an address output buffer, a control signal output buffer, and a data input / output buffer respectively inserted in the wiring path may be employed. The data input / output buffer may be controlled to a high impedance state in response to a memory chip access instruction from the data processor chip. The buffer circuit may be an address input / output buffer, a control signal input / output buffer, and a data input / output buffer that are respectively brought into a high impedance state in response to an operation selection of the memory chip.

  The external connection electrodes corresponding to address output and data input / output may be arranged on the back surface of the area where the buffer circuit is mounted.

  A relatively large number of external connection electrodes assigned to supply of the power supply voltage and the ground voltage may be arranged on the back surface of the area where the memory chip is mounted.

  According to the above, the second semiconductor device such as a multi-chip module is capable of high-speed operation by reducing high-frequency noise, has high external noise resistance, and has high reliability as an entire electronic circuit, They can be realized at a relatively low cost.

  A representative one of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to provide a semiconductor module that can contribute to an improvement in yield and reliability by reducing the number of steps for assembling several types of semiconductor integrated circuit chips on a module substrate.

《Motherboard and multichip module》
FIG. 1 shows an example of an electronic circuit according to the present invention using a multichip module. The electronic circuit 1 shown in the figure is not particularly limited, but a circuit portion that requires high-speed data processing such as image processing, such as a digital copy device or a car navigation device, and monitoring of communication functions and systems. This is a circuit in which a circuit portion that does not require a high-speed operation so as to realize a function is mixedly mounted.

  An electronic circuit 1 shown in FIG. 1 has a wiring pattern (not shown) of a wiring board 2, a multichip module 3 as a semiconductor module, ASICs (Application Specific ICs) 4 and 5, and a crystal oscillator. (OSC) 6 is mounted. The input / output connector 7 is connected to a predetermined wiring pattern (not shown) of the wiring board 2 so that the electronic circuit 1 can be coupled to other devices. The connector 7 is not limited to the illustrated form, and can be variously changed. The wiring board 2 is a low-cost printed board in which, for example, about two layers of wiring patterns are printed on the front and back of a glass epoxy resin.

  FIG. 22 illustrates a part of the wiring board 2 as a printed board in a longitudinal section. Copper wirings 81A, 81B, and 81C are formed on the front surface of the glass epoxy resin substrate 80, and copper wirings 82A and 82B are formed on the back surface, which are used as connecting portions for mounting the multichip module 3, the ASICs 4, 5, and the like. Except for the portion, the copper wiring is covered and protected by a solder resist layer 84. In the illustrated example, the copper wiring 81A is connected to the copper wiring 82A through the through hole 83A, the copper wiring 81C is connected to the copper wiring 82C through the through hole 83B, and wiring using two wiring layers on the front and back sides. This is merely an example showing the outline of the wiring structure, and various wiring patterns are actually formed according to the desired wiring.

  Although not specifically illustrated, it is needless to say that the electronic circuit 1 may increase the high frequency impedance of the power supply line with a bypass capacitor or be surrounded by a shield frame as a general countermeasure against high frequency noise.

  The multi-chip module 3 includes a data processor chip 11 as a bare chip, memory chips 12a to 12d, buffer chips 13a to 13e, and logic gates on a multilayer wiring board 10 having a large number of external connection electrodes arranged on the bottom surface. This is an example of a second semiconductor device on which the chip 14 is mounted and operated at a relatively high speed. Focusing on the relationship between the mother board as the first mounting board and the daughter board as the second mounting board mounted thereon, the first semiconductor device and the second semiconductor device capable of operating at a higher speed than the first semiconductor device. The semiconductor device is mounted on the bus of the wiring board 2 in a common connection state. The relationship of the multichip module 3 to the wiring board 2 corresponds to the relationship of the daughter board to the mother board.

  As will be described later with reference to FIGS. 13, 20, and 21, the multilayer wiring board 10 has a plurality of wiring patterns. For example, the power wiring pattern and the ground wiring pattern are uniformly formed as a conductor layer. The equivalent capacitance between the signal pattern and the power supply pattern or the ground pattern can be increased and uniform across the entire circuit due to the solid pattern structure or the like. The multilayer wiring structure itself can exhibit a function of suppressing the generation and diffusion of high frequency noise to some extent. The wiring layer of the multilayer wiring board 10 is connected to the external connection electrode on one surface of the substrate 10 and connected to the mounting pad of the bare chip on the other surface. The details of the multilayer wiring board 10 will be described later.

  The ASICs 4 and 5 are positioned as peripheral circuits of the data processor chip 11 and are circuits having peripheral functions such as communication and monitoring. The ASICs 4 and 5 are examples of a first semiconductor device having an operation speed slower than that of the second semiconductor device. The The ASICs 4 and 5 are, for example, semiconductor chips housed in a flat package.

  The crystal oscillator 6 supplies a clock signal as an operation reference to the multichip module 3 and the ASICs 4 and 5. According to FIG. 1, the reference clock output from the oscillator 6 is input to the substrate 10 via the wiring 6 </ b> I of the substrate 2. The reference clock input to the substrate 10 is supplied to the processor chip 11 via the wiring in the substrate 10 and is set to a desired frequency, for example, 200 MHz, by the clock pulse generation circuit in the data processor chip 11. It is a clock. On the other hand, the data processor chip 11 outputs the operation clocks of the memory chips 12a to 12d and the operation clocks of the ASICs 4 and 5. The operation clock for the ASICs 4 and 5 is supplied from the substrate 10 to the ASICs 4 and 5 via the wiring 6O in the substrate 2. The multichip module 3 and the ASICs 4 and 5 start processing upon receiving a command or data input via the input / output connector 7. In the middle of the processing, the multichip module 1 and the ASICs 4 and 5 input / output data via a common bus (not shown). The final processing results by the multichip module 1 and the ASICs 4 and 5 are output from the input / output connector 7 to the outside.

  FIG. 2 shows the appearance of an electronic circuit according to a comparative example that does not employ the multichip module 3. The function of the multichip module 3 is replaced by a plurality of semiconductor integrated circuit chips included in a region 3A surrounded by a broken line in FIG. That is, in the electronic circuit 1A of FIG. 2, instead of the multichip module 3 of FIG. 1, a data processor 11A and memories 12Aa to 12Ad are mounted on the wiring board 2A as individually packaged semiconductor product circuits. The data processor 11A and the memories 12Aa to 12Ad that operate at a relatively high speed and the ASICs 4 and 5 that only need to operate at a relatively low speed are commonly connected to the same bus on the wiring board 2A. Circuits corresponding to the buffer chips 13a to 13e in FIG. 1 are not provided.

  As shown in FIG. 2, when a device that should operate at high speed and a device that can operate at low speed are connected to a common bus, the design of the wiring board 2A having the common bus requires at least the data processor 11A and the memories 12Aa to 12Ad. Since the wiring connecting them requires high-speed operation, it is difficult to satisfy the electrical characteristics and the external noise resistance performance. If all the wiring boards 2A have a multi-layer wiring structure, the cost will increase remarkably even if the requirement can be satisfied. At this time, as shown in FIG. 1, if the circuit portion that requires high-speed operation is configured by the multichip module 3, the remaining circuits such as the ASICs 4 and 5 do not require high-speed operation. The design burden for can be greatly reduced.

  The chip components mounted on the multilayer wiring board 10 in FIG. 1 are bare chips that are not sealed in the IC package as described above. Therefore, compared with the components packaged here, the occupied area is reduced, and accordingly, delay components such as a resistance component and a capacitance component parasitic on the wiring in the circuit are reduced, which is suitable for high-speed operation. Further, since a large amount of wiring is completed in the multichip module 3, the number of wirings remaining on the wiring board 2 is reduced, and as a result, the number of wiring layers of the wiring board 2 can be reduced. This contributes to a reduction in manufacturing cost of the wiring board 2. Furthermore, as described above, by using the multichip module 3 in which a plurality of bare chips are mounted on one multilayer wiring board 10 and sealed, the area of the wiring board 2 itself can be reduced. Since the multichip module 3 has a size approximately equal to the outer shape of the packaged data processor 11A, the wiring board 2 itself can be made small, and is suitable for use in a small device such as a portable terminal. For example, the size of the module 3 can be reduced to 27 mm × 27 mm.

  In addition, changes due to product improvements and product development are planned from the beginning so that only the mounted multi-chip module is modified, so that the common use of the wiring board 2 of the electronic circuit becomes possible. The manufacturing cost is also reduced. That is, if the configuration of the electronic circuit 1 or 1A is changed, the wiring board 2A is completely redesigned in the case of FIG. 2, but in the case of FIG. Therefore, the redesign of the wiring board 2 can be made unnecessary.

《Noise-proof performance enhanced layout》
FIG. 3 shows an example of a chip layout of a multichip module. In FIG. 3, the data processor chip 11 and the memory chips 12a to 12d that are operated at a relatively high speed, and the buffer chips 13a to 13e and the logic gate chip 14 that are operated at a relatively low speed are arranged separately on the multilayer wiring board 10. ing. In particular, a data processor chip 11 is arranged at substantially the center of the multilayer wiring board 10, with a plurality of memory chips 12a to 12d on one side and a plurality of buffer chips 13a to 13e on the other side across the data processor chip 11. And the logic gate chip 14 is arranged in parallel. Although illustration is omitted, it goes without saying that there is no problem even if passive components such as a bypass capacitor and an oscillation prevention resistor are mounted on the module substrate as necessary.

  FIG. 4 shows the bottom surface of the multichip module shown in FIG. A large number of external connection electrodes are arranged on the bottom surface of the multilayer wiring board 10 so as to circulate in four rows. Although not particularly limited, the external connection electrode 15 is composed of a solder ball. Although not particularly limited, the diameter of each external connection electrode 15 is 0.76 millimeters (mm), and the distance between the centers of each external connection electrode 15 is 1.27 millimeters. The multilayer wiring board 10 employed here is not particularly limited, but adopts an external shape similar to an IC package called a ball grid array (hereinafter referred to as BGA). For example, it is suitable for a 256-pin BGA package. Needless to say, the multichip module 3 may use other package formats.

  FIG. 5 illustrates a function assignment state for the external connection electrodes of the multichip module. The orientation of FIG. 5 is consistent with FIG.

  In FIG. 5, memory chips 12a to 12d are generally arranged on the back surface of the region E5. Buffer chips 13a to 13e and a logic gate chip 14 are arranged on the back surface of the regions E1 to E4.

  In FIG. 5, the external connection electrode 15 vs indicated by a black circle is a circuit ground voltage Vss supply terminal (ground terminal). The external connection electrodes 15da and 15db shown by hatched circles and parallel lines are 1.8 V and 3.3 V supply voltage vdd supply terminals, and the white circle external connection electrodes 15 sg are signal terminals. The power supply of 1.8V is used as the operation power supply for the CPU of the data processor chip. In principle, the other circuits use 3.3V as the operating power supply.

  The external connection electrodes 15sg in the areas E1 and E2 are assigned to data input / output and address output, which are signals that change frequently or move frequently. On the other hand, the external connection electrode 15sg in the region E3 is assigned to an input and an output of a handshake signal of a data processor chip such as an interrupt signal or a data transfer request signal which is a signal whose signal change is gentle or has little movement, In this region E3, the electrodes 15da, 15db, and 15vs assigned to supply of the power supply voltage Vdd and the ground voltage Vss are particularly increased. The external connection electrode 15sg in the region E4 is assigned to output such as a chip select signal, and the external connection electrode 15sg in the region E5 is assigned to output such as a write signal and a read signal. Some of the signal external connection electrodes 15sg are roughly surrounded by power supply external connection terminals 15da, 15db, and 15vs. This is also intended to prevent signal noise. Note that CKIO is a clock output terminal to the ASICs 4 and 5, and XTAL and EXTAL are connection terminals to the oscillator 6.

  In FIG. 5, most of the external connection electrodes in one row that circulate in the innermost circumference are assigned to supply of the power supply voltage and the ground voltage, and this is applied to the data processor chip 11 mounted in the central portion of the multilayer wiring board 10. This is to strengthen the power supply.

  The data processor chip 11 and the memory chips 12a to 12d are operated at a relatively high speed or frequently, and the buffer chips 13a to 13e and the logic gate chip 14 are operated at a relatively low speed or the operation frequency is relatively low. Few. If the memory chips 12a to 12d, the buffer chips 13a to 13e, and the logic gate chip 14 are laid out on both sides of the data processor chip 11 as shown in FIG. 3, the high speed operation area and the low speed operation area are separated. . If the high-speed operation area and the low-speed operation area are separated on the module substrate 10, the function of the external connection electrode arranged on the back surface of the multilayer wiring 10 can be changed between the circuit characteristics of the high-speed operation area and the circuit characteristics of the low-speed operation area. It becomes possible to decide according to the difference.

  For example, external connection electrodes corresponding to address output and data input / output are arranged on the rear surfaces E1 and E2 of the region where the buffer chips 13a to 13e and the logic gate chip 14 having relatively low operation speed are mounted. The address output and data input / output operations are performed at high speed and frequently in the operation of the multichip module. Therefore, the data processor chip 11 which is a circuit in the high speed operation region is affected by the noise generated in such a frequent part of signal change. In addition, the memory chips 12a to 12d can be relaxed. This enhances noise resistance.

  Further, external connection electrodes 15da, 15db assigned to supply of the power supply voltage Vdd and the ground voltage Vss are provided on the back surface area E3 of the area where the data processor chip 11 and the memory chips 12a to 12d having relatively high operation speed are mounted. A relatively large amount of 15vs is arranged, and accordingly, the number of external connection electrodes 15sg allocated for signal input / output in the region E3 is relatively small. This means that external connection electrode portions with frequent signal changes such as address output and data input / output are separated from high-speed operation portions such as data processor chips and memory chips. Therefore, it is possible to reduce the influence of external noise on the data processor chip 11 and the memory chips 12a to 12d that operate at high speed. Also in this point, the noise resistance performance is enhanced.

  The viewpoint of enhancing the noise resistance can be grasped as a density with respect to the arrangement of the external connection electrodes for the operation power supply allocated to the supply of the power supply voltage and the ground voltage. The external connection electrodes allocated for the operation power supply are arranged closer to the back surface of the semiconductor integrated circuit chip that consumes more power. The charge / discharge operations of the internal circuits in the semiconductor integrated circuit chips 11, 12 a to 12 d, 13 a to 13 e, 14 generally have a correlation that the power consumption increases as the operation is performed at high speed and frequently. Therefore, if attention is paid to this point of view, signals such as address output and data input / output can be obtained by arranging the external connection electrodes allocated for the operation power source closer to the back surface of the semiconductor integrated circuit chip that consumes more power. The external connection electrode portion that frequently changes is moved away from the high-speed operation portion rather than the low-speed operation portion.

《Noise resistant performance enhancement buffer》
FIG. 6 illustrates a functional block diagram of the multichip module.

  FIG. 7 shows an example of a connection mode between the data processor chip and the memory chip in correspondence with terminals.

  The memory chips 12a to 12d are constituted by SDRAM, for example, and function as a main memory of the data processor chip 11, for example.

  Although not specifically shown, the SDRAM has a matrix of dynamic memory cells in a memory cell array, and performs operations such as row active, column active read, column active write, and refresh by a command signal supplied in synchronization with a clock signal. The address signal supplied with the command or the address signal generated by the internal address counter is used, and the read / write operation is performed in synchronization with the clock. If a burst operation is instructed, a predetermined burst number of data can be continuously read or written. As illustrated in FIG. 7, the SDRAMs 12a to 12d have / CS (chip selection) as an access control signal input terminal in addition to the address input terminals A13 to A0 and the data input / output terminals I / O15 to I / O0. , / RAS (row address strobe), / CAS (column address strobe), / WE (write enable), CLKE (clock enable), CLK (clock), DQML, and DQMH (data mask). DQML and DQMH (data mask) are control terminals for masking input data byte by byte in a burst write operation.

  In FIG. 6, the multi-chip module 3 includes a data bus 28D, an address bus 28A, and control buses 28C1 and 28C2 as an intra-module bus 28.

  A 14-bit address signal line A [16: 3] included in the address bus 28A is commonly connected to the memory chips 12a to 12d. The memory chips 12a to 12d and the signal line of the data bus 28D are individually connected in units of 16 bits. The 16-bit signal line D [15: 0] is connected to the memory chip 12a, the 16-bit signal line D [31:16] is connected to the memory chip 12b, and the 16-bit signal line D [47:32] is connected to the memory chip 12c. , 16-bit signal lines D [63:48] are connected to the memory chip 12d. The control bus 28C1 is a generic term for a group of signal lines connected to the memory chips 12a to 12d. For example, individual signals for each memory chip are supplied to terminals DQML and DQMH (data mask), and other terminals / CS (chip selection), / RAS (row address strobe), / CAS (column address strobe), / WE ( A common signal is supplied to each memory chip. The control bus 28C2 is a control signal not connected to the memory chip, for example, an interrupt signal, a DMA request signal, a DMA acknowledge signal, or the like.

  FIG. 7 shows address output terminals A16 to A3, data input / output terminals I / O63 to I / O0, and access control terminal CKIO as corresponding terminals of the data processor chip 11 connected to the terminals of the memory chips 12a to 12d. , CKE, / CSm, / RASm, / CASm, RD / WR, DQM7 to DQM0 are shown.

  As the data processor chip 11, SH7750 sold by Hitachi, Ltd. can be used. As illustrated in FIG. 8, a central processing unit (CPU) 21 and a floating point arithmetic unit (FPU) 22 are connected to the system bus 20. The system bus 20 can be interfaced to the cache bus 24 via the address translation / cache unit 23. The CPU 21 includes an instruction control unit 21A that decodes the fetched instruction and generates a control signal, and an arithmetic unit 21B that performs integer arithmetic under the control of the instruction control unit 21A. If the fetched instruction is an FPU instruction, the CPU 21 performs necessary bus access control to control the FPU 22 to fetch an operand or store an operation result. The FPU 22 decodes the FPU instruction and performs a floating point operation. The address translation / cache unit 23 has an address translation mechanism that translates a logical address into a physical address, and also has a data cache memory and an instruction cache memory. If the address translation / cache unit 23 is a cache hit, the information related to the hit is output to the system bus 20 and the information of the system bus 20 is written to the cache memory. When a cache miss occurs, the address translation / cache unit 23 instructs the bus state controller 25 to access the external bus, thereby enabling reading or writing of information related to the miss.

  The cache bus 24 is connected to a bus state controller 25. The bus state controller 25 performs external access via the internal bus 26, the external bus interface circuit 27, and the intra-module bus 28 according to an instruction from the cache bus 24, or an SCI (serial communication interface) 30 via the peripheral bus 29. The peripheral circuit such as the timer 31 and the A / D 32 is accessed. An interrupt controller 33, a clock generation circuit 34, and a DMAC (direct memory access controller) 35 are connected to the peripheral bus 29. The DMAC 35 can be accessed externally via the bus state controller 25 according to the initial setting by the CPU 21. The data processor chip 11 uses the clock signal CLK as an operation reference clock signal and operates synchronously with the clock signal.

  In FIG. 6, the data bus 28D, the address bus 28A, and the control bus 28C1 of the intra-module bus 28 include, for example, a data input / output buffer 40, an address output buffer 41, a control signal output buffer 42, and the buffer circuit as buffer circuits. A logic gate chip 14 is inserted. The data input / output buffer 40 is composed of the buffer chips 13a and 13b, the address output buffer 41 is composed of the buffer chips 13c and 13d, and the control signal output buffer 42 is composed of the buffer chip 13e. The data input / output buffer 40 blocks input when the data processor chip 11 accesses the memory chips 12a to 12d.

  FIG. 9 illustrates the configuration of one bit of the address output buffer 41 and the control signal output buffer 42. This is because the tristate buffers TB1 and TB2 are connected in reverse parallel, one tristate buffer TB1 is activated and controlled by the output of the AND gate G1, and the other tristate buffer TB2 is activated and controlled by the output of the AND gate G2. The That is, the buffers 41 and 42 can be regarded as tristate bus switches. The two inputs of the AND gate G1 are fixed at a high level, and the tri-state buffer TB1 can always be output when the operation power is turned on. Since the output of the other AND gate G2 is fixed to the low level, the tristate buffer TB2 is fixed to the high output impedance state. As a result, an output buffer capable of always performing an output operation after the operation power is turned on is realized.

  FIG. 10 illustrates the configuration of one bit of the data input / output buffer 40. This is because the tristate buffers TB1 and TB2 are connected in reverse parallel, one tristate buffer TB1 is activated and controlled by the output of the AND gate G1, and the other tristate buffer TB2 is activated and controlled by the output of the AND gate G2. The That is, the buffer 40 can be regarded as a pair of bus switches whose inputs and outputs are cross-connected. The logic gate chip 14 has a NAND gate G3 having two inputs of a power supply voltage Vdd and a chip selection signal / CS. The inverted output signal of the NAND gate G3 is input to one input of the AND gates G1 and G2. An inverted signal and a non-inverted signal of the read signal / RD are input to the other inputs of the AND gates G1 and G2.

  The chip selection operation of the memory chips 12a to 12d by the data processor chip 11 is instructed by the low level of / CS. In this state, the output of the NAND gate G3 is set to a high level, and in response to this, the outputs of both AND gates G1 and G2 are set to a low level, so that the data input / output buffer 40 is set to a high impedance state. In the chip non-selected state (/ CS = high level) of the memory chips 12a to 12d, the output of the AND gate G1 is set to the high level in response to the read operation instruction by / RD, and the tristate buffer TB1 is externally connected to the data bus. Data can be input to 28D. In the chip non-selected state (/ CS = high level) of the memory chips 12a to 12d, when the read operation by / RD is not instructed, the output of the AND gate G2 is set to the high level, and the tristate buffer TB2 is set to the data bus 28D. Data can be output to the outside. The buffer circuits shown in FIGS. 9 and 10 are configured using the general-purpose buffer circuit HD74LVHC16245, and therefore have almost the same circuit configuration. If a general-purpose buffer circuit is not used, the same circuit configuration may not be used.

  When the data processor chip 11 and the memory chips 12a to 12d are operated at a high speed of, for example, 100 MHz or more, noise tends to enter the intra-module bus 28. Recent semiconductor integrated circuits capable of high-speed operation tend to lower the power supply voltage. This is to reduce power consumption and reduce the signal amplitude, thereby reducing the time required for signal change and enabling high-speed operation. However, there is a problem that when the amplitude of the signal becomes small, it is easily affected by external noise. For such high-frequency noise, as described above, first, high-speed operation devices such as the data processor chip 11 and the memory chips 12a to 12d are selected, and a multi-chip module having a multilayer wiring structure having excellent noise resistance characteristics is obtained. . Second, the layout of the chip and the external connection terminal 15 with enhanced noise resistance performance is adopted for the multichip module. After that, the above-described buffer circuits 40, 41, 42, and 14 were inserted into the intra-module buses 28D, 28A, and 28C1. The buffer circuits 40, 41, 42, and 14 suppress the injection of noise from the wiring board 2 to the intra-module bus, in contrast to the first and second noise resistance enhancement measures for the multichip module 3 itself. Therefore, we are going to take more thorough noise countermeasures.

  The operation of the buffer circuits 40, 41, 42 and 14 from the above viewpoint will be described. As apparent from the above, the address output buffer 41 that outputs an address signal toward the external connection electrode 15 and the control signal output buffer 42 that outputs an access control signal toward the external connection electrode 15 always receive a signal input. Since it is suppressed, there is no inflow of high frequency noise from the external connection electrode 15 through it. Further, the data input / output buffer 40 which is brought into a high impedance state in response to the operation selection of the memory chip also makes it difficult for external noise to flow into the memory chip from the external connection electrode 15 via the intra-module bus. Therefore, it is possible to enhance a function of suppressing memory data destruction due to high frequency noise during memory access operation. Further, since it is sufficient to control the high impedance state in response to the operation selection of the memory chip, simple control is sufficient.

  As described above, it is possible to enhance the prevention of memory data destruction due to high frequency noise during the memory access operation.

  FIG. 17 illustrates another functional block diagram of the multichip module. The multichip module 3ext shown in the figure is different from the multichip module 3 of FIG. 6 in that an external device (for example, a car navigation system or the like is used to store map data on a CD-ROM) arranged outside the multichip module 3ext. (Device for reading from ROM, device for extracting teletext data) 43ext enables the inside of the multichip module 3ext to be accessed. For example, the multichip module 3ext includes a graphic accelerator 11ext. Further, the data bus 28D, the address bus 28A, and the control bus 28C1 of the intra-module bus 28 have a data input / output buffer 40ext and an address input / output as buffer circuits. A buffer 41ext, a control signal input / output buffer 42ext, and the logic gate chip 14ext are inserted. The data processor chip 11 has a bus arbitration circuit, and the external device 43ext supplies the bus request signal BREQ to the data processor chip 11 to request the bus right, and the bus right for the external device 43ext is acknowledged by the bus acknowledge signal BACK. Returned to the external device 43ext. Although the bus request signal BREQ and the bus acknowledge signal BACK are illustrated as being input / output via the control bus 28C1, it should be understood that they are actually input / output via the bus 28C2.

  18 illustrates an input / output buffer 40ext and a part of the logic gate chip 14ext that controls the input / output buffer 40ext, and FIG. 19 illustrates an input / output buffer 41ext, 42ext and a part of the logic gate chip 14ext that controls the input / output buffer 41ext. Yes. Circuit elements having the same functions as those in FIGS. 9 and 10 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The input / output buffers 40ext, 41ext, and 42ext are supplied with the chip selection signal / CS to the NAND gate G3, and the input is blocked when the data processor chip 11 accesses the memory chips 12a to 12d as in FIG.

  As shown in FIG. 19, the input / output buffers 41ext and 42ext function as output buffers by deactivating the tristate buffer TB2 when the data processor chip 11 has acquired the bus right.

  In the data input / output buffer 40ext, the data direction by the read / write is reversed depending on whether the data processor chip 11 acquires the bus right or the external device 43ext acquires the bus right. In order to support this, as illustrated in FIG. 18, when the bus acknowledge signal / BACK is negated (the data processor chip 11 has the bus right), the read signal / RD output by the data processor chip 11 is selected. A multiplexer MPX is provided for selecting a write signal / WR output from the external device 43ext when the bus acknowledge signal / BACK is asserted (the external device 43ext has the bus right).

  In the example of FIGS. 18 and 19, the external device 43ext can access the graphic accelerator 11ext. However, the external device 43ext cannot access the SDRAMs 12a to 12d by asserting the chip selection signal / CS. This is because the input / output buffers 40ext, 41ext, and 42ext are brought into a high impedance state by the assertion of the chip selection signal / CS. Although not shown in particular, in order to allow the external device 43ext having acquired the bus right to access the SDRAMs 12a to 12d by asserting the chip selection signal / CS, the NAND gate G3 in FIGS. 18 and 19 is changed to a two-input NOR gate. Instead, the chip selection signal / CS may be input to one input, and the inverted signal of the bus acknowledge signal / BACK may be input to the other input.

  In the configuration of FIG. 17 as well, similar to FIG. 6, a multi-chip module with a multi-layer wiring structure is adopted for high-frequency noise, and the layout of the external connection terminal 15 that covers the chip with enhanced noise resistance performance is adopted for the multi-chip module. In addition, the above-described buffer circuits 40ext, 41ext, 42ext, and 14ext are inserted into the intra-module buses 28D, 28A, and 28C1. The buffer circuits 40ext, 41ext, 42ext, 14 suppress the injection of noise from the wiring board 2 side to the in-module bus with respect to the first and second noise resistance enhancement measures for the multichip module 3ext itself. In addition, a thorough noise countermeasure is taken. Accordingly, since the buffer circuits 40ext, 41ext, and 42ext are set to a high impedance state in response to the operation selection of the memory chip, it is possible to strengthen a function of suppressing memory data destruction due to high frequency noise during the memory access operation.

<Address delay countermeasures>
As described with reference to FIG. 3, when the device mounting area of the multichip module is divided into the high-speed operation area and the low-speed operation area, it can be considered that the parallel address input timings to the memory chips 12a to 12d are aligned.

  For example, as illustrated in FIG. 11, when the bonding pads 50 of the memory chips 12 a to 12 d are arranged in a line along the longitudinal direction at a substantially central portion of the chip 51, the signal line A [16: 3] are extended in a direction crossing the arrangement direction of the bonding pads 50 and are sequentially coupled to the bonding pads 50 of the address system. 11, 52A to 52D are memory arrays constituting a plurality of memory banks, 53 is a power supply system control circuit, 54 is a data system control circuit, 55 is a command system control circuit, and 56 is an address system control circuit. The signal line A [16: 3] indicates a total of 14 address lines A16 to A3.

  FIG. 12 shows the connection state between the memory chips 12a to 12d and the signal line A [16: 3] of the address bus 28A in the entire multichip module 3. In the figure, the control buses 28C1 and 28C2 are not shown.

  According to the layout configuration of the address signal lines with respect to the address type bonding pads arranged in a line in the center pad format, the address signal propagated in parallel to the address bus 28A is transferred to each memory chip 12a-12d in parallel. The bit reaches the address bonding pad at the same timing. Therefore, it is most suitable for the arrangement of the memory chips 12a to 12d such as SDRAM to be operated at high speed.

  In the configuration shown in FIG. 12, the data processor chip 11 is connected to the memory chip 12a via 16 data lines D [15: 0] and to the memory chip 12b via 16 data lines D [31:16]. Further, it is coupled to the memory chip 12c via 16 data lines D [47:32] and to the memory chip 12d via 16 data lines D [63:48]. Data lines D [31:16] and [15: 0] are coupled to buffer circuits 13a and 13b. On the other hand, 26 address lines A [25: 0] are coupled to buffer circuits 13c and 13d.

<Multilayer wiring structure>
FIG. 13 shows an example of a multilayer wiring structure in the multilayer wiring board.

  The multilayer wiring board 10 has a structure in which build-up layers 61 and 62 in which the same number of wiring layers are stacked on the front and back of a core layer or base layer 60 having a plurality of wiring layers are generated. Due to the symmetry of the front and back by forming the build-up layers 61 and 62 having the same number of layers on the front and back of the core layer 60, it is possible to satisfactorily prevent the module substrate 3 from warping due to heat.

  The core layer 60 is configured by laminating wiring layers 60A to 60D made of, for example, four layers of copper via a glass epoxy resin. One buildup layer 61 is formed by laminating wiring layers 61 </ b> A to 61 </ b> C made of three layers of copper on an upper surface of the core layer 60 via an epoxy resin. Similarly, the other buildup layer 62 is formed by laminating wiring layers 62A to 62C made of three layers of copper on the bottom surface of the core layer 60 via an epoxy resin. The wiring layers are appropriately coupled by through holes or the like in order to obtain necessary connections.

  In particular, the predetermined wiring layers 60A to 60D, except for the selectively provided through-hole portions, are power supply wiring patterns and ground wiring patterns that are uniformly formed as a conductive layer over the entire surface. Consideration is given so that the equivalent capacitance between the pattern and the ground pattern can be made large and uniform over the entire circuit. Details will be described later with reference to FIGS.

  The uppermost layer of the build-up layer 61 is covered with an insulating layer (or protective layer) 63 such as a solder resist layer except for a mounting pad portion used for mounting the semiconductor integrated circuit chip 64 such as the data processor chip 11. ing. The bump electrode 65 made of gold (Au) of the semiconductor integrated circuit chip 64 is conductively connected to the mounting pad via an anisotropic conductive film 66 described later, and the surface of the buildup layer 61 via the anisotropic conductive film 66. It is fixed to.

  The surface of the buildup layer 62 is covered with an insulating layer 67 such as a resist layer except for a portion where the external connection electrode 15 is formed. The external connection electrodes 15 are formed by solder balls on the portion of the wiring layer 62 </ b> C exposed from the resist layer 67.

  The build-up layers 61 and 62 are formed by repeating the process of attaching an epoxy resin to the core layer 60, forming a through hole in a desired portion, and forming a wiring pattern made of copper on the upper surface thereof. More specifically, the buildup layer is formed as follows. First, the core layer 60 is immersed in an epoxy resin solution, and a first epoxy resin layer is formed on the front and back of the core layer 60. Then, in order to form a through hole in a portion of the epoxy resin layer corresponding to the wiring connection portion, etching is performed using an appropriate etching mask. Thereafter, a metal film made of copper constituting the wiring layer 61C or 62C is formed and etched to form the wiring layer 61C or 62C. By sequentially performing the above steps, the wiring layers 61A or 62A are formed. Thereafter, the build-up layers 61 and 62 are formed by selectively forming insulating films 63 and 67 such as solder resist films.

  If a build-up layer is formed on one side of the substrate, the core layer and the build-up layer have different heat characteristics. Therefore, the multi-chip module may be warped by the influence of thermal stress generated when the multi-chip module is mounted. If it does so, peeling with a core layer and a buildup layer may generate | occur | produce in any layer in a board | substrate, and the disconnection of internal wiring may generate | occur | produce. As described with reference to FIG. 13, in the substrate in which the build-up layers 61 and 62 are generated on both surfaces of the core layer 60, the heat resistance characteristics on both the front and back surfaces are equal, so that the influence of thermal stress can be suppressed low. Therefore, it is possible to reduce the possibility of delamination and wiring destruction, and it is possible to realize a highly reliable multichip module.

  The thickness of the multilayer wiring board 10 that is the sum of the thickness of the core layer 60 and the thicknesses of the build-up layers 61 and 62 is not particularly limited, but is 1.22 millimeters. Further, among the data processor chip 11, the memory chips 12a to 12d, the buffer chips 13a to 13d or the logic gate chip 14 arranged on one surface of the multilayer wiring board 10, the back surface of the thickest chip and the multilayer wiring board The distance between each of the external connection electrodes 15 formed on the other surface of 10, that is, the height of the multichip module 3 is 2.3 millimeters. As a result, the mounting height of the multichip module 3 is set to 2.7 millimeters or less.

  As a result, the multi-chip module 3 can be easily mounted on a mounting substrate provided in an electronic device that requires various elements such as a small-sized, thin, and light weight, such as a mobile phone or a handheld computer. it can.

  Although not shown in FIG. 13, there are the following power supply connection modes. For example, when the power supply terminal or the ground terminal provided on the semiconductor chip 11 cannot be connected to the connection terminal 15 (ground terminal) to the connection terminal 15 (power supply 1 terminal) linearly through a through hole as shown in FIG. There is also. In this case, the wiring layer 60A (ground layer) or 60D (ground layer) or the wiring layer 60B (power one layer layer) once formed in the core layer 60 from the power supply terminal or ground terminal provided in the semiconductor chip 11 is used. ) Or the wiring layer 60C (power supply layer 2). Thereafter, a wiring layer 60A (ground layer) corresponding to a connectable portion of the connection terminal 15 (ground terminal), connection terminal 15 (power supply 1 terminal) to connection terminal 15 (power supply 2 terminal) corresponding to the multichip module substrate 10. , 60D (ground layer), wiring layer 60B (power supply 1 layer) and wiring layer 60C (power supply 2 layer) linearly from the connection terminal 15 (ground terminal), connection terminal 15 (power supply 1 terminal) to connection terminal 15 ( Power supply 2 terminal).

  FIG. 20 is a diagram for explaining FIG. 13 in more detail, and gold bumps such as a ground terminal (GND) to a power supply terminal (VDD, 3.3 V, 1.8 V) provided on the semiconductor integrated circuit chip 64. The connection relationship between the electrode 65 and each external connection electrode 15 formed on the multilayer wiring board 10 is shown.

  As shown in the figure, the terminal 65 to be supplied with the ground potential provided in the semiconductor integrated circuit chip 64 is provided in the wiring 61A, 61B, 61C and the buildup layer 62 provided in the buildup layer 61. The wirings 62A, 62B and 62C are connected to a solder bump electrode 15 as a ground terminal to which a ground potential (ground potential: 0V) is to be supplied. The wiring layer 61C is electrically coupled to the wiring layers 60A and 60C in the portion of the through hole TH formed in the core layer 60. As a result, the wiring layers 60A and 60C are ground layers to which a ground potential is supplied. .

  On the other hand, the terminal 65 provided with the power supply potential (1.8 V) provided in the semiconductor integrated circuit chip 64 is provided in the wirings 61A, 61B, 61C and the buildup layer 62 provided in the buildup layer 61. The wiring 62A, 62B, 62C is connected to a solder bump electrode 15 as a power source 2 terminal to which a power source potential (1.8V) is to be supplied. The wiring layer 61C is electrically coupled to the wiring layer 60D in the portion of the through hole TH formed in the core layer 60. As a result, the wiring layer 60D includes a power supply layer to which a power supply potential (1.8V) is supplied. Is done.

  Although not shown in the drawing, a terminal 65 to which a power supply potential (3.3 V) provided in the semiconductor integrated circuit chip 64 is supplied is provided with wirings 61A, 61B, 61C provided in the buildup layer 61 and The wirings 62A, 62B, and 62C provided in the buildup layer 62 are connected to the solder bump electrode 15 as a power supply 1 terminal to which a power supply potential (3.3V) is to be supplied. The wiring layer 61C is electrically coupled to the wiring layer 60B at the portion of the through hole TH formed in the core layer 60. As a result, the wiring layer 60B is connected to the power supply 1 layer to which the power supply potential (1.8V) is supplied. Is done.

  As described above, the wiring layers 60A to 60D formed in the core layer 60A are coupled to the power supply potential (3.3V, 1.8V) or the ground potential, and as described above, an effect of reducing noise occurs. .

  FIG. 21 is a view for explaining FIG. 13 in more detail. The gold bump electrode 65 as a signal terminal provided on the semiconductor integrated circuit chip 64 and each external connection electrode 15 formed on the multilayer wiring board 10 are shown. The connection relationship is shown.

  As shown in the figure, the terminal 65 (signal 2) or 65 (signal 5) to be supplied with the signal 2 provided in the semiconductor integrated circuit chip 64 is connected to wirings 61A and 61B provided in the buildup layer 61. 61C and wirings 62A, 62B, 62C provided in the build-up layer 62, are connected to the solder bump electrode 15 (signal 2) as a signal terminal to which the signal 2 is to be supplied. The wiring layers 61C to 62A are not electrically coupled to the wiring layers 60A to 60D in the portion of the through hole TH formed in the core layer 60, and the wiring layers 61C to 62A are electrically connected to the portion of the through hole TH. Are connected. Note that the bumps 65 to which the signals 1, 3, 4 and 6 are supplied are also electrically coupled to the desired bump electrodes 15 in a portion not shown.

<Assembly of multichip module>
A method of assembling the multichip module 3 by the flip chip method will be described.

  FIG. 14 shows some important points in the process of mounting the bare chip on the module substrate by the flip chip method. FIG. 15 illustrates a cross-sectional structure of the bump electrode 65, the mounting pad 71, and the joint.

  FIG. 14A typically illustrates a semiconductor integrated circuit chip 64 as one bare chip. What is indicated by 65 is a bump electrode. The bump electrode 65 is formed on the bonding pad 73 (see FIG. 15) of the semiconductor integrated circuit chip 64, and the surface of the bump electrode 65 is plated with gold, for example.

  As shown in FIG. 14B, the mounting pads 71 are exposed on the surface of the module substrate 10, where the bump electrodes 65 are placed and conductively connected. The surface of the mounting pad is, for example, gold-plated.

  An anisotropic conductive film 66 is attached to the surface of the mounting pad 71 as shown in FIG. The anisotropic conductive film 66 is a thermosetting resin film in which conductive fine particles such as nickel particles are dispersed and mixed in a thermosetting resin. When a force is applied to the anisotropic conductive film 66 in the thickness direction, it is elastically deformed as illustrated in FIG. 15, and the conductive fine particles contained in the portion are chained and contacted, Conductivity can be obtained only in the portion. This state is maintained by being cured by heat, and the adhesive action is exhibited by the thermosetting property. What is necessary is just to determine the magnitude | size of the anisotropic conductive film 43 affixed on a board | substrate according to the magnitude | size of the IC chip connected.

  Finally, as shown in FIG. 14D, the anisotropic conductive film 66 is formed such that the bump electrodes 65 of the semiconductor integrated circuit chip 64 as a bare chip are bonded to predetermined mounting pads 71 on the module substrate 10. Crimp on top. Thereafter, heat is applied to cure the anisotropic conductive film 66, whereby the semiconductor integrated circuit chip 64 is attached as shown in the cross-sectional structure of FIG. 15, and the conductive connection between the bump electrode 65 and the mounting pad 71 is achieved. Is completed.

  When the multi-chip module 3 illustrated in FIG. 3 is assembled, a total of 11 bare chips of the data processor chip 11, the memory chips 12a to 12d, the buffer chips 13a to 13e, and the logic gate chip 14 have been described with reference to FIG. Thus, when mounting on the module substrate 10 one by one, a process of sticking a separate anisotropic conductive film 66 for each bare chip, pressing a bare chip on it, or thermosetting it Must be repeated 11 times each, and the working efficiency becomes extremely low.

  Therefore, from the viewpoint of reducing the number of assembly steps, it is possible to mount the semiconductor integrated circuit chips on the module substrate 10 in a line for each group of semiconductor integrated circuit chips having substantially the same height, for example, the same type of semiconductor integrated circuit chips. The mounting pads are grouped and arranged. Then, an anisotropic conductive film is attached to each of the grouped mounting pads, and the mounting pattern and the bump electrodes of the semiconductor integrated circuit chip are conductively connected through the attached anisotropic conductive film. For example, in the case of the multi-chip module 3 in which the bare chips are arranged as shown in FIG. 3, as shown in FIG. 16, an anisotropic conductive film 66A is pasted with the array of memory chips 12a to 12d as one group. Then, one anisotropic conductive film 66B is pasted as a group of the array of the buffer chips 13a to 13e and the logic gate chip 14, and one anisotropic conductive film 66C is pasted for the data processor 11 alone. wear. Then, for each group, the bare chip is pressure-bonded on the anisotropic conductive film so that the corresponding bump electrode 65 of the bare chip is bonded to the corresponding mounting pad 71, and heat is collectively applied to cure the anisotropic conductive film. Let Accordingly, it is possible to reduce the number of times the anisotropic conductive films 66A, 66B, and 66C are attached and the number of times the bare chip is bonded to the anisotropic conductive films 66A, 66B, and 66C or the number of times of pressure heating to about three. Therefore, the number of steps for assembling the multichip module 3 can be reduced. The simplification of the assembly process contributes to the improvement of the yield and reliability of the multichip module. Furthermore, the manufacturing cost of the multichip module can be reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention.

  For example, a semiconductor integrated circuit chip mounted on a multi-chip module is not limited to a bare chip, and may be sealed with a small or thin package such as a CSP (chip size package). Further, the use of the memory chip is not limited to the main memory and the cache memory, and may be any use that is accessed by the data processor. In addition, the multi-chip module also includes an accelerator, which is an arithmetic processing unit for reducing the processing load on the data processor, such as a circuit chip for graphics processing, error correction processing, compression processing, etc. Also good. Further, the number of memory chips mounted on the module substrate, the number of buffer chips, the number of data processors, and the like are not limited to the above description.

  The present invention is widely applied to an image processing device, a sound processing device, a multimedia device that performs high-speed data processing such as image processing, and a form information terminal or a portable communication terminal that performs communication, image display, and the like. be able to.

FIG. 1 is an external view showing an example of an electronic circuit according to the present invention using a multichip module. FIG. 2 is an external view of an electronic circuit according to a comparative example that does not employ a multichip module. FIG. 3 is a plan view showing an example of a chip layout of the multichip module. 4 is a bottom view of the multichip module shown in FIG. FIG. 5 is an explanatory view illustrating the state of function assignment to the external connection electrodes of the multichip module. FIG. 6 is a block diagram of the multichip module. FIG. 7 is an explanatory diagram showing an example of a connection mode between the data processor chip and the memory chip in correspondence with terminals. FIG. 8 is a block diagram showing an example of a data processor chip. FIG. 9 is a logic circuit diagram of the output buffer. FIG. 10 is a block diagram of an input / output buffer and a logic gate chip. FIG. 11 is a plan view illustrating the arrangement of address signal lines with respect to the bonding pads of the center chip memory chip. FIG. 12 is an explanatory diagram showing the connection state between the memory chip and the signal line of the address bus for the entire multi-chip module 3. FIG. 13 is a cross-sectional view showing an example of a multilayer wiring structure in a multilayer wiring board. FIG. 14 is an explanatory view showing some important points in the process of mounting the bare chip on the module substrate by the flip chip method. FIG. 15 is a cross-sectional view illustrating a cross-sectional structure of a bump electrode, a mounting pad, and a joint. FIG. 16 is an explanatory diagram of a multi-chip module showing a state in which a plurality of bare chips are mounted by attaching an anisotropic conductive film to each bare chip group. FIG. 17 is another functional block diagram of the multichip module. FIG. 18 is a logic circuit diagram illustrating a part of the data input / output buffer and the logic gate chip that controls the data input / output buffer of FIG. FIG. 19 is a logic circuit diagram illustrating a part of the address input / output buffer and the control signal input / output buffer of FIG. FIG. 20 is a detailed explanatory view of FIG. 13 showing a connection relationship between gold bump electrodes such as ground terminals or power supply terminals provided on the semiconductor integrated circuit chip and each external connection electrode formed on the multilayer wiring board. FIG. 21 is a detailed explanatory view of FIG. 13 showing a connection relationship between a gold bump electrode as a signal terminal provided on the semiconductor integrated circuit chip and each external connection electrode formed on the multilayer wiring board. FIG. 22 is a cross-sectional view showing an example of a wiring board as a printed board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Module substrate 11 Data processor chip 12a-12d Memory chip 13a-13e Buffer chip 14 Logic gate chip 66A, 66B, 66C Anisotropic conductive film

Claims (1)

A mounting pattern is formed on the other surface of the module substrate in which a plurality of external connection electrodes are arranged on one surface,
The mounting pattern has a grouped pattern that can be mounted by arranging the semiconductor integrated circuit chips in a line for each group of semiconductor integrated circuit chips having substantially the same height.
A semiconductor module, wherein a mounting pattern and a bump electrode of a semiconductor integrated circuit chip are conductively connected through an anisotropic conductive film attached to each of the grouped patterns.

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