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JP2007158419A - Crystal oscillator for surface mount - Google Patents

Crystal oscillator for surface mount Download PDF

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Publication number
JP2007158419A
JP2007158419A JP2005346617A JP2005346617A JP2007158419A JP 2007158419 A JP2007158419 A JP 2007158419A JP 2005346617 A JP2005346617 A JP 2005346617A JP 2005346617 A JP2005346617 A JP 2005346617A JP 2007158419 A JP2007158419 A JP 2007158419A
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ceramic substrate
chip
crystal
crystal piece
crystal oscillator
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Japanese (ja)
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Shusuke Harima
秀典 播磨
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Nihon Dempa Kogyo Co Ltd
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Nihon Dempa Kogyo Co Ltd
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Priority to JP2005346617A priority Critical patent/JP2007158419A/en
Priority to US11/606,511 priority patent/US7602107B2/en
Publication of JP2007158419A publication Critical patent/JP2007158419A/en
Priority to US12/584,155 priority patent/US7932786B2/en
Priority to US12/584,168 priority patent/US8008980B2/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive surface mount crystal oscillator for expediting miniaturization. <P>SOLUTION: The crystal oscillator for surface mount has a closed container 1 comprising a rectangular ceramic substrate 4 that has a metal film 9 on the outer periphery circulating around one main surface, and a packaged electrode 7 on the other surface; and a recessed metal cover 5, where an opening end face is brazed to the metal film 9. The closed container 1 stores an IC chip 2 and a crystal piece 3 in the closed container 1. The ceramic substrate 4 is formed in a plate shape where both the main surfaces are horizontal. In the IC chip 2, a circuit functional surface is fixed onto one main surface of the ceramic substrate 4 by using a bump 12. One extended longitudinal edge of an extraction electrode 14 in the crystal piece 3 is stuck onto one edge of a surface opposite to the circuit functional surface of the IC chip 2 directly, or by interposing an auxiliary substrate 21. The extraction electrode 14 extended to both the sides of one edge in the crystal piece 3 is electrically connected to a relay terminal 16 provided on the ceramic substrate 4 via a conductor 20 at least by wire bonding. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は表面実装用水晶発振器(以下、表面実装発振器とする)を技術分野とし、特に小型で安価な表面実装発振器に関する。   The present invention relates to a surface mount crystal oscillator (hereinafter referred to as a surface mount oscillator), and more particularly to a small and inexpensive surface mount oscillator.

(発明の背景)
表面実装発振器は小型・軽量であることから、特に携帯電話を代表としてコンパクトな移動型の電子機器に、周波数や時間の基準源として内蔵される。このようなものの一つに、本出願人による表面実装発振器がある(特許文献1参照)。
(Background of the Invention)
Since surface-mounted oscillators are small and lightweight, they are built in as a reference source for frequency and time in compact mobile electronic devices such as mobile phones. One of such devices is a surface mount oscillator by the present applicant (see Patent Document 1).

(従来技術の一例)
第3図は一従来例を説明する表面実装発振器の図で、同図(a)は断面図、同図(b)はICチップの回路機能面(一主面)の図、同図(c)は水晶片の平面図である。
(Example of conventional technology)
FIG. 3 is a diagram of a surface-mount oscillator for explaining a conventional example. FIG. 3 (a) is a sectional view, FIG. 3 (b) is a diagram of a circuit function surface (one main surface) of the IC chip, and FIG. ) Is a plan view of the crystal piece.

表面実装発振器は密閉容器1内にICチップ2と水晶片3とを収容してなる。密閉容器1はセラミック基板(実装基板)4と金属カバー5とからなる。セラミック基板4は矩形状とした平板状の第1セラミック4aと開口部を有して凹部を形成する第2セラミック4bとを積層してなる。第1セラミック4aは積層面側の表面(凹部底面)にICチップ2と電気的に接続する回路端子6を有し、裏面の4角部に実装電極7を有する。   The surface mount oscillator includes an IC chip 2 and a crystal piece 3 housed in a sealed container 1. The sealed container 1 includes a ceramic substrate (mounting substrate) 4 and a metal cover 5. The ceramic substrate 4 is formed by laminating a flat plate-like first ceramic 4a having a rectangular shape and a second ceramic 4b having an opening and forming a recess. The first ceramic 4a has circuit terminals 6 that are electrically connected to the IC chip 2 on the surface on the laminated surface side (the bottom surface of the recess), and has mounting electrodes 7 on the four corners of the back surface.

実装電極7はスルーホールによる側面電極及び第1と第2セラミック4(ab)との積層面を経て、ICチップ2のIC端子8が固着される回路端子6に電気的に接続する。側面電極は図示しないセット基板への実装時に半田フィレットを形成する。第2セラミック4bは外周に封止用の金属膜9を有し、一端部両側に水晶保持端子10を有する。金属カバー5は凹状とし、開口端面が第2セラミック4bの金属膜9上に接合される。例えば共晶合金AuSn等の金属ロウ11を用いた熱圧着によって接合される。   The mounting electrode 7 is electrically connected to the circuit terminal 6 to which the IC terminal 8 of the IC chip 2 is fixed via the side surface electrode by the through hole and the laminated surface of the first and second ceramics 4 (ab). The side electrodes form solder fillets when mounted on a set substrate (not shown). The second ceramic 4b has a metal film 9 for sealing on the outer periphery, and has crystal holding terminals 10 on both sides of one end. The metal cover 5 has a concave shape, and the opening end face is bonded onto the metal film 9 of the second ceramic 4b. For example, bonding is performed by thermocompression bonding using a metal braze 11 such as a eutectic alloy AuSn.

ICチップ2は少なくとも発振回路を有し、回路機能面である一主面にIC端子8を有する。そして、第1セラミック4a上の回路端子6にバンプ12を用いた超音波熱圧着によって固着される。これにより、ICチップ2の各IC端子8と実装電極7及び水晶保持端子10とが電気的に接続する。   The IC chip 2 has at least an oscillation circuit, and has an IC terminal 8 on one main surface which is a circuit function surface. And it adheres to the circuit terminal 6 on the 1st ceramic 4a by ultrasonic thermocompression using the bump 12. FIG. Thereby, each IC terminal 8 of the IC chip 2 is electrically connected to the mounting electrode 7 and the crystal holding terminal 10.

IC端子8は少なくとも一対の水晶端子、及び実装電極7と電気的に接続する電源、出力、アース、自動制御(AFC)端子を有する。水晶片3は両主面に励振電極13を有し、長さ方向の一端部両側に引出電極14を延出する。そして、引出電極14の延出した一端部両側が水晶保持端子10に導電性接着剤15等によって固着される。水晶保持端子10はICチップ2の水晶端子と電気的に接続する。   The IC terminal 8 has at least a pair of crystal terminals and a power source, an output, a ground, and an automatic control (AFC) terminal that are electrically connected to the mounting electrode 7. The crystal piece 3 has excitation electrodes 13 on both main surfaces, and extends extraction electrodes 14 on both sides of one end in the length direction. Then, both ends of the extended end portion of the extraction electrode 14 are fixed to the crystal holding terminal 10 by the conductive adhesive 15 or the like. The crystal holding terminal 10 is electrically connected to the crystal terminal of the IC chip 2.

このようなものでは、図示しない凹状とした積層セラミックからなる容器本体に平板状の金属カバー5を接合したものに比較し、特に金属カバー5を凹状としてセラミック基板4の外周に接合する。したがって、容器本体の枠幅例えば0.35mmに比較して、金属カバー5の厚み例えば0.08mmとして段に小さいので、内積を大きくできる。逆に言えば、小型化を促進できる。
特開2003−318690号公報 実開平6−48215号公報
In such a case, compared to a case where a flat metal cover 5 is joined to a container body made of a laminated ceramic (not shown), the metal cover 5 is particularly concave and joined to the outer periphery of the ceramic substrate 4. Therefore, the inner product can be increased because the thickness of the metal cover 5 is, for example, 0.08 mm, which is smaller than the frame width of the container body, for example, 0.35 mm. In other words, downsizing can be promoted.
JP 2003-318690 A Japanese Utility Model Publication No. 6-48215

(従来技術の問題点)
しかしながら、上記構成の表面実装発振器では、セラミック基板4は第1と第2セラミック4(ab)とを積層するので、単価が下がらない問題があった。特に、第2セラミック4bは開口部を有して打ち抜き加工を有するので、割り高になる問題があった。
(Problems of conventional technology)
However, in the surface mount oscillator having the above-described configuration, the ceramic substrate 4 has the first and second ceramics 4 (ab) laminated, so that there is a problem that the unit price does not decrease. In particular, since the second ceramic 4b has an opening and has a punching process, there is a problem that it is expensive.

また、セラミック基板4は水晶片3の一端部両側を保持する段部を要するので、ICチップ2を収容する面積は制限される。特に、付加価値を高める温度補償機構等を集積化した場合は、ICチップ2は大型化するので、段部はセラミック基板4の小型化(小面積化)を阻む問題もあった。   Further, since the ceramic substrate 4 requires stepped portions that hold both sides of one end of the crystal piece 3, the area for accommodating the IC chip 2 is limited. In particular, when a temperature compensation mechanism or the like that increases the added value is integrated, the IC chip 2 is increased in size, so that there is a problem that the step portion prevents the ceramic substrate 4 from being reduced in size (smaller in area).

(発明の目的)
本発明は安価で小型化を促進する表面実装発振器を提供することを目的とする。
(Object of invention)
It is an object of the present invention to provide a surface mount oscillator that is inexpensive and promotes miniaturization.

本発明は、特許請求の範囲(請求項1)に示したように、一主面の周回する外周に金属膜を有して他主面に実装電極を有する矩形状のセラミック基板と、前記金属膜に開口端面がロウ付けされた凹状の金属カバーとからなる密閉容器とを備え、前記密閉容器内にICチップと水晶片とを収容してなる表面実装用の水晶発振器であって、前記セラミック基板は両主面ともに水平面とした平板状とし、前記ICチップは前記セラミック基板の一主面に回路機能面がバンプを用いて固着され、前記水晶片の引出電極の延出した長さ方向の一端部は前記ICチップの回路機能面とは反対面の一端部上に直接又は補助基板を介在させて固着され、前記水晶片の一端部両側に延出した引出電極は前記セラミック基板上に設けられた中継端子と少なくともワイヤーボンディングによる導線を経て電気的に接続した構成とする。   According to the present invention, as shown in the claims (Claim 1), a rectangular ceramic substrate having a metal film on the outer periphery of one main surface and mounting electrodes on the other main surface, and the metal A crystal oscillator for surface mounting, comprising: a sealed container comprising a concave metal cover whose opening end face is brazed to a film, wherein an IC chip and a crystal piece are housed in the sealed container; The substrate is a flat plate with both main surfaces being horizontal surfaces, and the IC chip is fixed to one main surface of the ceramic substrate with a circuit function surface using bumps, and the length direction in which the lead electrode of the crystal piece extends is extended. One end is fixed directly on one end opposite to the circuit function surface of the IC chip or via an auxiliary substrate, and lead electrodes extending on both sides of the one end of the crystal piece are provided on the ceramic substrate. Relay terminal and at least A structure that is electrically connected through a conductive wire by Ya bonding.

このような構成であれば、セラミック基板は両主面ともに水平面として開口部を有する枠部は設けないので、セラミック基板の単価を低減できる。また、水晶片はICチップ上に設けられるので、セラミック基板には水晶片の一端部両側を固着する段部を要しない。そして、水晶片の一端部両側の引出電極はワイヤーボンディングによって中継端子に接続するので、水晶片の一端部と中継端子との間の距離を短くできる。したがって、セラミック基板の内積を大きくして小型化できる。   With such a configuration, since the ceramic substrate is not provided with a frame portion having an opening as both horizontal surfaces, the unit price of the ceramic substrate can be reduced. Further, since the crystal piece is provided on the IC chip, the ceramic substrate does not require a step portion for fixing both ends of the crystal piece. Since the lead electrodes on both sides of one end of the crystal piece are connected to the relay terminal by wire bonding, the distance between the one end of the crystal piece and the relay terminal can be shortened. Therefore, the inner product of the ceramic substrate can be increased to reduce the size.

(実施態様項)
本発明の請求項2では、前記セラミック基板と前記水晶片とは長さ方向が一致し、前記中継端子は前記セラミック基板の長さ方向の一端部両側とする。これにより、セラミック基板の長さを短縮して小型化できる。
(Embodiment section)
According to a second aspect of the present invention, the ceramic substrate and the crystal piece have the same length direction, and the relay terminal is on both sides of one end portion of the ceramic substrate in the length direction. Thereby, the length of the ceramic substrate can be shortened and miniaturized.

同請求項3では、請求項1の前記水晶片は前記ICチップの回路機能面とは反対面に一端部が絶縁性接着剤によって固着され、前記引出電極と前記中継端子とはワイヤーボンディングによって直接に接続する。これによれば、ICチップに水晶片の対向面が直接に固着されるので、部品点数を少なくできる。   In the third aspect, one end of the crystal piece of the first aspect is fixed to the surface opposite to the circuit function surface of the IC chip by an insulating adhesive, and the lead electrode and the relay terminal are directly connected by wire bonding. Connect to. According to this, since the opposing surface of the crystal piece is directly fixed to the IC chip, the number of parts can be reduced.

同請求項4では、請求項1の前記水晶片は引出電極の延出した一端部両側が補助基板の水晶保持端子に導電性接着剤によって固着され、前記補助基板は前記ICチップの回路機能面とは反対面に絶縁性接着剤によって固着され、前記水晶保持端子は前記中継端子とワイヤーボンディングによって電気的に接続する。これによれば、補助基板を用いるので、作業性を容易にする。   According to the fourth aspect of the present invention, the crystal piece of the first aspect is fixed to the crystal holding terminal of the auxiliary substrate by a conductive adhesive on both sides of the extended end portion of the extraction electrode, and the auxiliary substrate is a circuit functional surface of the IC chip. The crystal holding terminal is electrically connected to the relay terminal by wire bonding. According to this, since the auxiliary substrate is used, workability is facilitated.

同請求項5では、請求項1の前記セラミック基板は単層であって、前記実装電極は前記セラミック基板に設けたビアホールによって前記ICチップと電気的に接続する。これによれば、セラミック基板を単層とするので、単価をさらに安価にする。   In claim 5, the ceramic substrate according to claim 1 is a single layer, and the mounting electrode is electrically connected to the IC chip through a via hole provided in the ceramic substrate. According to this, since the ceramic substrate is a single layer, the unit price is further reduced.

同請求項6では、請求項1の前記セラミック基板は積層であって、前記実装電極は前記セラミック基板の積層面を経て前記ICチップと電気的に接続する。これによれば、ICチップは積層面を経て実装電極に電気的に接続するので、気密を確実にする。   According to the sixth aspect of the present invention, the ceramic substrate according to the first aspect is a multilayer, and the mounting electrode is electrically connected to the IC chip through a multilayer surface of the ceramic substrate. According to this, since the IC chip is electrically connected to the mounting electrode through the laminated surface, airtightness is ensured.

同請求項7では、請求項1の前記セラミック基板は積層であって、前記セラミック基板の側面には温度補償データの書込端子が設けられる。これにより、安価で小型な温度補償発振器を構成できる。   In claim 7, the ceramic substrate of claim 1 is a laminate, and a temperature compensation data write terminal is provided on a side surface of the ceramic substrate. Thereby, an inexpensive and small temperature compensated oscillator can be configured.

(第1実施形態)
第1図は本発明の第1実施形態を説明する図で、同図(a)は表面実装発振器の断面図、同図(b)はセラミック基板の平面図である。なお、前従来例と同一部分には同番号を付与してその説明は簡略又は省略する。
(First embodiment)
FIG. 1 is a diagram for explaining a first embodiment of the present invention. FIG. 1 (a) is a cross-sectional view of a surface mount oscillator, and FIG. 1 (b) is a plan view of a ceramic substrate. In addition, the same number is attached | subjected to the same part as a prior art example, and the description is simplified or abbreviate | omitted.

表面実装発振器は、前述したように、一主面の周回する外周に金属膜9を有する矩形状のセラミック基板4に、凹状の金属カバー5の開口端面を金属ロウ11で接合した密閉容器1を備える。そして、密閉容器1内にICチップ2と水晶片3とを収容してなる。   As described above, the surface-mount oscillator includes the sealed container 1 in which the opening end surface of the concave metal cover 5 is bonded to the rectangular ceramic substrate 4 having the metal film 9 on the outer periphery of one main surface by the metal brazing 11. Prepare. The IC chip 2 and the crystal piece 3 are accommodated in the sealed container 1.

第1実施形態では、セラミック基板4は最小限の一層とし、両主面ともに水平面とした平板状とする。周回する金属膜9は例えば4角部の外周端から離間し、4角部の端面(側面)にはスルーホールによる側面電極7bが形成される。そして、セラミック基板4の一主面には回路端子6及び中継端子16が形成される。また、水晶片3はICチップ2の長さよりも短くする。   In the first embodiment, the ceramic substrate 4 is a minimum of one layer, and has a flat plate shape in which both main surfaces are horizontal surfaces. The circulating metal film 9 is separated from, for example, the outer peripheral ends of the four corners, and side electrodes 7b are formed by through holes on the end surfaces (side surfaces) of the four corners. Circuit terminals 6 and relay terminals 16 are formed on one main surface of the ceramic substrate 4. Further, the crystal piece 3 is made shorter than the length of the IC chip 2.

回路端子6はICチップ2のIC端子8に対応して長さ方向の両側に4個ずつの計8個が形成される。そして、前述のように、少なくとも一対の水晶端子6(X1、X2)、及び電源6(Vcc)、出力6(Vout)、アース6(E)、自動周波数制御6(AFC)端子を有する。ここでのICチップ2は、発振回路とともに温度補償機構を内臓し、温度補償データを書き込む2個の書込端子を有する。これに対応して、回路端子6は2個の書込端子6(W1、W2)を有する。   A total of eight circuit terminals 6 corresponding to the IC terminals 8 of the IC chip 2 are formed, four on each side in the length direction. As described above, at least a pair of crystal terminals 6 (X1, X2), a power source 6 (Vcc), an output 6 (Vout), a ground 6 (E), and an automatic frequency control 6 (AFC) terminal are provided. The IC chip 2 here includes a temperature compensation mechanism together with an oscillation circuit, and has two write terminals for writing temperature compensation data. Correspondingly, the circuit terminal 6 has two write terminals 6 (W1, W2).

中継端子16はセラミック基板4の長さ方向の一端部両側に設けられ、回路端子6中の水晶端子6(X1、X2)に導電路17によって電気的に接続する。セラミック基板4の他主面(外表面、底面)には、側面電極7bと接続した実装電極7を有する。そして、IC端子8(回路端子6)中の電源6(Vcc)、出力6(Vout)、アース6(E)、自動周波数制御端子6(AFC)と電気的に接続する。   The relay terminals 16 are provided on both sides of one end of the ceramic substrate 4 in the length direction, and are electrically connected to the crystal terminals 6 (X1, X2) in the circuit terminals 6 by conductive paths 17. The other main surface (outer surface, bottom surface) of the ceramic substrate 4 has mounting electrodes 7 connected to the side electrodes 7b. The power supply 6 (Vcc), output 6 (Vout), ground 6 (E), and automatic frequency control terminal 6 (AFC) in the IC terminal 8 (circuit terminal 6) are electrically connected.

また、他主面には書込端子6(W1、W2)に接続して温度補償データ書込み用のプローブが当接する書込表面端子7(W1、W2)が設けられる。書込表面端子7(W1、W2)は、両長辺の実装電極間6間の中央に設けられる。そして、実装電極7及び書込表面端子7(ab)とこれに対応する各回路端子6とは、ビアホール18及び一主面の導電路17によって接続する。金属膜9は実装電極7中のアース端子7(E)にビアホール18によって電気的に接続し、ケースアースとする。   The other main surface is provided with writing surface terminals 7 (W1, W2) which are connected to the writing terminals 6 (W1, W2) and contact the temperature compensation data writing probe. The writing surface terminal 7 (W1, W2) is provided at the center between the mounting electrodes 6 on both long sides. The mounting electrode 7 and the writing surface terminal 7 (ab) are connected to the corresponding circuit terminals 6 by via holes 18 and conductive paths 17 on one main surface. The metal film 9 is electrically connected to the ground terminal 7 (E) in the mounting electrode 7 through a via hole 18 to form a case ground.

ビアホール18は、回路下地パターン(回路端子6、中継端子16、導電路17及び実装電極7)を印刷によって形成時する際、印刷材を貫通孔に充填する。印刷材は例えばモリブテン(Mo)やタングステン(W)からなる。そして、セラミック生地とともに一体的に焼成した後、例えば回路パターン上にメッキによるニッケル(Ni)及び金(Au)を積層して形成される。これにより、貫通孔は閉塞されて密閉を維持する。   The via hole 18 fills the through hole with a printing material when the circuit base pattern (the circuit terminal 6, the relay terminal 16, the conductive path 17, and the mounting electrode 7) is formed by printing. The printing material is made of molybdenum (Mo) or tungsten (W), for example. Then, after integrally firing together with the ceramic fabric, for example, nickel (Ni) and gold (Au) by plating are laminated on the circuit pattern. Thereby, a through-hole is obstruct | occluded and a sealing is maintained.

ICチップ2は従来同様にバンプ12を用いた超音波熱圧着によって、各IC端子8が回路端子6に接続する。水晶片3はセラミック基板1と長さ方向が一致し、引出電極14の延出した一端部の対向面が絶縁性接着剤19によって、ICチップ2の回路機能面とは反対面の一端部に固着される。この場合、水晶片の一端部はICチップ2の面内として外周から突出しない。そして、セラミック基板4の中継端子16と導線としての金線20によるワイヤーボンディングによって接続する。   In the IC chip 2, each IC terminal 8 is connected to the circuit terminal 6 by ultrasonic thermocompression using the bumps 12 as in the prior art. The crystal piece 3 is aligned with the ceramic substrate 1 in the length direction, and the opposing surface of one end portion of the lead electrode 14 is extended to one end portion of the surface opposite to the circuit function surface of the IC chip 2 by the insulating adhesive 19. It is fixed. In this case, one end portion of the crystal piece does not protrude from the outer periphery within the surface of the IC chip 2. And it connects with the relay terminal 16 of the ceramic substrate 4 by the wire bonding by the gold wire 20 as a conducting wire.

このような構成であれば、セラミック基板4を平板状の単層とする。したがって、セラミック基板4を最小数として平板なので、安価にできる。そして、水晶片3はICチップ2上に直接に固着するので、一端部両側を保持する段部を要しない。したがって、水晶片3の長さを同一とすると、セラミック基板4の長さを短縮できる。逆に、セラミック基板4の長さを同一とすると、内積を大きくできる。   With such a configuration, the ceramic substrate 4 is a flat single layer. Therefore, since the ceramic substrate 4 is a flat plate with the minimum number, the cost can be reduced. Since the crystal piece 3 is directly fixed on the IC chip 2, no stepped portion for holding both ends of the one end portion is required. Therefore, if the length of the crystal piece 3 is the same, the length of the ceramic substrate 4 can be shortened. Conversely, if the length of the ceramic substrate 4 is the same, the inner product can be increased.

ちなみに、ICチップ2の一端部から金属カバー5の内周面までを約0.3mmにできる。これに対して、従来例での段部は接着剤の塗布面積も必要なので約0.4mmを要し、さらにICチップ2を凹部内に搭載するため約0.15mmの間隙を要する。したがって、従来例では概ね0.55mmを必要とすることから、0.25mm短縮できる。これにより、金属カバー5としたことによる縮小に加えてさらなる小型化もしくは内積を大きくできる。   Incidentally, the distance from one end of the IC chip 2 to the inner peripheral surface of the metal cover 5 can be about 0.3 mm. On the other hand, the step portion in the conventional example requires about 0.4 mm because it requires a coating area of the adhesive, and further requires a gap of about 0.15 mm for mounting the IC chip 2 in the recess. Therefore, the conventional example requires approximately 0.55 mm, and can be shortened by 0.25 mm. Thereby, in addition to the reduction | decrease by having set it as the metal cover 5, further size reduction or an inner product can be enlarged.

また、水晶片3は一端部が絶縁性接着剤19によってICチップ2上に直接に固着される。したがって、ICチップ2を水晶片3の保持台として兼用するので、部品点数を少なくできる。また、水晶片3はICチップ2の長さよりも短くするので、セラミック基板4の大きさはICチップ3の大きさに依存して小さくできる。   Further, one end of the crystal piece 3 is directly fixed on the IC chip 2 by an insulating adhesive 19. Therefore, since the IC chip 2 is also used as a holding base for the crystal piece 3, the number of parts can be reduced. Further, since the crystal piece 3 is made shorter than the length of the IC chip 2, the size of the ceramic substrate 4 can be reduced depending on the size of the IC chip 3.

なお、水晶片3は水平に配置したが、他端側を上向きとして傾斜させ、ICチップ2との接触を防止するようにしてもよい。この場合、ワイヤーボンディング(金線20)のループ高さ程度とすれば、低背化を維持できる。また、底面に設けた書込表面端子6(W1、W2)は、セット基板に対する接続強度を高めるため、必要に応じて実装電極として適用できる。   Although the crystal piece 3 is arranged horizontally, it may be inclined with the other end side facing upward to prevent contact with the IC chip 2. In this case, if the wire bonding (gold wire 20) has a loop height, the height can be kept low. Further, the writing surface terminals 6 (W1, W2) provided on the bottom surface can be applied as mounting electrodes as necessary in order to increase the connection strength to the set substrate.

(第2実施形態)
第2図は本発明の第2実施形態を説明する図で、同図(a)は表面実装発振器の断面図、同図(b)は補助基板21の平面図である。なお、第1実施形態と同一部分の説明は省略又は簡略する。
(Second Embodiment)
2A and 2B are views for explaining a second embodiment of the present invention. FIG. 2A is a cross-sectional view of a surface mount oscillator, and FIG. 2B is a plan view of an auxiliary substrate 21. FIG. In addition, description of the same part as 1st Embodiment is abbreviate | omitted or simplified.

第2実施形態ではICチップ2に水晶片3を直接に固着するのではなく、補助基板21を介在させて水晶片3をICチップ2上に搭載するもので、その他の構成は第1実施形態と同一とする。ここでの補助基板21は例えば水晶片3と同一切断角度(ATカット)とした水晶板からなり、一対の水晶保持端子10を有する。   In the second embodiment, the crystal piece 3 is not directly fixed to the IC chip 2, but the crystal piece 3 is mounted on the IC chip 2 with the auxiliary substrate 21 interposed, and other configurations are the first embodiment. Same as The auxiliary substrate 21 here is made of, for example, a crystal plate having the same cutting angle (AT cut) as the crystal piece 3 and has a pair of crystal holding terminals 10.

ここでは、先ず、前述同様の超音波熱圧着によってICチップ2をセラミック基板4上に固着する。次に、絶縁性接着剤19によって補助基板21をICチップ2上に固着する。次に、引出電極14の延出した水晶片3の一端部両側を導電性接着剤15によって、補助基板21の水晶保持端子10に固着する。最後に、ワイヤーボンディングの金線20によって、水晶保持端子10とセラミック基板4上の中継端子16とを接続する。そして、金属ロウ11を用いた熱圧着によって、金属カバー5の開口端面をセラミック基板4の外周に設けた金属膜9に接合して封止する。   Here, first, the IC chip 2 is fixed onto the ceramic substrate 4 by ultrasonic thermocompression bonding similar to the above. Next, the auxiliary substrate 21 is fixed on the IC chip 2 by the insulating adhesive 19. Next, both ends of one end of the crystal piece 3 from which the extraction electrode 14 extends are fixed to the crystal holding terminal 10 of the auxiliary substrate 21 by the conductive adhesive 15. Finally, the crystal holding terminal 10 and the relay terminal 16 on the ceramic substrate 4 are connected by a gold wire 20 for wire bonding. Then, the opening end face of the metal cover 5 is bonded and sealed to the metal film 9 provided on the outer periphery of the ceramic substrate 4 by thermocompression using the metal solder 11.

このような構成であれば、補助基板21を介在させて水晶片3をICチップ2上に搭載する。したがって、補助基板21はICチップ2上に全面的に固着されるので機械的に安定になる。これにより、水晶保持端子10と中継端子16とを接続するワイヤーボンディングの作業を容易にする。また、水晶片3は補助基板21の厚みによってICチップ2とは間隙を有するので、固着作業等を容易にする。そして、ICチップ2との接触を防止して振動特性を良好に維持する。   With such a configuration, the crystal piece 3 is mounted on the IC chip 2 with the auxiliary substrate 21 interposed. Therefore, since the auxiliary substrate 21 is fixed on the entire surface of the IC chip 2, it is mechanically stable. This facilitates the wire bonding operation for connecting the crystal holding terminal 10 and the relay terminal 16. Further, since the crystal piece 3 has a gap from the IC chip 2 depending on the thickness of the auxiliary substrate 21, the fixing work or the like is facilitated. Then, the contact with the IC chip 2 is prevented and the vibration characteristics are kept good.

また、ここでは補助基板21を水晶片3と同一切断角度(ATカット)とするので、例えば膨張係数を同じにする。したがって、膨張係数差による歪みの発生を抑制して水晶振動子(水晶片3)の耐熱衝撃特性を良好にする。そして、第2実施形態においても第1実施形態と同様に、セラミック基板4は最小数の単層として平板なので、安価にできる。そして、一端部両側を保持する段部を要しないので、セラミック基板4の長さを短縮できて内積を大きくできる。   Here, since the auxiliary substrate 21 has the same cutting angle (AT cut) as that of the crystal piece 3, for example, the expansion coefficient is made the same. Therefore, the occurrence of distortion due to the difference in expansion coefficient is suppressed, and the thermal shock characteristics of the crystal resonator (crystal piece 3) are improved. In the second embodiment, as in the first embodiment, since the ceramic substrate 4 is a flat plate as the minimum number of single layers, the cost can be reduced. And since the step part holding one end part both sides is not required, the length of the ceramic substrate 4 can be shortened and an inner product can be enlarged.

(他の事項)
上記第1及び第2実施形態では水晶片3の他端側は自由端なので衝撃があった場合、ICチップ2と衝突して振動特性に悪影響を及ぼす。したがって、水晶片3の他端部の対応する例えばICチップ2及び又は金属カバー5の他端部に柔軟性の接着剤を塗布して、衝撃時の揺れ幅を小さくするようにしてもよい。
(Other matters)
In the first and second embodiments, since the other end side of the crystal piece 3 is a free end, when there is an impact, it collides with the IC chip 2 and adversely affects the vibration characteristics. Therefore, a flexible adhesive may be applied to, for example, the other end of the crystal chip 3 and / or the other end of the metal cover 5 corresponding to the other end of the crystal piece 3 to reduce the swing width at the time of impact.

また、セラミック基板4はいずれも単層としたが、各層ともに平板状であれば積層であってもよい。この場合でも、枠状のセラミックを使用しないので、打ち抜き加工を要することなく従来に比較して安価にできる。そして、第1実施形態で述べたと同様の効果を奏する。   Moreover, although all the ceramic substrates 4 were made into the single layer, if each layer is flat form, a lamination | stacking may be sufficient. Even in this case, since a frame-shaped ceramic is not used, it can be made cheaper than the prior art without requiring punching. The same effects as described in the first embodiment are obtained.

例えば積層とした場合には、ICチップ2と実装電極7とを積層面を経て電気的に接続して機密を確実にする。また、温度補償型とした場合は、セラミック基板4の側面に、温度補償データの書込端子や水晶振動子の特性検査端子等を形成できる。この場合、積層セラミックの最上位層及び最下位層を無電極極層として電気的短絡を防止できる。   For example, in the case of lamination, the IC chip 2 and the mounting electrode 7 are electrically connected through the lamination surface to ensure confidentiality. In the case of the temperature compensation type, a temperature compensation data writing terminal, a crystal resonator characteristic inspection terminal, and the like can be formed on the side surface of the ceramic substrate 4. In this case, an electrical short circuit can be prevented by using the uppermost layer and the lowermost layer of the multilayer ceramic as electrodeless electrode layers.

また、実装電極7は4角部に側面電極を設けたが、内積を稼ぐため、側面電極を除去して4角部の底面のみであったとしてもよい。さらに、金属膜9は外周の辺縁にまで設けたが、セラミックシートの分割を容易にするため、辺縁から離間してもよい。そして、温度補償データの書込端子を有する温度補償発振器として説明したが、温度補償機構がなかったとしも適用できることは勿論である。   Further, the mounting electrodes 7 are provided with side electrodes at the four corners. However, in order to increase the inner product, the side electrodes may be removed and only the bottom surfaces of the four corners may be provided. Furthermore, although the metal film 9 is provided up to the peripheral edge, it may be separated from the peripheral edge in order to facilitate the division of the ceramic sheet. The temperature compensation oscillator having the temperature compensation data writing terminal has been described, but it is needless to say that the present invention can be applied even if there is no temperature compensation mechanism.

本発明の第1実施形態を説明する図で、同図(a)は表面実装発振器の断面図、同図(b)はセラミック基板4の平面図である。1A and 1B are views for explaining a first embodiment of the present invention, in which FIG. 1A is a cross-sectional view of a surface mount oscillator, and FIG. 1B is a plan view of a ceramic substrate 4. 本発明の第2実施形態を説明する図で、同図(a)は表面実装発振器の断面図、同図(b)は補助基板21の平面図である。4A and 4B are diagrams illustrating a second embodiment of the present invention, in which FIG. 1A is a cross-sectional view of a surface mount oscillator, and FIG. 2B is a plan view of an auxiliary substrate 21. 従来例を説明する表面実装発振器の図で、同図(a)は断面図、同図(b)は水晶片3の平面図、同図(c)はICチップ2の回路機能面(一主面)の図である。FIG. 2A is a cross-sectional view of a surface-mount oscillator for explaining a conventional example, FIG. 2B is a plan view of a crystal piece 3, and FIG. 1C is a circuit function surface (mainly) of an IC chip 2. FIG.

符号の説明Explanation of symbols

1 密閉容器、2 ICチップ、3 水晶片、4 実装基板、5 金属カバー、6 回路端子、7 実装電極、8 IC端子、9 金属膜、10 水晶保持端子、11 金属ロウ、12 バンプ、13 励振電極、14 引出電極、15 導電性接着剤、16 中継端子、17 導電路、18 ビアホール、19 絶縁性接着剤、20 金線、21 補助基板。   DESCRIPTION OF SYMBOLS 1 Airtight container, 2 IC chip, 3 Crystal piece, 4 Mounting board, 5 Metal cover, 6 Circuit terminal, 7 Mounting electrode, 8 IC terminal, 9 Metal film, 10 Crystal holding terminal, 11 Metal solder, 12 Bump, 13 Excitation Electrode, 14 Lead electrode, 15 Conductive adhesive, 16 Relay terminal, 17 Conductive path, 18 Via hole, 19 Insulating adhesive, 20 Gold wire, 21 Auxiliary substrate.

Claims (7)

一主面の周回する外周に金属膜を有して他主面に実装電極を有する矩形状のセラミック基板と、前記金属膜に開口端面がロウ付けされた凹状の金属カバーとからなる密閉容器とを備え、前記密閉容器内にICチップと水晶片とを収容してなる表面実装用の水晶発振器であって、前記セラミック基板は両主面ともに水平面とした平板状とし、前記ICチップは前記セラミック基板の一主面に回路機能面がバンプを用いて固着され、前記水晶片の引出電極の延出した長さ方向の一端部は前記ICチップの回路機能面とは反対面の一端部上に直接又は補助基板を介在させて固着され、前記水晶片の一端部両側に延出した引出電極は前記セラミック基板上に設けられた中継端子と少なくともワイヤーボンディングによる導線を経て電気的に接続したことを特徴とする表面実装用の水晶発振器。   A sealed container comprising a rectangular ceramic substrate having a metal film on an outer periphery of one main surface and a mounting electrode on the other main surface; and a concave metal cover having an open end surface brazed to the metal film; A crystal oscillator for surface mounting in which an IC chip and a crystal piece are accommodated in the hermetically sealed container, wherein the ceramic substrate is a flat plate whose both main surfaces are horizontal surfaces, and the IC chip is the ceramic chip A circuit function surface is fixed to one main surface of the substrate using a bump, and one end portion in the length direction in which the lead electrode of the crystal piece extends is on one end portion of the surface opposite to the circuit function surface of the IC chip. The extraction electrode fixed directly or through an auxiliary substrate and extending on both sides of one end of the crystal piece is electrically connected to a relay terminal provided on the ceramic substrate through at least a wire by wire bonding. A surface-mount crystal oscillator according to claim. 前記セラミック基板と前記水晶片とは長さ方向が一致し、前記中継端子は前記セラミック基板の長さ方向の一端部両側である請求項1の表面実装用の水晶発振器。   2. The surface-mount crystal oscillator according to claim 1, wherein the ceramic substrate and the crystal piece have the same length direction, and the relay terminal is on both sides of one end portion of the ceramic substrate in the length direction. 前記水晶片は前記ICチップの回路機能面とは反対面に一端部が絶縁性接着剤によって固着され、前記引出電極と前記中継端子とはワイヤーボンディングによって直接に接続した請求項1の表面実装用の水晶発振器。   2. The surface mounting device according to claim 1, wherein one end of the crystal piece is fixed to an opposite surface of the IC chip to the circuit function surface by an insulating adhesive, and the extraction electrode and the relay terminal are directly connected by wire bonding. Crystal oscillator. 前記水晶片は引出電極の延出した一端部両側が前記補助基板の水晶保持端子に導電性接着剤によって固着され、前記補助基板は前記ICチップの回路機能面とは反対面に絶縁性接着剤によって固着され、前記水晶保持端子は前記中継端子とワイヤーボンディングによって電気的に接続したことを特徴とする表面実装用の水晶発振器。   The crystal piece is fixed to the crystal holding terminal of the auxiliary substrate by a conductive adhesive on both sides of the extended end portion of the extraction electrode, and the auxiliary substrate is an insulating adhesive on the surface opposite to the circuit function surface of the IC chip. A crystal oscillator for surface mounting, wherein the crystal holding terminal is electrically connected to the relay terminal by wire bonding. 前記セラミック基板は単層であって、前記実装電極は前記セラミック基板に設けたビアホールによって前記ICチップと電気的に接続した請求項1の表面実装用の水晶発振器。   2. The surface-mount crystal oscillator according to claim 1, wherein the ceramic substrate is a single layer, and the mounting electrode is electrically connected to the IC chip through a via hole provided in the ceramic substrate. 前記セラミック基板は積層であって、前記実装電極は前記セラミック基板の積層面を経て前記ICチップと電気的に接続した請求項1の表面実装用の水晶発振器。   2. The surface-mount crystal oscillator according to claim 1, wherein the ceramic substrate is a laminate, and the mounting electrode is electrically connected to the IC chip through a laminate surface of the ceramic substrate. 前記セラミック基板は積層であって、前記セラミック基板の側面には温度補償データの書込端子が設けられた請求項1の表面実装用の水晶発振器。   2. The surface-mount crystal oscillator according to claim 1, wherein the ceramic substrate is laminated, and a temperature compensation data writing terminal is provided on a side surface of the ceramic substrate.
JP2005346617A 2005-11-30 2005-11-30 Crystal oscillator for surface mount Pending JP2007158419A (en)

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US12/584,155 US7932786B2 (en) 2005-11-30 2009-09-01 Surface mount type crystal oscillator
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US8729967B2 (en) 2011-09-08 2014-05-20 Nihon Dempa Kogyo Co., Ltd. Surface-mounted crystal oscillator and manufacturing method thereof
TWI501547B (en) * 2011-09-08 2015-09-21 Nihon Dempa Kogyo Co Surface-mounted crystal oscillator and manufacturing method thereof
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US9939412B2 (en) 2013-02-06 2018-04-10 Empire Technology Development Llc Devices, systems, and methods for detecting odorants

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