JP2007157255A - Ferroelectric memory device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory device having small circuit scale and capable of reading data at high speed. <P>SOLUTION: This memory device includes a first charge transfer section and a second charge transfer section 162 for transferring charges discharged to first and second bit lines to first and second data lines, when charges stored in first and second memory cells are discharged to the first and second bit lines, and a transfer control section 270 for controlling the first and second charge transfer sections on the basis of the voltage of the first bit line, the transfer control section 270 having an operation amplifier 276 for comparing the first bit line with a reference voltage, and amplifying its voltage difference to output it. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a ferroelectric memory device and an electronic apparatus.

A conventional data storage device (ferroelectric memory device) is disclosed in Japanese Patent Laid-Open No. 2002-133857 (Patent Document 1). The conventional data storage device includes a charge transfer means for transferring the charge accumulated in the memory cell to the charge accumulation means in accordance with data, and a voltage generated by the charge accumulated in the charge accumulation means to amplify the voltage in the memory cell. The stored data is being read out.
JP 2002-133857 A

  However, the conventional data storage device has a problem that it is extremely difficult to arrange a large number of memory cells in the data storage device because of the large circuit scale of charge transfer means and the like.

  The present inventor has been engaged in research and development of semiconductor memory devices, in particular, ferroelectric memory devices, and has been diligently studied to achieve high integration (downsizing) and high speed of the devices. An invention relating to a ferroelectric memory device having a small scale and capable of reading data at high speed has been filed as Japanese Patent Application No. 2004-325245.

  However, there is a great demand for speeding up the apparatus, and as will be described in detail later, for example, in order to increase the reading speed, the capability of elements (for example, transistors and capacitors) that constitute a circuit related to reading is improved. There is a need to increase it. As a result, these elements have to be formed large, and it is difficult to achieve high integration (downsizing) of the device, so further improvement is necessary.

  An object of the present invention is to provide a ferroelectric memory device capable of increasing the speed of the device. It is another object of the present invention to provide a ferroelectric memory device that can achieve high integration (downsizing) of the device. Another object of the present invention is to improve read characteristics of a ferroelectric memory device.

  Thus, an object of the present invention is to provide a ferroelectric memory device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  (1) In order to solve the above problems, a ferroelectric memory device of the present invention includes (a) a first memory cell and a second memory cell for storing predetermined data, and (b) a first memory cell. A first bit line connected to the second bit line, a second bit line connected to the second memory cell, (c) a first data line and a second data line having a predetermined capacity, and (d ) When the charges accumulated in the first memory cell and the second memory cell are discharged to the first bit line and the second bit line, respectively, they are discharged to the first bit line and the second bit line. A first charge transfer unit and a second charge transfer unit for transferring the generated charges to the first data line and the second data line, respectively, and (e) comparing the first bit line with a reference voltage. , Having an operational amplifier for amplifying the voltage difference and outputting it, and corresponding to the output, the first charge A transfer control unit that controls the transmission unit and the second charge transfer unit; and (f) a voltage stored in the second memory cell based on the voltage of the second data line to which the charge is transferred from the second bit line. And a determination unit for determining the data.

  In the above configuration, since the transfer control unit controls the second charge transfer unit based on the voltage of the first bit line, the charge released to the second bit line is the voltage of the first bit line. Is transferred to the second data line. That is, the transfer control unit controls the transfer of charges on a plurality of bit lines including the predetermined bit line based on the voltage of the predetermined bit line. Therefore, according to the above configuration, since it is not necessary to provide a transfer control unit for each bit line, even if a large number of memory cells are arranged in the ferroelectric memory device, the circuit scale of the ferroelectric memory device is suppressed. be able to.

  In the above configuration, since the operational amplifier is used for the transfer control unit, for example, when the charge transfer unit is configured by a MOS transistor, the MOS transistor has a sufficiently higher threshold voltage [Vth] (n-channel MISFET). Or a sufficiently low (p-channel MISFET) voltage can be applied at high speed. Therefore, the drive capability of these elements can be suppressed, and these elements can be reduced in size. Moreover, even if the driving capability of the MOS transistor is lowered and the element is reduced, high speed operation is possible.

  In the ferroelectric memory device, the first charge transfer unit and the second charge transfer unit are composed of, for example, MOS transistors.

  In the ferroelectric memory device, the first charge transfer unit and the second charge transfer unit are configured by, for example, p-type MOS transistors, and the operational amplifier compares, for example, the first bit line and the ground voltage, The voltage difference is amplified, and the transfer control unit outputs a voltage lower than the threshold value of the p-type MOS transistor.

  In the ferroelectric memory device, the determination unit preferably compares the voltage of the first data line with the voltage of the second data line to determine data stored in the second memory cell.

  In the above configuration, data can be determined using the voltage of the first data line as a reference voltage. Therefore, according to the above configuration, since it is not necessary to have a circuit for generating a reference voltage, the circuit scale of the ferroelectric memory device can be further suppressed.

  In the ferroelectric memory device, the capacity of the first memory cell is preferably different from the capacity of the second memory cell.

  According to the above configuration, since the voltage of the first data line can be adjusted by adjusting the capacity of the first memory cell, the reference voltage can be generated very easily.

  (2) In order to solve the above problems, a ferroelectric memory device of the present invention includes (a) a memory cell for storing predetermined data, (b) a bit line connected to the memory cell, and (c) a predetermined (D) a charge transfer unit that transfers the charge released to the bit line to the data line when the charge accumulated in the memory cell is released to the bit line; and (e) It has an operational amplifier that compares the bit line with a reference voltage, amplifies the voltage difference and outputs the amplified voltage difference, and has a transfer control unit that controls the charge transfer unit in response to the output.

  In the above configuration, since the operational amplifier is used for the transfer control unit, for example, when the charge transfer unit is configured by a MOS transistor, the MOS transistor is sufficiently higher than the threshold value [Vth] of the MOS transistor (in the case of an n-channel type MISFET). ) Or a sufficiently low (p-channel MISFET) voltage can be applied at high speed. Therefore, the drive capability of these elements can be suppressed, and these elements can be reduced in size. Moreover, even if the driving capability of the MOS transistor is lowered and the element is reduced, high speed operation is possible.

  Hereinafter, the present invention will be described through embodiments of the invention with reference to the drawings. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features that are present are essential to the solution of the invention.

 FIG. 1 is a circuit diagram showing a ferroelectric memory device of the present embodiment. The ferroelectric memory device 100 includes a memory cell array 110, a word line control circuit 120, a plate line control circuit 130, a precharge circuit 150, a charge transfer circuit 160, a transfer control circuit 270, and a precharge circuit 180. The negative voltage generation circuit 190, the voltage control circuit 200, the sense amplifier 230, and the control signal generation circuit 300 are configured.

  Further, the ferroelectric memory device 100 includes m (m is a positive integer) word lines WL1 to m and plate lines PL1 to m, n (n is a positive integer) bit lines BL1 to n and data. Lines DL1 to DLn, a dummy bit line DBL, and a dummy data line DDL are provided.

  Memory cell array 110 has m × (n + 1) memory cells MC (including memory cells MC connected to dummy bit line DBL) arranged in an array. The memory cell MC includes an n-type MOS transistor TR and a ferroelectric capacitor C.

  The n-type MOS transistor TR has a gate connected to one of the word lines WL1 to WLm, a source connected to one of the dummy bit line DBL and the bit lines BL1 to n, and a drain connected to one end of the ferroelectric capacitor C. It is connected to the. That is, the n-type MOS transistor TR switches whether to connect one end of the ferroelectric capacitor C to the dummy bit line DBL and the bit lines BL1 to n based on the voltages of the word lines WL1 to WLm. In this specification, the source and drain refer to one end and the other end of a MOS transistor, and these may be collectively referred to as “source / drain electrodes”.

  The other end of the ferroelectric capacitor C is connected to one of the plate lines PL1 to PLm. Based on the voltage difference between the one end and the other end, predetermined data is stored and stored. A predetermined amount of charge is discharged to the dummy bit line DBL and the bit lines BL1 to n based on the data. In this embodiment, the ferroelectric capacitor C stores data “0” when the voltage at the other end is higher than the coercive voltage with respect to the voltage at one end, and the voltage at the other end is stored. When the voltage at one end becomes higher than the coercive voltage, data “1” is stored.

  The word line control circuit 120 is connected to the word lines WL1 to WLm and controls the voltages of the word lines WL1 to WLm. Specifically, the word line control circuit 120 converts the voltage of a predetermined word line WL among the word lines WL1 to m to another word based on an address signal supplied from the outside of the ferroelectric memory device 100. The n memory cells MC connected to the predetermined word line WL are selected higher than the voltage of the line WL.

  Plate line control circuit 130 is connected to plate lines PL1-m and controls the voltages of plate lines PL1-m. Specifically, the plate line control circuit 130 makes the voltage of a predetermined plate line PL among the plate lines PL1 to PLm higher than the voltages of the other plate lines PL based on the address signal, Select the plate line PL.

  The precharge circuit 150 includes n-type MOS transistors 152 respectively connected to the dummy bit line DBL and the bit lines BL1 to BLn. The n-type MOS transistor 152 has a source grounded and a drain connected to the dummy bit line DBL and the bit lines BL1 to BLn. The n-type MOS transistor 152 has a gate connected to the control signal generation circuit 300, and determines whether the dummy bit line DBL and the bit lines BL1 to n are grounded based on the voltage of the signal PR supplied to the gate. Switch between.

  The charge transfer circuit 160 includes n + 1 p-type MOS transistors 162, which are examples of a first charge transfer unit and a second charge transfer unit. The p-type MOS transistor 162 has a source connected to the dummy bit line DBL and the bit lines BL1 to n, and a drain connected to the dummy data line DDL and the data lines DL1 to n. The p-type MOS transistor 162 switches whether to connect the dummy bit line DBL and the bit lines BL1 to n to the dummy data line DDL and the data lines DL1 to n based on the gate voltage.

  The transfer control circuit 270 is an example of a transfer control unit, and generates a voltage to be supplied to the charge transfer circuit 160. The transfer control circuit 270 includes a ferroelectric capacitor 276 and an operational amplifier (OP amplifier, operational amplifier) 274.

  The negative input of the operational amplifier 274 (reverse phase input terminal, inverting input terminal, input unit) is connected to the dummy bit line DBL, and the positive input (in-phase input terminal, input unit) is grounded. The output of the operational amplifier 274 is connected to one end of the ferroelectric capacitor 276, and the other end of the ferroelectric capacitor 276 is connected to the charge transfer circuit 160 (connected to the node VT). That is, the transfer control circuit 270 is configured by connecting an operational amplifier 274 and a ferroelectric capacitor 276 in series, its input (−input) is connected to the dummy bit line DBL, and its output is connected to the charge transfer circuit 160. Yes.

  In the charge transfer circuit 160, the output (node VT) of the transfer control circuit 270, that is, the other end of the ferroelectric capacitor 276 is n + 1 p-type MOS transistors connected to the dummy bit line DBL and the bit lines BL1 to BLn. 162 is connected to the gate. Then, the transfer control circuit 270 controls the voltage supplied to the gate of the p-type MOS transistor 162 based on the voltage of the dummy bit line DBL, so that the dummy bit line DBL becomes the dummy data line DDL and the bit line Whether or not BL1 to n are connected to the data lines DL1 to DLn is controlled.

  The precharge circuit 180 includes n + 1 p-type MOS transistors 182. In the p-type MOS transistor 182, the source is connected to the dummy data line DDL and the data lines DL1 to DLn, and the drain is grounded. Then, the p-type MOS transistor 182 precharges the voltages of the dummy data line DDL and the data lines DL1 to DLn to the ground voltage based on the voltage supplied to the gate.

  The negative voltage generation circuit 190 includes n + 1 ferroelectric capacitors 192 and an inverter 194. The ferroelectric capacitor 192 has one end connected to the dummy bit line DBL and the bit lines BL1 to n, and the other end connected to the output of the inverter 194. The inverter 194 receives the signal NEG as an input, and supplies the inverted signal to the other end of the ferroelectric capacitor 192.

  The voltage control circuit 200 generates a voltage to be supplied to the charge transfer circuit 160 and the precharge circuit 180. The voltage control circuit 200 includes inverters 202 to 206, ferroelectric capacitors 208 to 212, and p-type MOS transistors 214 to 228.

  The inverters 202 to 206 have inputs connected to the control signal generation circuit 300, and receive a signal VTG, a signal CLP2, and a signal CLP1, respectively, as inputs. The inverters 202 to 206 have their outputs connected to one ends of the ferroelectric capacitors 208 to 212, respectively, and each of the inverters 202 to 206 receives a predetermined voltage based on the voltages of the signal VTG, the signal CLP2, and the signal CLP1. Supply to the end.

  The other end of the ferroelectric capacitor 208 is connected to the source of the p-type MOS transistor 228. Then, the ferroelectric capacitor 208 generates a voltage to be supplied to the source of the p-type MOS transistor 228 based on the voltage supplied from the inverter 202 to one end of the ferroelectric capacitor 208. Specifically, when a ground voltage is supplied to one end, the ferroelectric capacitor 208 generates a predetermined negative voltage by coupling at the other end.

  In the p-type MOS transistor 214, the source is connected to the other end of the ferroelectric capacitor 208, the gate and drain are grounded, and the voltage of the node A1 is clamped. Specifically, the p-type MOS transistor 214 clamps the voltage at the node A1 so that the voltage does not increase too much at the node A1 when the drive voltage VCC is supplied to one end of the ferroelectric capacitor 208. It is configured as follows. For this reason, when the ground voltage is supplied to one end of the ferroelectric capacitor 208, the voltage of A1 becomes a negative voltage by being boosted in the minus direction starting from the clamped voltage. The p-type MOS transistor 216 has a source and a gate connected to the other end of the ferroelectric capacitor 208 and a drain connected to the ground, and clamps the voltage at the node A1. Specifically, the p-type MOS transistor 216 is generated by coupling, and the negative voltage supplied to the source of the p-type MOS transistor 228 becomes the threshold voltage of the p-type MOS transistor 162 or a voltage close thereto. It is configured to clamp the voltage at node A1.

  The other end of the ferroelectric capacitor 210 is connected to the gates of the p-type MOS transistor 228 and the p-type MOS transistor 182. Then, the ferroelectric capacitor 210 generates a voltage to be supplied to the gates of the p-type MOS transistor 228 and the p-type MOS transistor 182 based on the voltage supplied from the inverter 204 to one end of the ferroelectric capacitor 210. Specifically, when the ground voltage is supplied to one end, the ferroelectric capacitor 210 generates a voltage lower than twice the threshold voltage of the p-type MOS transistors 228 and 182 by coupling at the other end. To do. The ferroelectric capacitor 212 has the other end connected to the gate of the p-type MOS transistor 218, and generates a voltage to be supplied to the gate of the p-type MOS transistor 218 based on the voltage supplied to one end. .

  The p-type MOS transistor 218 has a source connected to the other end of the ferroelectric capacitor 210, a drain connected to the ground, and a node A3 to which the other end of the ferroelectric capacitor 210 is connected based on the voltage at the node A2. Is precharged to the ground voltage.

  The p-type MOS transistors 222 to 226 are diode-connected in series and clamp the voltage at the node A2. Specifically, the drain of the p-type MOS transistor 226 is grounded, and the gate and source of the p-type MOS transistor 222 are connected to the other end of the ferroelectric capacitor 212.

  In the p-type MOS transistor 220, the source is connected to the other end of the ferroelectric capacitor 212, the gate and drain are grounded, and the voltage of the node A2 is clamped. Specifically, the p-type MOS transistor 220 clamps the voltage at the node A2 so that the voltage does not rise too much at the node A2 when the drive voltage VCC is supplied to one end of the ferroelectric capacitor 212. It is configured as follows. For this reason, when the ground voltage is supplied to one end of the ferroelectric capacitor 212, the voltage of A2 becomes a negative voltage by being boosted in the minus direction starting from the clamped voltage.

  The sense amplifier 230 includes p-type MOS transistors 232-236, n-type MOS transistors 238-242, an inverter 244, and NOR circuits 246 and 248, and is connected to the bit lines BL1-n. Data stored in the memory cell MC is determined. Specifically, the sense amplifier 230 has a current mirror type configuration, and compares the voltage of the dummy data line DDL received as an input with the voltage of the data lines DL1 to DLn to compare the bit lines BL1 to n1. The data stored in the memory cell MC connected to is determined.

  That is, in the sense amplifier 230, the p-type MOS transistor 232 and the n-type MOS transistor 238, and the p-type MOS transistor 234 and the n-type MOS transistor 240 are respectively connected in series, and the dummy data line is connected to the gate of the p-type MOS transistor 232. The DDL is connected, and the data lines DL1 to DLn are connected to the gate of the p-type MOS transistor 234. The gates of the n-type MOS transistors 238 and 240 are connected to each other and further connected to the drain of the n-type MOS transistor 238.

  Then, the sense amplifier 230 compares the voltage supplied to the gate of the p-type MOS transistor 232 with the voltage supplied to the gate of the p-type MOS transistor 234 to compare the p-type MOS transistor 234 and the n-type MOS transistor 240. Inverted voltages at the connection point (drain) are output from the NOR circuits 246 and 248 as outputs OUT-D and outputs OUT-1 to OUT-n, respectively, as the comparison results.

  Further, the drive voltage VCC is supplied to the sources of the p-type MOS transistors 232 and 234 via the p-type MOS transistor 236, and the sources of the n-type MOS transistors 238 and 240 are supplied via the n-type MOS transistor 242. Is grounded. A signal SAON is supplied to the gate of the p-type MOS transistor 236 via the inverter 244, and a signal SAON is supplied to the gate of the n-type MOS transistor 242. That is, the p-type MOS transistor 236 and the n-type MOS transistor 242 control whether to operate the sense amplifier 230 based on the voltage of the signal SAON.

  FIG. 2 is a timing chart showing the operation of the ferroelectric memory device 100 of the present embodiment. With reference to FIGS. 1 and 2, the operation of the ferroelectric memory device 100 according to the present embodiment is described with reference to an example in which data stored in the memory cells MC connected to the word line WL1 and the bit line BL1 is read. explain. In the following example, data “0” is stored in the memory cells MC connected to the word line WL1 and the dummy bit line DBL, and data “1” is stored in the memory cells MC connected to the word line WL1 and the bit line BL1. Is remembered.

  In the following example, when each signal indicates L logic, the voltage of the signal is ground voltage (GND, reference voltage, 0 V), and when each signal indicates H logic, the signal voltage (potential) is ferroelectric. This is VCC, VDD, or VPP, which is a drive voltage (operating voltage, power supply voltage) of the memory device 100. The voltage of each signal is not limited to this, and it is sufficient that the voltage of the signal when indicating H logic is higher than the voltage of the signal when indicating L logic.

  First, in the initial state, the control signal generation circuit 300 outputs H logic as the signal PR, and each n-type MOS transistor 152 is on, so that the dummy bit line DBL and the bit lines BL1 to BLn are grounded.

  Next, the control signal generation circuit 300 sets the signal CLP1 to H logic. As a result, the output of the inverter 206 changes from H logic to L logic, so that the voltage at the other end of the ferroelectric capacitor 212, that is, the voltage at the node A2 becomes negative due to coupling, and the p-type MOS transistor 218 is turned on. Then, the node A3 is grounded.

  Next, the control signal generation circuit 300 sets the signal CLP1 to L logic and turns off the p-type MOS transistor 218, and sets the signal CLP2 to H logic. As a result, the voltage at the other end of the ferroelectric capacitor 210, that is, the voltage at the node A3 becomes a negative voltage by coupling, the p-type MOS transistor 228 is turned on, and the node VT is connected to the node A1. On the other hand, the p-type MOS transistor 182 is turned on, and the dummy data line DDL and the data lines DL1 to DLn are similarly grounded.

  Further, the control signal generation circuit 300 sets the signal PR to L logic, sets the dummy bit line DBL and the bit lines BL1 to BLn to the floating state, and the word line control circuit 120 increases the voltage of the word line WL1 to increase the word line The n-type MOS transistor TR constituting the memory cell MC connected to WL1 is turned on. Thereby, the ferroelectric capacitor C constituting the memory cell MC connected to the word line WL1 is connected to the dummy bit line DBL and the bit lines BL1 to n.

  Next, the control signal generation circuit 300 sets the signal VTG to H logic. As a result, the output of the inverter 202 changes from H logic to L logic, so that the voltage at the other end of the ferroelectric capacitor 208, that is, the voltage at the node A1 becomes a negative voltage due to coupling. Since the p-type MOS transistor 228 is on, the voltage of the node VT, that is, the gate of the p-type MOS transistor 162 is also a negative voltage. As described above, in this embodiment, when the signal VTG changes from the L logic to the H logic, the voltage of the node A1 becomes the threshold voltage (−Vth) of the p-type MOS transistor 162 or a voltage close thereto. Therefore, when the signal VTG changes from the L logic to the H logic, the node VT, that is, the gate of the p-type MOS transistor 162 is charged to the threshold voltage or a voltage close thereto.

  Next, the control signal generation circuit 300 sets the signal CLP2 to L logic, turns off the p-type MOS transistor 182 and the p-type MOS transistor 228, and sets the signal NEG to H logic. As a result, since the output of the inverter 194 changes from H logic to L logic, the voltage of the dummy data line DDL and the data lines DL1 to n connected to the ferroelectric capacitor 192 is charged to a negative voltage by coupling. .

  Next, the plate line control circuit 130 increases the voltage of the plate line PL1 to VCC. Accordingly, since the VCC is applied to the ferroelectric capacitor C constituting the memory cell MC connected to the word line WL1 with reference to the voltages of the dummy bit line DBL and the bit lines BL1 to BLn, the ferroelectric capacitor C In accordance with the data stored in, charges taken out from the ferroelectric capacitor C are discharged to the dummy bit line DBL and the bit lines BL1 to BLn.

  When the voltage of the dummy bit line DBL connected to the negative input of the operational amplifier 274 rises and the voltage difference from the ground voltage exceeds a predetermined voltage, the operational amplifier 274 sets its output to the L level. Therefore, the voltage at one end of the ferroelectric capacitor 276 decreases, and the capacitor 276 reduces the other end (node VT), that is, the gate voltage of the p-type MOS transistor 162 based on the decrease (by coupling). Lower. That is, the operational amplifier 274 compares the dummy bit line DBL with the ground voltage, amplifies and outputs the voltage difference, and lowers the gate voltage of the p-type MOS transistor 162 via the ferroelectric capacitor 276. As a result, the gate of each p-type MOS transistor 162 is turned on exceeding the threshold voltage (−Vth), and the dummy bit line DBL and the bit lines BL1 to BLn are connected to the dummy data line DDL via the p-type MOS transistor 162, respectively. And data lines DL1 to DLn.

  Here, in this embodiment, since the operational amplifier 274 is used, the output can be greatly lowered. In other words, a voltage considerably lower than the threshold value (Vth) of the p-type MOS transistor 162 can be output (see a waveform of the VT potential in FIG. 2).

  Therefore, the p-type MOS transistor 162 can be easily turned on even if the driving capability of the p-type MOS transistor 162 is reduced, that is, even if the element of the p-type MOS transistor 162 is formed small. In other words, the p-type MOS transistor 162 can operate at high speed even if the driving capability of the p-type MOS transistor 162 is reduced (the element of the p-type MOS transistor 162 is made smaller).

  FIG. 3 is a circuit diagram for explaining the effect of the present embodiment. Instead of the transfer control circuit 270 of the present application, a transfer control circuit 170 is used in FIG. As shown in the figure, when the transfer control circuit 170 is composed of ferroelectric capacitors 172 and 176, an inverter 174, a transmission gate 178, and an inverter 179, the output (node VT) of the transfer control circuit 170 is p The p-type MOS transistor 162 is turned on and off in the vicinity of the threshold (−Vth) of the type MOS transistor 162 (see the b waveform of the VT potential in FIG. 2).

  Therefore, when trying to realize the same reading speed as the circuit of FIG. 1 in the circuit of FIG. 3, for example, a p-type MOS transistor 162 having a size (driving capability) of about 10 times or more that of the circuit of FIG. . Moreover, since the load on the node VT increases as a result of increasing the size of the p-type MOS transistor 162, the speed cannot be increased as much as the circuit of FIG. Furthermore, even if the drive capability of the transfer control circuit 170 is increased in response to an increase in the load on the node VT, the circuit size is further increased, and the load on the inverter 174 is increased, so that a sufficiently high speed is achieved. Cannot be achieved.

  In FIG. 3, the ferroelectric capacitor 172 has one end connected to the dummy bit line DBL and the other end connected to the input of the inverter 174. The output of the inverter 174 is connected to one end of the ferroelectric capacitor 176, and the other end of the ferroelectric capacitor 176 is connected to the charge transfer circuit 160. That is, the transfer control circuit 170 is configured by connecting a ferroelectric capacitor 172, an inverter 174, and a ferroelectric capacitor 176 in series, its input is connected to the dummy bit line DBL, and its output is the charge transfer circuit 160. It is connected to the. The transmission gate 178 is connected to the input and output of the inverter 174, and the input and output of the inverter 174 are short-circuited based on the signal SH to the gate and the inverted signal of the signal SH output from the inverter 179. . Other configurations are the same as those in FIG.

  On the other hand, according to the present embodiment, since the element of the p-type MOS transistor 162 can be reduced, the circuit can be reduced in size or highly integrated. Further, even if the element of the p-type MOS transistor 162 is reduced, the reading speed can be maintained (high-speed operation is possible).

  Thus, when the p-type MOS transistor 162 is turned on, the dummy bit line DBL and the bit lines BL1 to n are connected to the dummy data line DDL and the data lines DL1 to n through the p-type MOS transistor 162 as described above. . Further, since the dummy data line DDL and the data lines DL1 to DLn are charged to a sufficiently lower voltage than the dummy bit line DBL and the bit lines BL1 to n, the dummy bit line DBL and the bit lines BL1 to n are connected to the dummy data line. When connected to the DDL and the data lines DL1 to n, the charges discharged from the ferroelectric capacitor C to the dummy bit line DBL and the bit lines BL1 to n are respectively connected to the dummy data line via the p-type MOS transistor 162. The data is transferred to DDL and data lines DL1 to DLn.

  Note that the amount of charge released to the bit lines BL1 to BLn when the data “1” is stored in the ferroelectric capacitor C is larger than that when the data “0” is stored. The bit line voltage rises high and Vgs increases. At this time, the charge transfer capability of the p-type MOS transistor 162 increases in proportion to the square of | Vgs−Vth |. Therefore, more charges are transferred at a higher speed in the former case.

  When charges are transferred from the dummy bit line DBL to the dummy data line DDL, the voltage of the dummy bit line DBL gradually decreases according to the transferred charge amount. When the voltage difference between the voltage of the dummy bit line DBL and the ground voltage becomes equal to or lower than a predetermined voltage, the output of the operational amplifier 274 becomes H level. Therefore, the voltage at one end of the ferroelectric capacitor 276 rises, and the capacitor 276 increases the other end (node VT), that is, the gate voltage of the p-type MOS transistor 162 based on the rise (by coupling). The value is raised to the vicinity of the threshold (−Vth). As a result, the p-type MOS transistor 162 is turned off, so that the dummy bit line DBL and the bit lines BL1 to n are electrically disconnected from the dummy data line DDL and the data lines DL1 to n, respectively, and the charge transfer is completed. .

  By the way, when data “1” is stored in the dielectric capacitor C, the BL voltage does not decrease even when the gate voltage of the p-type MOS transistor 162 increases, and the p-type MOS transistor 162 is completely Does not turn off. For this reason, the charge transfer continues slowly until the BL voltage decreases. Accordingly, the voltage of the data line DL1 to which the charge is transferred from the bit line BL1 connected to the ferroelectric capacitor C in which the data “1” is stored rises greatly to the voltage V1 and then gradually increases to the voltage V4. It rises (solid line in the figure).

  On the other hand, when data “0” is stored in the ferroelectric capacitor C, the voltage of the bit line BL is lower than the voltage of the dummy bit line DBL. Therefore, when the gate voltage of the p-type MOS transistor 162 increases, the charge transfer is completely completed. Therefore, the voltage of the data line DL1 rises at a high speed but only rises to the voltage V2 (dotted line in the figure).

  In addition, as described above, in this example, data “0” is stored in the ferroelectric capacitor C connected to the dummy bit line DBL, and the capacitance of the ferroelectric capacitor C is determined by the bit lines BL1 to n. Larger than the capacitance of the ferroelectric capacitor C connected to. Therefore, the voltage of the dummy bit line DBL is lower than the voltage of the bit line BL from which “1” data is discharged, and is higher than the voltage of the bit line BL from which “0” data is discharged. When charge is transferred from the DBL to the dummy data line DDL, the voltage of the dummy data line DDL rises to a voltage V3 between the voltage V1 and the voltage V2.

  Even when data “1” is stored in the ferroelectric capacitor C, the p-type MOS transistor 162 is delayed off by setting the charge transfer very fast and the operation of the operational amplifier slightly late. All charges can be transferred while In this case, the voltage of the data line DL1 to which charges are transferred from the bit line BL1 connected to the ferroelectric capacitor C in which the data “1” is stored rises to the voltage V4 at high speed.

  When the signal SAON becomes H logic and the sense amplifier 230 starts operation, the voltage V1 of the gate of the p-type MOS transistor 234 connected to the data line DL1 is the p-type MOS transistor 234 connected to the dummy data line DDL. Therefore, the voltage of the output OUT-1 is set to VCC as a comparison result.

  That is, when data “1” is stored in the ferroelectric capacitor C, the voltage of the gate of the p-type MOS transistor 234 is higher than the voltage of the gate of the p-type MOS transistor 232, and the sense amplifier 230 outputs the output OUT. It is determined that the data “1” is stored in the ferroelectric capacitor C with the voltages of −1 to n as VCC. On the other hand, in the sense amplifier 230, when data “0” is stored in the ferroelectric capacitor C, the voltage of the gate of the p-type MOS transistor 234 becomes lower than the voltage of the gate of the p-type MOS transistor 232. 230 determines that the data “0” is stored in the ferroelectric capacitor C by setting the voltages of the outputs OUT−1 to n to 0V. With the above operation, the data stored in the ferroelectric capacitor C is read in the ferroelectric memory device 100.

  In the above embodiment, since the transfer control circuit 270 controls the gate voltage of the p-type MOS transistor 162 based on the voltage of the dummy bit line DBL, the charges discharged to the bit lines BL1 to BLn are Based on the voltage of DBL, transfer to the data lines DL1 to DLn is controlled. Therefore, according to the above-described embodiment, it is not necessary to provide the transfer control circuit 270 for each of the bit lines BL1 to n. Therefore, even if a large number of memory cells MC are arranged in the ferroelectric memory device 100, it is possible to The circuit scale of the dielectric memory device 100 can be suppressed.

  Further, in the above-described embodiment, the charges discharged to the bit lines BL1 to n can be transferred to suppress the voltage rise of the bit lines BL1 to BLn. Therefore, according to the above embodiment, the voltage applied to the ferroelectric capacitor C can be increased. Therefore, when reading data, a large amount of charge is discharged from the ferroelectric capacitor C to the bit lines BL1 to BLn. Thus, the read margin is improved.

  In the above embodiment, since the sense amplifier 230 can determine data using the voltage of the dummy data line DDL as a reference voltage, the circuit scale of the ferroelectric memory device 100 can be further reduced.

  Further, according to the above embodiment, since the voltage of the dummy data line DDL can be adjusted by adjusting the capacitance of the ferroelectric capacitor C, the reference voltage can be generated very easily. In the above embodiment, even if the capacitance of the ferroelectric capacitor C changes due to, for example, process fluctuations, and the voltages of the data lines DL1 to DLn fluctuate, the voltage of the dummy data line DDL changes accordingly. To do. Therefore, according to the above embodiment, a desired reference voltage can be generated very easily.

  The examples and application examples described through the above-described embodiments of the present invention can be used in appropriate combination depending on the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above-described embodiments. Is not to be done.

  For example, the dummy bit line DBL and the bit lines BL1 to BLn may be precharged to VCC, the dummy data line DDL and the data lines DL1 to n to be precharged to a voltage higher than VCC, and the charge transfer circuit 160 may be configured by an n-type MOS transistor. Good.

  For example, data “1” may be stored in the ferroelectric capacitor C connected to the dummy bit line DBL. In this case, the capacitance of the ferroelectric capacitor C may be smaller than the capacitance of the ferroelectric capacitor C connected to the bit lines BL1 to BLn.

  Further, two dummy bit lines DBL may be prepared, and data “1” and data “0” may be stored in the ferroelectric capacitors C connected to the respective dummy bit lines DBL. In this case, the transfer control circuit 270 may be provided for each of the two dummy bit lines DBL, and the output VT may be short-circuited, or the operational amplifier 274 may be provided for each of the two dummy bit lines DBL, and the output thereof. May be short-circuited.

  Further, two dummy bit lines DBL connected to the ferroelectric capacitor C storing data “1” and data “0” are prepared in the same manner as described above, and both of the two dummy bit lines DBL are 2 It may be input to one operational amplifier 274 having two input terminals. At this time, the two − inputs are different from the + input in the operational amplifier 274, and may be connected to an input circuit including two transistors connected in parallel or two transistor groups connected in parallel.

  For example, each ferroelectric capacitor except the ferroelectric capacitor C may be a paraelectric capacitor.

  Further, the transfer control circuit 270 may be provided for each bit line including the dummy bit line DBL. In this case, although the number of transfer control circuits 270 used increases, the potential of all the bit lines can be maintained at the same potential with high speed and high accuracy by the action of the operational amplifier. For this reason, charge transfer to the data line can be performed at high speed and with high accuracy, and the difference in the charge discharged from the memory cell MC is accurately reflected in the read result. In this manner, the operation speed can be increased while increasing the read margin of the circuit.

1 is a circuit diagram showing a ferroelectric memory device of the present embodiment. 3 is a timing chart showing the operation of the ferroelectric memory device of the present embodiment. It is a circuit diagram for demonstrating the effect of this Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Ferroelectric memory device, 110 ... Memory cell array, 120 ... Word line control circuit, 130 ... Plate line control circuit, 150 ... Precharge circuit, 160 ... Charge transfer circuit , 170 ... transfer control circuit, 180 ... precharge circuit, 190 ... negative voltage generation circuit, 200 ... voltage control circuit, 230 ... sense amplifier, 270 ... transfer control circuit, 274 ... Operational amplifier, 276 ... Ferroelectric capacitor, 300 ... Control signal generation circuit, BL1 to n ... Bit line, DBL ... Dummy bit line, DL1 to n ... Data line, DDL ... Dummy data line, MC ... Memory cell, PL1-m ... Plate line, VT ... Node, WL1-m ... Word line

Claims (7)

(A) a first memory cell and a second memory cell for storing predetermined data;
(B) a first bit line connected to the first memory cell and a second bit line connected to the second memory cell;
(C) a first data line and a second data line having a predetermined capacity;
(D) When charges accumulated in the first memory cell and the second memory cell are discharged to the first bit line and the second bit line, respectively, the first bit line and A first charge transfer unit and a second charge transfer unit for transferring charges discharged to the second bit line to the first data line and the second data line, respectively.
(E) an operational amplifier that compares the first bit line with a reference voltage, amplifies the voltage difference, and outputs the amplified voltage difference;
A transfer control unit for controlling the first charge transfer unit and the second charge transfer unit in response to the output;
(F) a determination unit that determines data stored in the second memory cell based on a voltage of the second data line to which electric charge has been transferred from the second bit line;
A ferroelectric memory device comprising:   2. The ferroelectric memory device according to claim 1, wherein the first charge transfer unit and the second charge transfer unit include MOS transistors. The first charge transfer unit and the second charge transfer unit include p-type MOS transistors,
The operational amplifier compares the first bit line with a ground voltage, amplifies the voltage difference, and the transfer control unit outputs a voltage lower than a threshold value of the p-type MOS transistor. 3. The ferroelectric memory device according to 1 or 2.   The determination unit compares the voltage of the first data line and the voltage of the second data line to determine the data stored in the second memory cell. The ferroelectric memory device according to any one of 1 to 3.   5. The ferroelectric memory device according to claim 1, wherein a capacity of the first memory cell is different from a capacity of the second memory cell. 6. (A) a memory cell for storing predetermined data;
(B) a bit line connected to the memory cell;
(C) a data line having a predetermined capacity;
(D) a charge transfer unit that transfers the charge released to the bit line to the data line when the charge accumulated in the memory cell is released to the bit line;
(E) an operational amplifier that compares the bit line with a reference voltage, amplifies the voltage difference, and outputs the amplified voltage difference;
A transfer control unit that controls the charge transfer unit in response to the output;
A ferroelectric memory device comprising: An electronic apparatus comprising the ferroelectric memory device according to claim 1.

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