JP2007150244A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a semiconductor device that a resistance of wiring in a gate electrode is small and a resistance of contact between the gate electrode and a shared contact plug is small. <P>SOLUTION: The semiconductor device includes fully silicified, first gate wiring 19A formed on a semiconductor substrate 10, a first sidewall 21A formed on the side of the first gate wiring 19A, and an impurity diffused layer 14B formed in an active area 12. On an inter-layer insulating film 35 formed in the semiconductor substrate 10, a shared contact plug 24 connected with the first gate wiring 19A and impurity diffused layer 14B is formed. The first gate wiring 19A has a protrusion 20A protruded from the first sidewall 21A in its portion connected with the shared contact plug 24. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a gate wiring fully silicided and having a local wiring structure and a manufacturing method thereof.

  In recent years, along with higher integration, higher functionality, and higher speed of semiconductor devices, there is an increasing demand for miniaturization of semiconductor devices. With the miniaturization of semiconductor devices, the contact resistance and wiring resistance of the gate electrode tend to increase. In order to reduce the contact resistance and wiring resistance, the gate electrode is silicided.

  In addition, wiring resistance is reduced by using a local wiring structure such as a wiring connecting a gate electrode and a source / drain diffusion layer formed inside a semiconductor device.

  For example, a shared contact plug that electrically connects a gate electrode and a source / drain diffusion layer is formed by forming a contact hole exposing a part of the gate electrode and a part of the source / drain diffusion layer in the interlayer insulating film. The hole can be formed by filling a conductive material (see, for example, Patent Document 1).

  FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device including a conventional shared contact plug. As shown in FIG. 8, the conventional semiconductor device includes a gate electrode 103 made of silicon formed on a silicon substrate 101 via a gate oxide film 102. A silicide layer 104 is formed on the gate electrode 103, and a sidewall oxide film 105 is formed on the sidewalls of the gate electrode 103 and the silicide layer 104. A source / drain region 106 is formed on the silicon substrate 101 below the side of the gate electrode 103, and a silicide layer 107 is formed on the source / drain region 106 to cover the gate electrode 103 and the source / drain region 106. An interlayer oxide film 108 is formed. A contact hole 109 is formed in the interlayer oxide film 108 so as to expose a part of the gate electrode 103 and a part of the source / drain region 106, and a shared contact plug 110 is formed in the contact hole 109. The shared contact plug 110 is electrically connected to the gate electrode 103 and the source / drain region 106.

By using such a shared contact plug, it is possible to reduce the size of the semiconductor device, reduce the wiring resistance by using the local wiring structure, and realize a semiconductor device that operates at high speed.
JP-A-8-181205

  However, as a result of various studies on the conventional semiconductor device provided with the shared contact plug, the inventors of the present application have developed a silicide layer on the gate electrode 103 made of silicon as the gate electrode is further miniaturized. It has been found that the configuration in which 104 is formed has a problem that the wiring resistance increases and the contact area between the gate electrode 103 and the shared contact plug 110 decreases, so that the contact resistance increases.

  On the other hand, in recent years, full silicidation of a gate electrode has been studied in order to increase the speed of a semiconductor device, and it is expected to reduce wiring resistance by full silicidation of the gate electrode. However, the problem of an increase in contact resistance due to a decrease in the contact area between the gate electrode and the shared contact plug still occurs.

  An object of the present invention is to solve the above-mentioned conventional problems and to realize a semiconductor device in which the wiring resistance in the gate electrode is small and the contact resistance between the gate electrode and the shared contact plug is small.

  In order to achieve the above object, according to the present invention, a semiconductor device has a configuration in which a gate wiring has a protruding portion protruding from a sidewall in a shared contact plug formation region.

  Specifically, a semiconductor device according to the present invention includes an element isolation region formed in a semiconductor substrate, an active region that is a region surrounded by the element isolation region in the semiconductor substrate, and a full silicidation formed on the semiconductor substrate. Formed on a semiconductor substrate, an insulating first sidewall formed on a side surface of the first gate wiring, an impurity diffusion layer formed in an active region, and a semiconductor substrate; An interlayer insulating film having an opening that exposes a region spanning part of the first gate wiring and part of the impurity diffusion layer, and a conductive material formed in the opening, and the first gate wiring and impurities A contact plug connected to the diffusion layer is provided, and the first gate wiring has a protruding portion protruding from the first sidewall at a portion connected to the contact plug.

  According to the semiconductor device of the present invention, since the first gate wiring has the protruding portion protruding from the first sidewall at the portion electrically connected to the contact plug, the shared contact plug and the gate are provided. The contact area with the wiring can be increased. Therefore, the contact resistance between the gate wiring and the shared contact plug can be reduced. Further, since the gate wiring is fully silicided, the wiring resistance of the gate wiring can be reduced.

  In the semiconductor device of the present invention, it is preferable that the protruding portion of the first gate wiring covers a part of the upper surface of the first sidewall. With such a configuration, the sidewall can be protected by the protrusion when the contact hole for the shared contact plug is formed. Accordingly, since the sidewall is hardly etched when forming the contact hole, it is possible to prevent the shallow impurity diffusion layer from being exposed on the bottom surface of the contact hole. As a result, it is possible to realize a semiconductor device in which the shared contact plug and the shallow impurity diffusion layer are not short-circuited and the junction breakdown voltage is not reduced and the junction leakage current is not increased.

  In the semiconductor device of the present invention, the first gate wiring includes a first gate electrode and a first wiring formed integrally with the first gate electrode, and the contact plug is connected to the first wiring. The projecting portion is provided at a portion of the first wiring connected to the contact plug, and the first gate electrode preferably does not project from the first sidewall. With such a configuration, when a contact plug connected to the source / drain region is formed in addition to the shared contact plug, it is possible to prevent the contact plug and the gate electrode from being short-circuited.

  In the semiconductor device of the present invention, the first sidewall is formed on the side surface of the first gate electrode so that the height of the portion formed on the side surface of the portion where the projecting portion is provided in the first wiring is formed. It is preferable that the height is lower than the height of the portion. With such a configuration, it becomes easy to form a protruding portion that covers the upper surface of the sidewall, and the sidewall can be reliably protected.

  In the semiconductor device of the present invention, the first gate wiring is preferably formed on the active region via a first gate insulating film.

  The semiconductor device according to the present invention includes a second gate wiring formed on the semiconductor substrate at a distance from the first gate wiring and fully silicided, and below the second gate wiring on the active region. A second gate insulating film formed in the portion; and an insulating second sidewall formed on a side surface of the second gate wiring; and the impurity diffusion layer includes a second gate in the active region. It is preferable that the source / drain region be formed in a region between the wiring and the first gate wiring.

  In the semiconductor device of the present invention, the source / drain region has a first diffusion layer formed in a region of the active region lateral to the second gate wiring and a second diffusion layer as compared with the first diffusion layer in the active region. A second diffusion layer formed at a position far from the gate wiring and deeper than the first diffusion layer, and the contact plug is electrically connected to the second diffusion layer. preferable.

  In the semiconductor device of the present invention, the second gate wiring includes a second gate electrode and a second wiring formed integrally with the second gate electrode, and the second gate electrode includes the second gate electrode It is preferable that the gate insulating film is formed on the gate insulating film and does not protrude from the second sidewall.

  In the semiconductor device of the present invention, the first gate wiring is preferably made of nickel silicide.

  The semiconductor device of the present invention preferably further includes a base protective film formed between the interlayer insulating film and the semiconductor substrate.

  In the semiconductor device of the present invention, the contact plug is preferably electrically connected to the impurity diffusion layer through a silicide layer.

  The method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming an element isolation region in a semiconductor substrate and forming an active region surrounded by the element isolation region in the semiconductor substrate, and a step after the step (a). And (b) forming a first gate wiring formation film made of a semiconductor material containing silicon on the semiconductor substrate, and forming an insulating first sidewall on the side surface of the first gate wiring formation film. Step (c) for forming, step (d) for forming an impurity diffusion layer in the active region after step (b), and formation of the first gate wiring after step (c) and step (d) A step (e) of forming a first gate wiring by fully siliciding the film; a step (f) of forming an interlayer insulating film on the entire surface of the semiconductor substrate after the step (e); and etching the interlayer insulating film A portion of the first gate wiring and the impurity diffusion layer A step (g) of forming an opening in a region straddling the portion, and a step of forming a contact plug electrically connected to the first gate wiring and the impurity diffusion layer by filling the opening with a conductive material (H), and the step (e) is characterized in that a protruding portion protruding from the first sidewall is formed in a portion connected to the contact plug in the first gate wiring.

  According to the method of manufacturing a semiconductor device of the present invention, the protruding portion protruding from the first sidewall is formed in the portion connected to the contact plug in the first gate wiring, so that the shared contact plug is formed. When the recess is formed, the first sidewall is protected by the protruding portion, so that the first sidewall is hardly etched. As a result, it is possible to prevent a short circuit between the shared contact plug and the shallow impurity diffusion layer, and to realize a semiconductor device in which the junction breakdown voltage does not decrease and the junction leakage current does not increase.

  In the method for manufacturing a semiconductor device of the present invention, in the step (e), it is preferable that the protruding portion of the first gate wiring is formed so as to cover a part of the upper surface of the first sidewall.

  In the method for manufacturing a semiconductor device of the present invention, in the step (e), a first gate wiring in which the first gate electrode and the first wiring are integrally formed is formed from the first gate wiring forming film, and the manufacturing is performed. In the method, between the step (d) and the step (e), a portion to be the first gate electrode in the first gate wiring formation film is etched, so that the first gate in the first gate wiring formation film is etched. The method further includes a step (i) in which a film thickness of a portion to be an electrode is made thinner than a film thickness of a portion of the gate wiring formation film where the protruding portion of the first wiring is formed. It is preferable that the gate electrode does not protrude from the first sidewall.

  In the method for manufacturing a semiconductor device of the present invention, in step (i), the film thickness of the portion of the first gate wiring formation film that becomes the protruding portion of the first wiring is set to two times the height of the first sidewall. It is preferable to set it to 1 or more. By setting it as such a structure, it becomes possible to form a protrusion part reliably.

  In the method for manufacturing a semiconductor device of the present invention, in the method for manufacturing a semiconductor device, in step (i), the film thickness of the portion to be the first gate electrode in the first gate wiring formation film is changed to the thickness of the first sidewall. It is preferable to be less than half of the height. With this configuration, it is possible to form a normal gate wiring that does not protrude from the sidewall in a region where the shared contact plug is not formed.

  In the method for manufacturing a semiconductor device of the present invention, the side formed on the side surface of the portion of the first gate wiring formation film that becomes the protruding portion of the first wiring between the steps (i) and (e). And (j) further comprising a step (j) of making the height of the wall lower than the height of the first sidewall formed on the side surface of the portion to be the first gate electrode in the first gate wiring formation film. Is preferred. With such a configuration, it is easy to form a protruding portion that covers the upper surface of the first sidewall.

  In the method for manufacturing a semiconductor device of the present invention, in step (j), the height of the first sidewall is made lower than the height of the upper surface of the first gate wiring formation film in the region where the protrusion is formed. Is preferred.

  The method for manufacturing a semiconductor device of the present invention further includes a step (k) of forming a base protective film on the entire surface of the semiconductor substrate between the step (e) and the step (f). In the step (f), It is preferable to form an interlayer insulating film over the base insulating film.

  In the method for manufacturing a semiconductor device of the present invention, in the step (b), a second gate wiring formation film made of a semiconductor material containing silicon is formed on the semiconductor substrate at a distance from the first gate wiring formation film. In step (c), an insulating second sidewall is formed on the side surface of the second gate wiring formation film. In step (d), the side of the second gate wiring formation film in the active region is formed. In the step (e), the second gate wiring is preferably formed by fully siliciding the second gate wiring formation film in the step (e).

  The method for manufacturing a semiconductor device of the present invention further includes a step (l) of forming a gate insulating film on the active region between the step (a) and the step (b), and in the step (b), the active region is formed. It is preferable to form a first gate wiring formation film and a second gate wiring formation film on the gate insulating film.

  According to the semiconductor device and the manufacturing method thereof of the present invention, the wiring resistance in the gate electrode and the contact resistance between the gate electrode and the shared contact plug can be reduced.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings. 1A and 1B show a semiconductor device according to the first embodiment, where FIG. 1A shows a planar configuration, and FIG. 1B shows a cross-sectional configuration taken along line Ib-Ib in FIG. .

  In FIG. 1A, the first transistor 51A formed in the first active region 13A surrounded by the element isolation region 11 formed in the semiconductor substrate 10 and the second active region 13B are formed. A second transistor 51B is shown. The first transistor 51A has a fully-silicided first gate electrode 17A and a source / drain region 14A formed in the first active region 13A. The second transistor 51B has a fully silicided second gate electrode 17B and a source / drain region 14B formed in the second active region 13B. The first transistor 51A and the second transistor 51B are both P-type MIS transistors.

  As shown in FIG. 1B, the second transistor 51B includes a second gate insulating film 15B formed on the second active region 13B surrounded by the element isolation region 11 of the semiconductor substrate 10, and a second gate insulating film 15B. The second gate electrode 17B formed on the second gate insulating film 15B, the second sidewall 21B formed on the side surface of the second gate electrode 17B, and the second active region 13B. And a source / drain region 14B which is a P-type impurity diffusion layer formed in regions on both sides of the gate electrode 17B.

  The source / drain region 14B includes a shallow source / drain diffusion layer (extension region or LDD region) 14a formed under the side of the second gate electrode 17B and a deep source formed under the side of the second sidewall 21B. A silicide layer 16 is formed on the upper surface of the deep source / drain diffusion layer 14b.

  On the second active region 13B, a first gate insulating film 15A made of the same insulating film as the second gate insulating film 15B and a full silicide formed on the first gate insulating film 15A are formed. The first wiring 18A and the first side wall 21A formed on the side surface of the first wiring 18A are formed. The first wiring 18A has a protruding portion 20A that protrudes from the first sidewall 21A and covers a part of the upper surface of the first sidewall 21A. As shown in FIG. 1A, the first wiring 18A is integrally formed with the first gate electrode 17A of the first transistor 51A. The first wiring 18A is formed by the first gate electrode 17A and the first wiring 18A. A first gate wiring 19A that is fully silicided is formed.

  The second gate electrode 17B is integrally formed with the fully-silicided second wiring 18B as shown in FIG. 1A, and the second gate electrode 17B, the second wiring 18B, Thus, the second gate wiring 19B which is fully silicided is formed. The second wiring 18B extends over the element isolation region 11 and the first active region 13A, and is connected to the source / drain region 14A by the shared contact plug 24. A protruding portion 20B is formed in the region where the shared contact plug 24 is formed in the second wiring 18B. The configuration of the second wiring 18B in which the protruding portion 20B is formed is the same as the configuration of the first wiring 18A in which the protruding portion 20A shown in FIG. 1B is formed.

  A base protective film 34 made of a silicon nitride film is provided on the semiconductor substrate 10 so as to cover the second gate electrode 17B, the first wiring 18A, the first sidewall 21A, the second sidewall 21B, and the like. An interlayer insulating film 35 made of a silicon oxide film is formed on the underlying protective film 34.

  In one of the deep source / drain diffusion layers 14b formed on both sides of the second gate electrode 17B in the second active region 13B, the interlayer insulating film 35 extends over one region so as to straddle the first wiring 18A. In addition, a shared contact plug 24 formed through the base protective film 34 is formed, and a contact plug 25 formed through the interlayer insulating film 35 and the base protective film 34 is formed on the other region. Is formed. The contact plug 25 and the shared contact plug 24 are made of a conductive material such as tungsten filled in the contact hole, and are connected to the deep source / drain diffusion layer 14b through the silicide layer 16, respectively.

  In the semiconductor device according to the present embodiment, the first wiring 18A has a protruding portion 20A protruding from the first sidewall 21A at a portion of the first wiring 18A connected to the shared contact plug 24. Since the width of the protruding portion 20A is wider than the width of the first wiring 18A, the contact area between the first gate wiring 19A and the shared contact plug 24 increases. Therefore, the contact resistance between the first gate line 19A and the shared contact plug 24 can be reduced.

  Further, since the protruding portion 20A covers a part of the upper surface of the first sidewall 21A, the protruding portion 20A functions as an etching mask when forming contact holes in the interlayer insulating film 35 and the base protective film 34. It is possible to suppress the etching of the first sidewall 21A. As a result, when the contact hole for the shared contact plug is formed, it is possible to prevent the shallow source / drain diffusion layer 14a from being exposed. As a result, it is possible to suppress a decrease in junction breakdown voltage and an increase in junction leakage current due to a short circuit between the shared contact plug 24 and the shallow source / drain diffusion layer 14a.

  Similarly, the second wiring 18B has a protruding portion 20B protruding from the second sidewall 21B at a portion connected to the shared contact plug 24 of the second wiring 18B, and the protruding portion 20B is the second side. A part of the upper surface of the wall 21B is covered, and the contact resistance between the second gate wiring 19B and the shared contact plug 24 is also reduced.

  The method for manufacturing the semiconductor device according to the present embodiment will be described below with reference to the drawings. 2 to 4 show cross-sectional configurations in the order of steps in the method of manufacturing the semiconductor device according to the first embodiment. 2 to 4 show cross sections taken along line Ib-Ib in FIG.

  First, as shown in FIG. 2A, an element isolation region 11 for electrically isolating elements is formed on a semiconductor substrate 10 by, for example, an STI (shallow trench isolation) method. As a result, a second active region 13B surrounded by the element isolation region 11 is formed in the semiconductor substrate 10. Subsequently, boron, which is a P-type impurity, is ion-implanted into the semiconductor substrate 10 to form a P-type well 12.

  Next, as shown in FIG. 2B, gate insulation made of silicon oxide having a thickness of 2 nm is formed on the second active region 13B by a dry oxidation method, a wet oxidation method, an oxidation method using radical oxygen, or the like. A film 15 is formed. Subsequently, a polysilicon film 22 having a thickness of 80 nm to be a gate electrode is deposited on the entire surface of the semiconductor substrate 10 by, for example, a CVD (chemical vapor deposition) method, and then the polysilicon film 22 is formed on the polysilicon film 22 later. In this step, a silicon oxide film 23 having a thickness of 60 nm, which serves as a protective film for the polysilicon film 22, is formed by, for example, a CVD method. At this time, the film thickness of the silicon oxide film 23 is made smaller than the film thickness of the polysilicon film 22.

  Next, as shown in FIG. 2C, the first protection is performed by patterning the silicon oxide film 23 into a gate wiring shape (a shape in which the gate electrode and the wiring are integrated) by photolithography and dry etching. A film 23A and a second protective film 23B are formed.

  Subsequently, using the patterned first protective film 23A and second protective film 23B as a mask, the polysilicon film 22 and the gate insulating film 15 are etched by dry etching. Thereby, the first gate wiring forming film 22A and the first gate insulating film 15A, and the second gate wiring forming film 22B and the second gate insulating film 15B are formed.

  Subsequently, boron (B), which is a P-type impurity, is ion-implanted into the second active region 13B using the first gate wiring formation film 22A and the second gate wiring formation film 22B as a mask, thereby forming a shallow P-type. A source / drain diffusion layer 14a is formed.

  For etching the silicon oxide film 23, an etching gas mainly containing fluorocarbon may be used, and for etching the polysilicon film 22, an etching gas mainly containing chlorine or bromine may be used.

  Next, as shown in FIG. 2D, a silicon nitride film having a film thickness of, for example, 50 nm is deposited over the entire surface of the semiconductor substrate 10 by, for example, a CVD method, and then the deposited silicon nitride film is applied. Anisotropic etching is performed. As a result, the silicon formed on the side surfaces of the first gate wiring formation film 22A and the first protective film 23A and the portions formed on the side surfaces of the second gate wiring formation film 22B and the second protective film 23B. The nitride film is removed. As a result, the first sidewall 21A that continuously covers both side surfaces of the first gate wiring formation film 22A and the first protective film 23A, the second gate wiring formation film 22B, and the second protective film 23B. A second sidewall 21B that continuously covers both side surfaces is formed.

  Next, as shown in FIG. 2E, boron, which is a P-type impurity, is introduced into the second active region 13B by ion implantation using the first sidewall 21A and the second sidewall 21B as a mask, P-type deep source / drain diffusion layers 14b are formed in regions on both sides of the second gate wiring formation film 22B (outside the second sidewall 21B) in the second active region 13B. As a result, a source / drain region 14B composed of a shallow source / drain diffusion layer 14a and a deep source / drain diffusion layer 14b is formed.

  Subsequently, after removing the natural oxide film formed on the upper surface of the deep source / drain diffusion layer 14b, a nickel film (not shown) having a film thickness of 10 nm is deposited on the semiconductor substrate 10 by sputtering. Thereafter, for example, the first RTA (rapid thermal annealing) at a temperature of 320 ° C. is performed on the semiconductor substrate 10 in a nitrogen atmosphere to react the silicon constituting the semiconductor substrate 10 with the nickel film.

  Next, for example, the remaining unreacted nickel film is removed using a mixed acid of hydrochloric acid and hydrogen peroxide solution, and then the semiconductor substrate 10 is subjected to the second time at a temperature higher than the first RTA (for example, 550 ° C.). Perform RTA. Thereby, the low resistance silicide layer 16 is formed on the upper surface of the deep source / drain diffusion layer 14b.

  Next, as shown in FIG. 3A, a protective film 32 made of a silicon oxide film serving as a mask for full silicidation is formed on the entire surface of the semiconductor substrate 10, and then the protective film 32 is formed by CMP. The surface is planarized and polished until the upper surfaces of the first protective film 23A and the second protective film 23B are exposed.

Next, as shown in FIG. 3B, the first gate wiring formation film 22A is formed by using a dry etching method or a wet etching method under conditions for selectively etching silicon oxide with respect to silicon nitride and polysilicon. The upper portions of the first protective film 23A, the second protective film 23B, and the protective film 32 are etched until the upper surface of the second gate wiring formation film 22B is exposed. In order to selectively etch the silicon oxide film, in the case of the dry etching method, for example, C ₅ F ₈ , O ₂ and Ar are respectively 15 ml / min (standard state) and 18 ml / min (standard state). And at a flow rate of 950 ml / min (standard state) at a pressure of 6.7 Pa, a high frequency (RF) output (T / B) of 1800 W / 1500 W, and a substrate temperature of 0 ° C. Ion etching may be performed.

  Next, as shown in FIG. 3C, a resist mask 41 is formed to cover a portion of the first gate wiring formation film 22A that is connected to the shared contact plug 24 in a later step. Here, the resist mask 41 is formed in a region where the protrusion 20A is formed in a later step. Subsequently, the first gate wiring formation film 22A and the second gate wiring formation film 22B are etched to remove the portion covered with the resist mask 41 by dry etching, so that the film thickness becomes 40 nm. Although not shown, a resist mask is also formed in the region where the protruding portion 20B is formed for the second gate wiring formation film 22B so that it is not etched.

  Next, as shown in FIG. 3D, after removing the resist mask 41, a metal film 33 made of nickel having a thickness of 100 nm is deposited on the protective film 32 by sputtering. Subsequently, by performing RTA at 400 ° C. on the semiconductor substrate 10 in a nitrogen atmosphere, the first gate wiring formation film 22A and the second gate wiring formation film 22B react with the metal film 33 to fully silicide. To do. Note that the thickness of the metal film 33 is 1.1 times or more of the thickness of the region where the protruding portion 20A is formed in the first gate wiring formation film 22A, whereby the first gate wiring formation film 22A and the first gate wiring formation film 22A. Thus, the full silicidation of the second gate wiring formation film 22B can be performed reliably.

  Next, as shown in FIG. 3E, by removing the unreacted metal film 33, the first wiring 18A having the protruding portion 20A protruding from the first sidewall 21A and the first sidewall A fully silicided first gate wiring 19A (see FIG. 1) is formed which includes the first gate electrode 17A (see FIG. 1) that does not protrude from 21A. At the same time, the second wiring 18B (see FIG. 1) having the protruding portion 20B (see FIG. 1) protruding from the second sidewall 21B and the second gate electrode 17B not protruding from the second sidewall 21B. A fully silicided second gate wiring 19B (see FIG. 1) is formed.

  Next, as shown in FIG. 4A, after the protective film 32 is removed by using a dry etching method or a wet etching method, a base made of a silicon nitride film having a thickness of 50 nm is formed on the entire surface of the semiconductor substrate 10. The protective film 34 is deposited by, for example, the CVD method.

  Next, as shown in FIG. 4B, after an interlayer insulating film 35 made of a silicon oxide film is formed on the base protective film 34 by, for example, the CVD method, the surface of the interlayer insulating film 35 is planarized by the CMP method. To do. Thereafter, a resist mask (not shown) is formed on the interlayer insulating film 35, and then the interlayer insulating film 35 and the base protective film 34 are dry-etched using the resist mask, whereby one deep source / drain diffusion layer is formed. A first contact hole 35a exposing a part of the silicide layer 16 on the part 14b, a part of the first side wall 21A, and a part of the protruding part 20A of the first wiring 18A is formed. At the same time, a second contact hole 35b exposing a part of the silicide layer 16 on the other deep source / drain diffusion layer 14b is formed.

  Next, as shown in FIG. 4C, after removing the resist mask, titanium (Ti) and titanium nitride (TiN), which serve as a barrier metal layer, are formed on the semiconductor substrate 10 by a CVD method to 10 nm and 10 nm, respectively. Deposit 5 nm (not shown). Thereafter, a metal film made of tungsten or the like is deposited on the deposited barrier metal layer.

  Subsequently, the metal film on the interlayer insulating film 35 deposited outside the first contact hole 35a and the second contact hole 35b is removed by CMP or etch back. Thus, the shared contact plug 24 connected to the silicide layer 16 and the first wiring 18A on one deep source / drain diffusion layer 14b, and the contact plug 25 connected to the silicide layer 16 on the other deep source / drain diffusion layer 14b. And are formed.

  In the manufacturing method of the semiconductor device of this embodiment, full silicidation is performed by making the film thickness of the portion of the first gate wiring formation film 22A where the protruding portion 20A is formed thicker than other portions. As a result, the fully silicided first gate wiring 19 </ b> A having the protruding portion 20 </ b> A in the region where the shared contact plug 24 is formed can be easily formed. Therefore, a semiconductor device having a small contact resistance between the shared contact plug 24 and the first gate electrode 17A can be easily formed.

  In addition, the protruding portion 20A of the first wiring 18A covering the upper surface of the first sidewall 21A serves as an etching mask when forming the first contact hole 35a, thereby suppressing the etching of the first sidewall 21A. It is possible. Therefore, even when the shared contact plug 24 is formed, it is possible to manufacture a semiconductor device in which the junction breakdown voltage does not decrease and the junction leakage current does not increase.

  In order to form the protruding portion 20A that covers the upper surface of the first sidewall 21A, the thickness of the first gate wiring formation film 22A in the region where the protruding portion 20A is to be formed is 2 times the height of the first sidewall 21A. The first gate wiring formation film 22 </ b> A may be fully silicided in a state of 1 / min or more.

  In the manufacturing method of the semiconductor device of the present embodiment, the height of the first sidewall 21A is the same as the thickness of the first gate wiring formation film 22A and the first protective film 23A in the region where the protrusion 20A is formed. It is almost equal to the sum of the film thickness. In the present embodiment, the film thickness of the first gate wiring formation film 22A is 80 nm, and the film thickness of the first protective film 23A is 60 nm. Accordingly, the height of the first sidewall 21A is 140 nm, and the film thickness of the first gate wiring formation film 22A in the region where the protruding portion 20A is formed is one half or more of the height of the first sidewall 21A. Become.

The film thickness of the metal film 33 deposited on the first gate wiring formation film 22A during full silicidation is 100 nm, and the film of the first gate wiring formation film 22A in the region where the protruding portion 20A is formed. The thickness is 1.1 times or more. Thus, under the condition where nickel is more than silicon, Ni ₂ Si and Ni ₃ Si are formed during silicidation. By forming Ni ₂ Si and Ni ₃ Si, the film thickness after silicidation expands to about twice that of the polysilicon film.

  In the region where the shared contact plug 24 is formed, that is, the region where the protruding portion 20A is formed, the thickness of the first gate wiring formation film 22A is 80 nm, and the height of the first sidewall 21A is 140 nm. The first wiring 18A that is fully silicided and expands to about twice the thickness of the first gate wiring formation film 22A protrudes from the first sidewall 21A. Further, since the protruding portion 20A extends in the lateral direction, the upper surface of the first sidewall 21A is covered. Similarly, the protruding portion 20B of the second wiring 18B protrudes from the second sidewall 21B and covers the upper surface of the second sidewall 21B.

  On the other hand, in the region where the shared contact plug 24 is not formed, that is, the region where the second gate electrode 17B is formed, the thickness of the second gate wiring formation film 22B is etched to be 40 nm. Therefore, the second gate electrode 17B does not protrude from the second sidewall 21B even when fully silicided. Similarly, the first gate electrode 17A does not protrude from the first sidewall 21A.

  Note that the thicknesses of the polysilicon film 22, the silicon oxide film 23, and the metal film 33 may be appropriately changed according to the size of the element to be formed. Further, the region where the protruding portion 20A covers the upper surface of the first sidewall 21A can be adjusted by changing the ratio of the thickness of the polysilicon film 22 and the silicon oxide film 23.

  In the present embodiment, two transistors have been described as an example, but other transistors may be formed on the semiconductor substrate. An element other than a transistor may be formed, and the impurity diffusion layer connected by the shared contact plug is not limited to the source / drain diffusion layer, and may be, for example, an impurity diffusion layer in which a diode is formed.

  In the present embodiment, the first gate wiring 19A and the second gate wiring 19B are formed from the polysilicon film 22, but an amorphous silicon film may be used instead of the polysilicon film. Further, other semiconductor materials including silicon may be used.

  As the metal film 33 for full silicidation, a nickel film is used, but other metal films for full silicidation such as platinum may be used. Although nickel is used as a metal for forming the silicide layer 16, a metal for silicidation such as cobalt, titanium, or tungsten may be used instead. Moreover, instead of the sputtering method, a CVD method or the like may be used for depositing these metal films.

  Further, although the silicon nitride film is used for the sidewall, a laminated structure of a silicon oxide film and a silicon nitride film may be used.

  In this embodiment, the base protective film 34 covering the transistor is formed. However, the base protective film 34 is not necessarily formed. In this case, the interlayer insulating film 35 may be deposited on the protective film 32 without etching the protective film 32.

  Further, the base protective film 34 is deposited after the protective film 32 is etched. However, the base protective film 34 may be deposited before the protective film 32 is deposited. In this case, when polishing to the upper ends of the first protective film 23A and the second protective film 23B while planarizing the surface of the protective film 32 by CMP, the first protective film 23A and the second protective film 23A are polished. The underlying protective film 34 deposited on the protective film 23B may also be polished and removed.

(Second Embodiment)
The second embodiment of the present invention will be described below with reference to the drawings. 5A and 5B show a semiconductor device according to the second embodiment, where FIG. 5A shows a planar configuration, and FIG. 5B shows a cross-sectional configuration taken along line Vb-Vb in FIG. . In FIG. 5, the same components as those of FIG.

  As shown in FIG. 5B, in the semiconductor device of the present embodiment, the height of the first sidewall 21A in the region where the shared contact plug 24 is formed has a second gate electrode 17B of the second sidewall 21B. It is lower than the height of the part formed on the side surface. Therefore, the protruding portion 20A can be easily formed in the formation region of the shared contact plug 24, and the protruding portion 20A can reliably cover the upper surface of the first sidewall 21A. Other configurations are the same as those in the first embodiment.

  A method for manufacturing a semiconductor device according to the second embodiment will be described below with reference to the drawings. 6 and 7 show cross-sectional structures in the respective steps of the semiconductor device manufacturing method according to the present embodiment. The first gate wiring formation film 22B is etched until the thickness of the second gate wiring formation film 22B is less than half the height of the second sidewall 21B. Since it is the same as the process up to FIG. 3C in the embodiment, the description is omitted.

  As shown in FIG. 6A, a resist mask 42 is formed on the semiconductor substrate 10 so as to cover a region where a gate electrode is to be formed and to have an opening in a region where a protrusion is to be formed. Subsequently, using the resist mask 42, the exposed portions of the first sidewall 21 </ b> A and the second sidewall 21 </ b> B in the region where the protrusion is to be formed are etched to make the height lower than the other regions. In other words, the height of the first sidewall 21A and the second sidewall 21B in the region where the shared contact plug 24 is formed is the height of the portion formed on the side surface of the first gate electrode 17A of the first sidewall 21A and The height is made lower than the height of the portion formed on the side surface of the second gate electrode 17B of the second sidewall 21B.

  Next, as shown in FIG. 6B, after removing the resist mask 42, a metal film 33 made of nickel having a thickness of 100 nm is deposited on the protective film 32 by sputtering. Subsequently, by performing RTA at 400 ° C. on the semiconductor substrate 10 in a nitrogen atmosphere, the first gate wiring formation film 22A and the second gate wiring formation film 22B react with the metal film 33 to fully silicide. To do.

Next, as shown in FIG. 6C, by removing the unreacted metal film 33, the first wiring 18A having the protruding portion 20A protruding from the first sidewall 21A and the first sidewall A fully silicided first gate wiring 19A (see FIG. 5) is formed which includes the first gate electrode 17A (see FIG. 5) that does not protrude from 21A. At the same time, from the second wiring 18B (see FIG. 5) having the protruding portion 20B (see FIG. 5) protruding from the second sidewall 21B and the second gate electrode 17B not protruding from the second sidewall 21B. A fully silicided second gate wiring 19B (see FIG. 5) is formed.
Next, as shown in FIG. 7A, after the protective film 32 is removed by using a dry etching method or a wet etching method, a base made of a silicon nitride film having a thickness of 50 nm is formed on the entire surface of the semiconductor substrate 10. The protective film 34 is deposited by, for example, the CVD method.

  Next, as shown in FIG. 7B, an interlayer insulating film 35 made of a silicon oxide film is formed on the base protective film 34 by, for example, the CVD method, and then the surface of the interlayer insulating film 35 is planarized by the CMP method. To do. Thereafter, a resist mask (not shown) is formed on the interlayer insulating film 35, and then the interlayer insulating film 35 and the base protective film 34 are dry-etched using the resist mask, whereby one deep source / drain diffusion layer is formed. A first contact hole 35a exposing a part of the silicide layer 16 on the part 14b, a part of the first sidewall 21A, and a part of the protruding part 20A of the first wiring 18A is formed. At the same time, a second contact hole 35b exposing a part of the silicide layer 16 on the other deep source / drain diffusion layer 14b is formed.

  Next, as shown in FIG. 7C, a conductive material such as tungsten is embedded in the first contact hole 35a and the second contact hole 35b in the same manner as in the first embodiment. Thus, the shared contact plug 24 connected to the silicide layer 16 and the first wiring 18A on one deep source / drain diffusion layer 14b, and the contact plug 25 connected to the silicide layer 16 on the other deep source / drain diffusion layer 14b. And are formed.

  In the semiconductor device manufacturing method of the present embodiment, the height of the first sidewall 21A in the region where the shared contact plug 24 is formed is set lower than the height in other regions. Thereby, the first gate wiring 19A including the first wiring 18A having the protruding portion 20A and the first gate electrode 17A having no protruding portion can be easily formed. Further, by adopting the same configuration for the second side wall 21B, the second gate wiring 19B including the second wiring 18B having the protruding portion 20B and the second gate electrode 17B having no protruding portion can be easily formed. Can be formed.

  Thereby, when the first contact hole 35a for forming the shared contact plug 24 is formed, the etching of the first sidewall 21A can be suppressed. As a result, it is possible to suppress the occurrence of a leakage current caused by a short circuit between the shared contact plug 24 and the shallow source / drain diffusion layer 14a.

  The etching amount of the region where the protruding portion 20A of the first sidewall 21A is formed may be determined in consideration of the film thickness of the first gate wiring forming film 22A in the region where the protruding portion 20A is formed. In this case, the upper surface of the first sidewall 21A can be covered by making the upper surface of the first sidewall 21A lower than the upper surface of the first gate wiring formation film 22A in the region where the protruding portion 20A is formed. It becomes easy. The height of the first sidewall 21A after etching is preferably larger than the thickness of the base protective film 34.

  In the present embodiment, the first sidewall 21A is etched after the second gate wiring formation film 22B is etched. However, after the first sidewall 21A is etched, the second sidewall wiring film 22B is etched. The gate wiring formation film 22B may be etched.

  The present invention is useful as a semiconductor device in which a gate wiring is fully silicided and has a local wiring structure, a manufacturing method thereof, and the like.

(A) And (b) shows the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the Ib-Ib line | wire of (a). It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A) And (b) shows the semiconductor device which concerns on the 2nd Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the Vb-Vb line | wire of (a). It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. It is sectional drawing which shows the semiconductor device which concerns on a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Element isolation region 12 Well 13A 1st active region 13B 2nd active region 14A Source / drain region 14B Source / drain region 14a Shallow source / drain diffused layer 14b Deep source / drain diffused layer 15 Gate insulating film 15A 1st gate Insulating film 15B Second gate insulating film 16 Silicide layer 17A First gate electrode 17B Second gate electrode 18A First wiring 18B Second wiring 19A First gate wiring 19B Second gate wiring 20A Projecting portion 20B Protruding portion 21A First sidewall 21B Second sidewall 22 Polysilicon film 22A First gate wiring formation film 22B Second gate wiring formation film 23 Silicon oxide film 23A First protective film 23B Second protective film 24 Shared contact plug 25 Contact plug 32 Protective film 33 Metal film 34 Base protective film 35 Interlayer insulating film 35a First contact hole 35b Second contact hole 41 Resist mask 42 Resist mask 51A First transistor 51B Second transistor

Claims (21)

An element isolation region formed in a semiconductor substrate;
An active region which is a region surrounded by the element isolation region in the semiconductor substrate;
A first gate wiring formed on the semiconductor substrate and fully silicided;
An insulating first sidewall formed on a side surface of the first gate wiring;
An impurity diffusion layer formed in the active region;
An interlayer insulating film formed on the semiconductor substrate and having an opening exposing a region straddling a part of the first gate wiring and a part of the impurity diffusion layer;
A conductive plug formed in the opening, and comprising a contact plug connected to the first gate wiring and the impurity diffusion layer,
The semiconductor device according to claim 1, wherein the first gate wiring has a protruding portion protruding from the first sidewall at a portion connected to the contact plug. The semiconductor device according to claim 1,
The protruding portion of the first gate wiring covers a part of the upper surface of the first sidewall. The semiconductor device according to claim 1 or 2,
The first gate wiring includes a first gate electrode and a first wiring formed integrally with the first gate electrode,
The contact plug is connected to the first wiring;
The protrusion is provided in a portion connected to the contact plug in the first wiring,
The semiconductor device, wherein the first gate electrode does not protrude from the first sidewall. The semiconductor device according to claim 3.
The height of the portion of the first sidewall formed on the side surface of the portion where the protruding portion is provided in the first wiring is the height of the portion formed on the side surface of the first gate electrode. A semiconductor device characterized by being lower than a height. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device according to claim 1, wherein the first gate wiring is formed on the active region via a first gate insulating film. The semiconductor device according to any one of claims 1 to 5,
A second gate wiring formed on the semiconductor substrate and spaced from the first gate wiring and fully silicided;
A second gate insulating film formed on a lower portion of the second gate wiring on the active region;
An insulating second sidewall formed on a side surface of the second gate wiring;
The semiconductor device, wherein the impurity diffusion layer is a source / drain region formed in a region between the second gate wiring and the first gate wiring in the active region. The semiconductor device according to claim 6.
The source / drain region includes a first diffusion layer formed in a region of the active region at a side of the second gate wiring, and the second gate compared to the first diffusion layer in the active region. A second diffusion layer formed at a position away from the wiring and deeper than the first diffusion layer,
The semiconductor device, wherein the contact plug is electrically connected to the second diffusion layer. The semiconductor device according to claim 6 or 7,
The second gate wiring includes a second gate electrode and a second wiring formed integrally with the second gate electrode,
The semiconductor device, wherein the second gate electrode is formed on the second gate insulating film and does not protrude from the second sidewall. The semiconductor device according to any one of claims 1 to 8,
The semiconductor device, wherein the first gate wiring is made of nickel silicide. The semiconductor device according to claim 1,
A semiconductor device, further comprising a base protective film formed between the interlayer insulating film and the semiconductor substrate. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the contact plug is electrically connected to the impurity diffusion layer through a silicide layer. Forming an element isolation region in a semiconductor substrate and forming an active region surrounded by the element isolation region in the semiconductor substrate;
(B) forming a first gate wiring formation film made of a semiconductor material containing silicon on the semiconductor substrate after the step (a);
Forming an insulating first sidewall on the side surface of the first gate wiring formation film;
A step (d) of forming an impurity diffusion layer in the active region after the step (b);
After the step (c) and the step (d), the step (e) of forming the first gate wiring by fully siliciding the first gate wiring formation film;
A step (f) of forming an interlayer insulating film on the entire surface of the semiconductor substrate after the step (e);
Etching the interlayer insulating film to form an opening in a region straddling part of the first gate wiring and part of the impurity diffusion layer;
And (h) forming a contact plug electrically connected to the first gate wiring and the impurity diffusion layer by filling the opening with a conductive material,
In the step (e), a protruding portion protruding from the first sidewall is formed in a portion of the first gate wiring connected to the contact plug. In the manufacturing method of the semiconductor device according to claim 12,
In the step (e), the protruding portion of the first gate wiring is formed so as to cover a part of the upper surface of the first sidewall. In the manufacturing method of the semiconductor device according to claim 12 or 13,
In the step (e), the first gate wiring in which the first gate electrode and the first wiring are integrally formed from the first gate wiring forming film is formed,
Between the step (d) and the step (e), a portion to be the first gate electrode in the first gate wiring formation film is etched, and the first gate wiring formation film in the first gate wiring formation film is etched. A step (i) of further reducing a film thickness of a portion to be a gate electrode of a portion of the gate wiring formation film to be smaller than a film thickness of a portion of the first wiring in which the protruding portion is formed;
In the step (e), the first gate electrode does not protrude from the first side wall. In the manufacturing method of the semiconductor device according to claim 14,
In the step (i), a film thickness of a portion of the first gate wiring formation film that becomes the projecting portion of the first wiring is set to a half or more of a height of the first sidewall. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 14 or 15,
In the step (i), a film thickness of a portion to be the first gate electrode in the first gate wiring formation film is set to be less than a half of a height of the first sidewall. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to any one of claims 14 to 16,
Between the step (i) and the step (e), the height of the sidewall formed on the side surface of the portion of the first gate wiring formation film that becomes the protruding portion of the first wiring Further comprising a step (j) of lowering the height than the height of the first sidewall formed on the side surface of the portion to be the first gate electrode in the first gate wiring formation film. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 17,
In the step (j), the height of the first sidewall is made lower than the height of the upper surface of the first gate wiring formation film in the region where the protrusion is formed. Manufacturing method. The method of manufacturing a semiconductor device according to any one of claims 12 to 18,
Between the step (e) and the step (f), the method further comprises a step (k) of forming a base protective film on the entire surface of the semiconductor substrate,
In the step (f), the interlayer insulating film is formed on the base insulating film. In the manufacturing method of the semiconductor device of any one of Claims 12-19,
In the step (b), a second gate wiring formation film made of a semiconductor material containing silicon is formed on the semiconductor substrate at a distance from the first gate wiring formation film,
In the step (c), an insulating second sidewall is formed on a side surface of the second gate wiring formation film,
In the step (d), the impurity diffusion layer is formed in a region lateral to the second gate wiring formation film in the active region,
In the step (e), the second gate wiring formation film is fully silicided to form a second gate wiring. The method for manufacturing a semiconductor device according to claim 20 comprises:
A step (l) of forming a gate insulating film on the active region between the step (a) and the step (b);
In the step (b), the first gate wiring formation film and the second gate wiring formation film are formed on the active region via the gate insulating film.

Images